[NFC][AArch64] neon-abd.ll - remove unnecessary entry labels to reduce diff size in #186659 (#189690)
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Simon Pilgrim
GitHub
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6477f3aa16
commit
728de262fc
@ -557,13 +557,12 @@ define <2 x i32> @combine_sabd_2s_zerosign_negative(<2 x i32> %a, <2 x i32> %b)
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; select pattern with constant and type shrinking
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define <8 x i32> @sabd_8h_splat_imm(<8 x i16> %a) {
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; CHECK-LABEL: sabd_8h_splat_imm:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.4h, #89
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; CHECK-NEXT: movi v1.8h, #89
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; CHECK-NEXT: sabdl2 v1.4s, v0.8h, v1.8h
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; CHECK-NEXT: sabdl v0.4s, v0.4h, v2.4h
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; CHECK-NEXT: ret
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entry:
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%conv = sext <8 x i16> %a to <8 x i32>
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%sub = sub <8 x i32> %conv, splat(i32 89)
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%cmp.i = icmp slt <8 x i32> %sub, splat(i32 0)
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@ -577,13 +576,12 @@ entry:
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; ... with uabd
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define <8 x i32> @uabd_8h_splat_imm(<8 x i16> %a) {
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; CHECK-LABEL: uabd_8h_splat_imm:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.4h, #89
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; CHECK-NEXT: movi v1.8h, #89
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; CHECK-NEXT: uabdl2 v1.4s, v0.8h, v1.8h
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; CHECK-NEXT: uabdl v0.4s, v0.4h, v2.4h
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; CHECK-NEXT: ret
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entry:
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%conv = zext <8 x i16> %a to <8 x i32>
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%sub = sub <8 x i32> %conv, splat(i32 89)
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%cmp.i = icmp slt <8 x i32> %sub, splat(i32 0)
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@ -597,7 +595,7 @@ entry:
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; And now it's buildvector of const
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define <8 x i32> @sabd_8h_bv_imm(<8 x i16> %a) {
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; CHECK-LABEL: sabd_8h_bv_imm:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x9, #549747425280 // =0x7fff800000
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: adrp x8, .LCPI45_0
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@ -607,7 +605,6 @@ define <8 x i32> @sabd_8h_bv_imm(<8 x i16> %a) {
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; CHECK-NEXT: sabdl v0.4s, v0.4h, v2.4h
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; CHECK-NEXT: sabdl v1.4s, v1.4h, v3.4h
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; CHECK-NEXT: ret
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entry:
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%conv = sext <8 x i16> %a to <8 x i32>
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%sub = sub <8 x i32> %conv, <i32 39, i32 42, i32 51, i32 51, i32 0, i32 -128, i32 127, i32 69>
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%cmp.i = icmp slt <8 x i32> %sub, splat(i32 0)
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@ -621,7 +618,7 @@ entry:
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; ... uabd version
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define <8 x i32> @uabd_8h_bv_imm(<8 x i16> %a) {
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; CHECK-LABEL: uabd_8h_bv_imm:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: adrp x8, .LCPI46_0
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; CHECK-NEXT: adrp x9, .LCPI46_1
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@ -630,7 +627,6 @@ define <8 x i32> @uabd_8h_bv_imm(<8 x i16> %a) {
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; CHECK-NEXT: uabdl v0.4s, v0.4h, v3.4h
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; CHECK-NEXT: uabdl v1.4s, v1.4h, v2.4h
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; CHECK-NEXT: ret
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entry:
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%conv = zext <8 x i16> %a to <8 x i32>
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%sub = sub <8 x i32> %conv, <i32 39, i32 42, i32 51, i32 51, i32 0, i32 64000, i32 127, i32 69>
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%cmp.i = icmp slt <8 x i32> %sub, splat(i32 0)
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@ -644,7 +640,7 @@ entry:
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; And now it's buildvector with sext and constants
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define <4 x i32> @sabd_4h_bv_non_imm(<4 x i16> %a, i16 %b) {
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; CHECK-LABEL: sabd_4h_bv_non_imm:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxth w9, w0
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; CHECK-NEXT: mov w8, #-128 // =0xffffff80
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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@ -656,7 +652,6 @@ define <4 x i32> @sabd_4h_bv_non_imm(<4 x i16> %a, i16 %b) {
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; CHECK-NEXT: mov v1.s[3], w8
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; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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%conv = sext <4 x i16> %a to <4 x i32>
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%exted.b = sext i16 %b to i32
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%ze.vec = insertelement <4 x i32> <i32 poison, i32 -128, i32 42, i32 69>, i32 %exted.b, i32 0
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@ -672,7 +667,7 @@ entry:
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; ... uabd
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define <4 x i32> @uabd_4h_bv_non_imm(<4 x i16> %a, i16 %b) {
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; CHECK-LABEL: uabd_4h_bv_non_imm:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w0, #0xffff
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; CHECK-NEXT: mov w8, #64000 // =0xfa00
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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@ -684,7 +679,6 @@ define <4 x i32> @uabd_4h_bv_non_imm(<4 x i16> %a, i16 %b) {
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; CHECK-NEXT: mov v1.s[3], w8
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; CHECK-NEXT: uabd v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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entry:
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%conv = zext <4 x i16> %a to <4 x i32>
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%exted.b = zext i16 %b to i32
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%ze.vec = insertelement <4 x i32> <i32 poison, i32 64000, i32 13, i32 37>, i32 %exted.b, i32 0
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@ -700,7 +694,7 @@ entry:
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; negative: immediate wont fit in signed i16
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define <8 x i32> @sabd_8s_splat_imm_no_shrink(<8 x i16> %a) {
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; CHECK-LABEL: sabd_8s_splat_imm_no_shrink:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #250, lsl #8
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; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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@ -709,7 +703,6 @@ define <8 x i32> @sabd_8s_splat_imm_no_shrink(<8 x i16> %a) {
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; CHECK-NEXT: bic v1.4s, #3, lsl #16
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; CHECK-NEXT: bic v0.4s, #3, lsl #16
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; CHECK-NEXT: ret
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entry:
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%conv = sext <8 x i16> %a to <8 x i32>
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%sub = sub <8 x i32> %conv, splat(i32 64000)
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%cmp.i = icmp slt <8 x i32> %sub, splat(i32 0)
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@ -723,7 +716,7 @@ entry:
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; negative: value out of range of unsigned i16
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define <8 x i32> @uabd_8s_splat_imm_no_shrink(<8 x i16> %a) {
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; CHECK-LABEL: uabd_8s_splat_imm_no_shrink:
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; CHECK: // %bb.0: // %entry
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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@ -733,7 +726,6 @@ define <8 x i32> @uabd_8s_splat_imm_no_shrink(<8 x i16> %a) {
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; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
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; CHECK-NEXT: ret
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entry:
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%conv = zext <8 x i16> %a to <8 x i32>
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%sub = sub <8 x i32> %conv, splat(i32 -1)
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%cmp.i = icmp slt <8 x i32> %sub, splat(i32 0)
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