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[BOLT] Use range-based implicit def/use accessors. NFCI

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This commit is contained in:
Benjamin Kramer 2023-01-24 23:11:23 +01:00
parent d7043e8c41
commit 7557b83aa5
3 changed files with 21 additions and 34 deletions
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6
bolt/include/bolt/Passes/LivenessAnalysis.h
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@ -142,10 +142,8 @@ protected:
Used |= BC.MIB->getAliases(Point.getOperand(I).getReg(), Used |= BC.MIB->getAliases(Point.getOperand(I).getReg(),
/*OnlySmaller=*/false); /*OnlySmaller=*/false);
} }
for (auto I = InstInfo.getImplicitUses(), for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
E = InstInfo.getImplicitUses() + InstInfo.getNumImplicitUses(); Used |= BC.MIB->getAliases(ImplicitUse, false);
I != E; ++I)
Used |= BC.MIB->getAliases(*I, false);
if (IsCall && if (IsCall &&
(!BC.MIB->isTailCall(Point) || !BC.MIB->isConditionalBranch(Point))) { (!BC.MIB->isTailCall(Point) || !BC.MIB->isConditionalBranch(Point))) {
// Never gen FLAGS from a non-conditional call... this is overly // Never gen FLAGS from a non-conditional call... this is overly

35
bolt/lib/Core/MCPlusBuilder.cpp
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@ -328,9 +328,8 @@ void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); for (MCPhysReg ImplicitDef : InstInfo.implicit_defs())
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) Regs |= getAliases(ImplicitDef, /*OnlySmaller=*/false);
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) { for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
const MCOperand &Operand = Inst.getOperand(I); const MCOperand &Operand = Inst.getOperand(I);
@ -345,12 +344,10 @@ void MCPlusBuilder::getTouchedRegs(const MCInst &Inst, BitVector &Regs) const {
const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); for (MCPhysReg ImplicitDef : InstInfo.implicit_defs())
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) Regs |= getAliases(ImplicitDef, /*OnlySmaller=*/false);
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false); for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses(); Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/false);
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) { for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
if (!Inst.getOperand(I).isReg()) if (!Inst.getOperand(I).isReg())
@ -365,9 +362,8 @@ void MCPlusBuilder::getWrittenRegs(const MCInst &Inst, BitVector &Regs) const {
const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); for (MCPhysReg ImplicitDef : InstInfo.implicit_defs())
for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) Regs |= getAliases(ImplicitDef, /*OnlySmaller=*/true);
Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) { for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
const MCOperand &Operand = Inst.getOperand(I); const MCOperand &Operand = Inst.getOperand(I);
@ -382,9 +378,8 @@ void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses(); for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/true);
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) { for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
if (!Inst.getOperand(I).isReg()) if (!Inst.getOperand(I).isReg())
@ -415,9 +410,8 @@ void MCPlusBuilder::getSrcRegs(const MCInst &Inst, BitVector &Regs) const {
const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses(); for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/true);
Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
for (unsigned I = InstInfo.getNumDefs(), E = InstInfo.getNumOperands(); for (unsigned I = InstInfo.getNumDefs(), E = InstInfo.getNumOperands();
I != E; ++I) { I != E; ++I) {
@ -438,9 +432,8 @@ bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
if (MI.getOperand(I).isReg() && if (MI.getOperand(I).isReg() &&
RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg())) RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
return true; return true;
if (const uint16_t *ImpUses = InstInfo.ImplicitUses) { for (MCPhysReg ImplicitUse : InstInfo.implicit_uses()) {
for (; *ImpUses; ++ImpUses) if (ImplicitUse == Reg || RegInfo->isSubRegister(Reg, ImplicitUse))
if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
return true; return true;
} }
return false; return false;

12
bolt/lib/Passes/RegReAssign.cpp
View File

@ -146,23 +146,19 @@ void RegReAssign::rankRegisters(BinaryFunction &Function) {
const MCInstrDesc &Desc = BC.MII->get(Inst.getOpcode()); const MCInstrDesc &Desc = BC.MII->get(Inst.getOpcode());
// Disallow substituitions involving regs in implicit uses lists // Disallow substituitions involving regs in implicit uses lists
const MCPhysReg *ImplicitUses = Desc.getImplicitUses(); for (MCPhysReg ImplicitUse : Desc.implicit_uses()) {
while (ImplicitUses && *ImplicitUses) {
const size_t RegEC = const size_t RegEC =
BC.MIB->getAliases(*ImplicitUses, false).find_first(); BC.MIB->getAliases(ImplicitUse, false).find_first();
RegScore[RegEC] = RegScore[RegEC] =
std::numeric_limits<decltype(RegScore)::value_type>::min(); std::numeric_limits<decltype(RegScore)::value_type>::min();
++ImplicitUses;
} }
// Disallow substituitions involving regs in implicit defs lists // Disallow substituitions involving regs in implicit defs lists
const MCPhysReg *ImplicitDefs = Desc.getImplicitDefs(); for (MCPhysReg ImplicitDef : Desc.implicit_defs()) {
while (ImplicitDefs && *ImplicitDefs) {
const size_t RegEC = const size_t RegEC =
BC.MIB->getAliases(*ImplicitDefs, false).find_first(); BC.MIB->getAliases(ImplicitDef, false).find_first();
RegScore[RegEC] = RegScore[RegEC] =
std::numeric_limits<decltype(RegScore)::value_type>::min(); std::numeric_limits<decltype(RegScore)::value_type>::min();
++ImplicitDefs;
} }
for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) {