[BOLT] Use range-based implicit def/use accessors. NFCI
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@ -142,10 +142,8 @@ protected:
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Used |= BC.MIB->getAliases(Point.getOperand(I).getReg(),
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/*OnlySmaller=*/false);
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}
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for (auto I = InstInfo.getImplicitUses(),
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E = InstInfo.getImplicitUses() + InstInfo.getNumImplicitUses();
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I != E; ++I)
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Used |= BC.MIB->getAliases(*I, false);
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for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
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Used |= BC.MIB->getAliases(ImplicitUse, false);
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if (IsCall &&
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(!BC.MIB->isTailCall(Point) || !BC.MIB->isConditionalBranch(Point))) {
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// Never gen FLAGS from a non-conditional call... this is overly
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@ -328,9 +328,8 @@ void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I)
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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for (MCPhysReg ImplicitDef : InstInfo.implicit_defs())
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Regs |= getAliases(ImplicitDef, /*OnlySmaller=*/false);
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const MCOperand &Operand = Inst.getOperand(I);
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@ -345,12 +344,10 @@ void MCPlusBuilder::getTouchedRegs(const MCInst &Inst, BitVector &Regs) const {
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I)
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
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for (MCPhysReg ImplicitDef : InstInfo.implicit_defs())
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Regs |= getAliases(ImplicitDef, /*OnlySmaller=*/false);
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for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
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Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/false);
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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@ -365,9 +362,8 @@ void MCPlusBuilder::getWrittenRegs(const MCInst &Inst, BitVector &Regs) const {
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I)
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
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for (MCPhysReg ImplicitDef : InstInfo.implicit_defs())
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Regs |= getAliases(ImplicitDef, /*OnlySmaller=*/true);
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const MCOperand &Operand = Inst.getOperand(I);
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@ -382,9 +378,8 @@ void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
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Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/true);
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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@ -415,9 +410,8 @@ void MCPlusBuilder::getSrcRegs(const MCInst &Inst, BitVector &Regs) const {
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const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode());
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const MCPhysReg *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I)
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
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Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/true);
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for (unsigned I = InstInfo.getNumDefs(), E = InstInfo.getNumOperands();
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I != E; ++I) {
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@ -438,10 +432,9 @@ bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
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if (MI.getOperand(I).isReg() &&
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RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
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return true;
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if (const uint16_t *ImpUses = InstInfo.ImplicitUses) {
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for (; *ImpUses; ++ImpUses)
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if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
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return true;
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for (MCPhysReg ImplicitUse : InstInfo.implicit_uses()) {
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if (ImplicitUse == Reg || RegInfo->isSubRegister(Reg, ImplicitUse))
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return true;
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}
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return false;
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}
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@ -146,23 +146,19 @@ void RegReAssign::rankRegisters(BinaryFunction &Function) {
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const MCInstrDesc &Desc = BC.MII->get(Inst.getOpcode());
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// Disallow substituitions involving regs in implicit uses lists
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const MCPhysReg *ImplicitUses = Desc.getImplicitUses();
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while (ImplicitUses && *ImplicitUses) {
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for (MCPhysReg ImplicitUse : Desc.implicit_uses()) {
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const size_t RegEC =
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BC.MIB->getAliases(*ImplicitUses, false).find_first();
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BC.MIB->getAliases(ImplicitUse, false).find_first();
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RegScore[RegEC] =
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std::numeric_limits<decltype(RegScore)::value_type>::min();
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++ImplicitUses;
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}
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// Disallow substituitions involving regs in implicit defs lists
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const MCPhysReg *ImplicitDefs = Desc.getImplicitDefs();
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while (ImplicitDefs && *ImplicitDefs) {
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for (MCPhysReg ImplicitDef : Desc.implicit_defs()) {
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const size_t RegEC =
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BC.MIB->getAliases(*ImplicitDefs, false).find_first();
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BC.MIB->getAliases(ImplicitDef, false).find_first();
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RegScore[RegEC] =
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std::numeric_limits<decltype(RegScore)::value_type>::min();
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++ImplicitDefs;
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}
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for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) {
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