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[RISCV] Don't use li+sh3add for constants that can use lui+add.

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If we're adding a constant that can't use addi we try a few tricks,
one of which is using li+sh3add. We should not do this if lui+add
would work. For example adding 8192. Using sh3add prevents folding
a sext.w to form addw, thus increasing instruction count.
This commit is contained in:
Craig Topper 2022-08-05 12:41:28 -07:00
parent 4b8db17c32
commit 75c64c7c4e
3 changed files with 36 additions and 4 deletions
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8
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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@ -237,17 +237,17 @@ def CSImm12MulBy4 : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
int64_t C = N->getSExtValue();
// Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
return !isInt<13>(C) && isShiftedInt<12, 2>(C);
// Skip if C is simm12, an lui, or can be optimized by the PatLeaf AddiPair.
return !isInt<13>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 2>(C);
}]>;
def CSImm12MulBy8 : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
int64_t C = N->getSExtValue();
// Skip if C is simm12 or can be optimized by the PatLeaf AddiPair or
// Skip if C is simm12, an lui or can be optimized by the PatLeaf AddiPair or
// CSImm12MulBy4.
return !isInt<14>(C) && isShiftedInt<12, 3>(C);
return !isInt<14>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 3>(C);
}]>;
def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{

10
llvm/test/CodeGen/RISCV/rv32zba.ll
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@ -561,6 +561,16 @@ define i32 @add8208(i32 %a) {
ret i32 %c
}
define i32 @add8192(i32 %a) {
; CHECK-LABEL: add8192:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: ret
%c = add i32 %a, 8192
ret i32 %c
}
define i32 @addshl_5_6(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_6:
; RV32I: # %bb.0:

22
llvm/test/CodeGen/RISCV/rv64zba.ll
View File

@ -1116,6 +1116,28 @@ define i64 @add8208(i64 %a) {
ret i64 %c
}
; Make sure we prefer LUI for the 8192 instead of using sh3add.
define signext i32 @add8192_i32(i32 signext %a) {
; CHECK-LABEL: add8192_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 2
; CHECK-NEXT: addw a0, a0, a1
; CHECK-NEXT: ret
%c = add i32 %a, 8192
ret i32 %c
}
; Make sure we prefer LUI for the 8192 instead of using sh3add.
define i64 @add8192(i64 %a) {
; CHECK-LABEL: add8192:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: ret
%c = add i64 %a, 8192
ret i64 %c
}
define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_6:
; RV64I: # %bb.0: