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[AArch64] Fix v1fx patterns for Floating-point Multiply Extend and Floating-point Compare to Zero.

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llvm-svn: 197403
This commit is contained in:
Chad Rosier 2013-12-16 18:29:54 +00:00
parent 5f87edb484
commit 75df5680fe
2 changed files with 30 additions and 1 deletions
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7
clang/test/CodeGen/aarch64-neon-intrinsics.c
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@ -3110,7 +3110,6 @@ int32x4_t test_vqrdmulhq_s32(int32x4_t a, int32x4_t b) {
// CHECK: sqrdmulh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
}
float32x2_t test_vmulx_f32(float32x2_t a, float32x2_t b) {
// CHECK: test_vmulx_f32
return vmulx_f32(a, b);
@ -5694,6 +5693,12 @@ float64_t test_vmulxd_f64(float64_t a, float64_t b) {
// CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
}
float64x1_t test_vmulx_f64(float64x1_t a, float64x1_t b) {
// CHECK: test_vmulx_f64
return vmulx_f64(a, b);
// CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
}
float32_t test_vrecpss_f32(float32_t a, float32_t b) {
// CHECK: test_vrecpss_f32
return vrecpss_f32(a, b);

24
clang/test/CodeGen/aarch64-neon-misc.c
View File

@ -204,6 +204,12 @@ uint32x2_t test_vcgez_f32(float32x2_t a) {
return vcgez_f32(a);
}
// CHECK: test_vcgez_f64
// CHECK: fcmge {{d[0-9]+}}, {{d[0-9]+}}, #0
uint64x1_t test_vcgez_f64(float64x1_t a) {
return vcgez_f64(a);
}
// CHECK: test_vcgezq_f32
// CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
uint32x4_t test_vcgezq_f32(float32x4_t a) {
@ -270,6 +276,12 @@ uint32x2_t test_vclez_f32(float32x2_t a) {
return vclez_f32(a);
}
// CHECK: test_vclez_f64
// CHECK: fcmle {{d[0-9]+}}, {{d[0-9]+}}, #0
uint64x1_t test_vclez_f64(float64x1_t a) {
return vclez_f64(a);
}
// CHECK: test_vclezq_f32
// CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
uint32x4_t test_vclezq_f32(float32x4_t a) {
@ -336,6 +348,12 @@ uint32x2_t test_vcgtz_f32(float32x2_t a) {
return vcgtz_f32(a);
}
// CHECK: test_vcgtz_f64
// CHECK: fcmgt {{d[0-9]+}}, {{d[0-9]+}}, #0
uint64x1_t test_vcgtz_f64(float64x1_t a) {
return vcgtz_f64(a);
}
// CHECK: test_vcgtzq_f32
// CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
uint32x4_t test_vcgtzq_f32(float32x4_t a) {
@ -401,6 +419,12 @@ uint64x2_t test_vcltzq_s64(int64x2_t a) {
uint32x2_t test_vcltz_f32(float32x2_t a) {
return vcltz_f32(a);
}
// CHECK: test_vcltz_f64
// CHECK: fcmlt {{d[0-9]+}}, {{d[0-9]+}}, #0
uint64x1_t test_vcltz_f64(float64x1_t a) {
return vcltz_f64(a);
}
// CHECK: test_vcltzq_f32
// CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0