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[RISCV][NFC] Simplify the vector pipe names in SiFive7 sched model (#181268)

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Instead of creating a `VA` for single vector pipe configuration (e.g.
X280) and `VA1` + `VA2` for dual vector pipes ones (e.g. X390), we could
have just use `VA1` in the former case to simplify the related name
aliases.

NFC.
This commit is contained in:
Min-Yih Hsu 2026-02-12 16:13:53 -08:00 committed by GitHub
parent d55219bbe3
commit 77efa4af20
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GPG Key ID: B5690EEEBB952194
11 changed files with 1834 additions and 1838 deletions
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32
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -279,13 +279,11 @@ multiclass SiFive7ProcResources<bit dualVALU = false> {
def FDiv : ProcResource<1>; // FP Division/Sqrt
// Arithmetic sequencer(s)
// VA1 can handle any vector airthmetic instruction.
def VA1 : ProcResource<1>;
if dualVALU then {
// VA1 can handle any vector airthmetic instruction.
def VA1 : ProcResource<1>;
// VA2 generally can only handle simple vector arithmetic.
def VA2 : ProcResource<1>;
} else {
def VA : ProcResource<1>;
}
def VL : ProcResource<1>; // Load sequencer
@ -1554,21 +1552,19 @@ multiclass SiFive7SchedResources<int vlen, bit dualVALU,
defm SiFive7 : SiFive7ProcResources<dualVALU>;
// Pull out defs from SiFive7ProcResources so we can refer to them by name.
defvar SiFive7PipeA = !cast<ProcResource>(NAME # SiFive7PipeA);
defvar SiFive7PipeB = !cast<ProcResource>(NAME # SiFive7PipeB);
defvar SiFive7PipeAB = !cast<ProcResGroup>(NAME # SiFive7PipeAB);
defvar SiFive7IDiv = !cast<ProcResource>(NAME # SiFive7IDiv);
defvar SiFive7FDiv = !cast<ProcResource>(NAME # SiFive7FDiv);
// Pass SiFive7VA for VA1 and VA1OrVA2 if there is only 1 VALU.
defvar SiFive7VA1 = !if (dualVALU,
!cast<ProcResource>(NAME # SiFive7VA1),
!cast<ProcResource>(NAME # SiFive7VA));
defvar SiFive7PipeA = !cast<ProcResource>(NAME # "SiFive7PipeA");
defvar SiFive7PipeB = !cast<ProcResource>(NAME # "SiFive7PipeB");
defvar SiFive7PipeAB = !cast<ProcResGroup>(NAME # "SiFive7PipeAB");
defvar SiFive7IDiv = !cast<ProcResource>(NAME # "SiFive7IDiv");
defvar SiFive7FDiv = !cast<ProcResource>(NAME # "SiFive7FDiv");
defvar SiFive7VA1 = !cast<ProcResource>(NAME # "SiFive7VA1");
// Use SiFive7VA1 for VA1OrVA2 if there is only 1 VALU.
defvar SiFive7VA1OrVA2 = !if (dualVALU,
!cast<ProcResGroup>(NAME # SiFive7VA1OrVA2),
!cast<ProcResource>(NAME # SiFive7VA));
defvar SiFive7VL = !cast<ProcResource>(NAME # SiFive7VL);
defvar SiFive7VS = !cast<ProcResource>(NAME # SiFive7VS);
defvar SiFive7VCQ = !cast<ProcResource>(NAME # SiFive7VCQ);
!cast<ProcResGroup>(NAME # "SiFive7VA1OrVA2"),
!cast<ProcResource>(NAME # "SiFive7VA1"));
defvar SiFive7VL = !cast<ProcResource>(NAME # "SiFive7VL");
defvar SiFive7VS = !cast<ProcResource>(NAME # "SiFive7VS");
defvar SiFive7VCQ = !cast<ProcResource>(NAME # "SiFive7VCQ");
// Define WriteRes records that are the same across all SiFive7 derived
// SchedModels.

6
llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
View File

@ -44,13 +44,13 @@ body: |
# CHECK-NEXT: SiFive7PipeAB | | | x | | | | | | | | | | | | | | |
# CHECK-NEXT: SU(7) | | | | | i | | | | | | | | | | | | |
# CHECK-NEXT: SiFive7VCQ | | | | | x | | | | | | | | | | | | |
# CHECK-NEXT: SiFive7VA | | | | | | x | x | x | x | | | | | | | | |
# CHECK-NEXT: SiFive7VA1 | | | | | | x | x | x | x | | | | | | | | |
# CHECK-NEXT: SU(6) | | | | | | | | | i | | | | | | | | |
# CHECK-NEXT: SiFive7VCQ | | | | | | | | | x | | | | | | | | |
# CHECK-NEXT: SiFive7VA | | | | | | | | | | x | x | x | x | | | | |
# CHECK-NEXT: SiFive7VA1 | | | | | | | | | | x | x | x | x | | | | |
# CHECK-NEXT: SU(8) | | | | | | | | | | | | | i | | | | |
# CHECK-NEXT: SiFive7VCQ | | | | | | | | | | | | | x | | | | |
# CHECK-NEXT: SiFive7VA | | | | | | | | | | | | | | x | x | x | x |
# CHECK-NEXT: SiFive7VA1 | | | | | | | | | | | | | | x | x | x | x |
# CHECK-NEXT: SU(9) | | | | | | | | | | | | | | | | | i |
# CHECK-NEXT: SiFive7PipeAB | | | | | | | | | | | | | | | | | x |

30
llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
View File

@ -40,7 +40,7 @@
# ISF-NEXT: [2] - VLEN512SiFive7PipeA:1
# ISF-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# ISF-NEXT: [4] - VLEN512SiFive7PipeB:1
# ISF-NEXT: [5] - VLEN512SiFive7VA:1
# ISF-NEXT: [5] - VLEN512SiFive7VA1:1
# ISF-NEXT: [6] - VLEN512SiFive7VCQ:1
# ISF-NEXT: [7] - VLEN512SiFive7VL:1
# ISF-NEXT: [8] - VLEN512SiFive7VS:1
@ -51,7 +51,7 @@
# ISFB-NEXT: [2] - VLEN512SiFive7PipeA:1
# ISFB-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# ISFB-NEXT: [4] - VLEN512SiFive7PipeB:1
# ISFB-NEXT: [5] - VLEN512SiFive7VA:1
# ISFB-NEXT: [5] - VLEN512SiFive7VA1:1
# ISFB-NEXT: [6] - VLEN512SiFive7VCQ:1
# ISFB-NEXT: [7] - VLEN512SiFive7VL:1
# ISFB-NEXT: [8] - VLEN512SiFive7VS:1
@ -62,7 +62,7 @@
# ISFBE-NEXT: [2] - VLEN512SiFive7PipeA:1
# ISFBE-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# ISFBE-NEXT: [4] - VLEN512SiFive7PipeB:1
# ISFBE-NEXT: [5] - VLEN512SiFive7VA:1
# ISFBE-NEXT: [5] - VLEN512SiFive7VA1:1
# ISFBE-NEXT: [6] - VLEN512SiFive7VCQ:1
# ISFBE-NEXT: [7] - VLEN512SiFive7VL:1
# ISFBE-NEXT: [8] - VLEN512SiFive7VS:1
@ -73,7 +73,7 @@
# ISFE-NEXT: [2] - VLEN512SiFive7PipeA:1
# ISFE-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# ISFE-NEXT: [4] - VLEN512SiFive7PipeB:1
# ISFE-NEXT: [5] - VLEN512SiFive7VA:1
# ISFE-NEXT: [5] - VLEN512SiFive7VA1:1
# ISFE-NEXT: [6] - VLEN512SiFive7VCQ:1
# ISFE-NEXT: [7] - VLEN512SiFive7VL:1
# ISFE-NEXT: [8] - VLEN512SiFive7VS:1
@ -260,7 +260,7 @@
# ISN-NEXT: [1] - VLEN512SiFive7IDiv
# ISN-NEXT: [2] - VLEN512SiFive7PipeA
# ISN-NEXT: [3] - VLEN512SiFive7PipeB
# ISN-NEXT: [4] - VLEN512SiFive7VA
# ISN-NEXT: [4] - VLEN512SiFive7VA1
# ISN-NEXT: [5] - VLEN512SiFive7VCQ
# ISN-NEXT: [6] - VLEN512SiFive7VL
# ISN-NEXT: [7] - VLEN512SiFive7VS
@ -270,7 +270,7 @@
# ISF-NEXT: [1] - VLEN512SiFive7IDiv
# ISF-NEXT: [2] - VLEN512SiFive7PipeA
# ISF-NEXT: [3] - VLEN512SiFive7PipeB
# ISF-NEXT: [4] - VLEN512SiFive7VA
# ISF-NEXT: [4] - VLEN512SiFive7VA1
# ISF-NEXT: [5] - VLEN512SiFive7VCQ
# ISF-NEXT: [6] - VLEN512SiFive7VL
# ISF-NEXT: [7] - VLEN512SiFive7VS
@ -280,7 +280,7 @@
# ISFB-NEXT: [1] - VLEN512SiFive7IDiv
# ISFB-NEXT: [2] - VLEN512SiFive7PipeA
# ISFB-NEXT: [3] - VLEN512SiFive7PipeB
# ISFB-NEXT: [4] - VLEN512SiFive7VA
# ISFB-NEXT: [4] - VLEN512SiFive7VA1
# ISFB-NEXT: [5] - VLEN512SiFive7VCQ
# ISFB-NEXT: [6] - VLEN512SiFive7VL
# ISFB-NEXT: [7] - VLEN512SiFive7VS
@ -290,7 +290,7 @@
# ISFBE-NEXT: [1] - VLEN512SiFive7IDiv
# ISFBE-NEXT: [2] - VLEN512SiFive7PipeA
# ISFBE-NEXT: [3] - VLEN512SiFive7PipeB
# ISFBE-NEXT: [4] - VLEN512SiFive7VA
# ISFBE-NEXT: [4] - VLEN512SiFive7VA1
# ISFBE-NEXT: [5] - VLEN512SiFive7VCQ
# ISFBE-NEXT: [6] - VLEN512SiFive7VL
# ISFBE-NEXT: [7] - VLEN512SiFive7VS
@ -300,7 +300,7 @@
# ISFE-NEXT: [1] - VLEN512SiFive7IDiv
# ISFE-NEXT: [2] - VLEN512SiFive7PipeA
# ISFE-NEXT: [3] - VLEN512SiFive7PipeB
# ISFE-NEXT: [4] - VLEN512SiFive7VA
# ISFE-NEXT: [4] - VLEN512SiFive7VA1
# ISFE-NEXT: [5] - VLEN512SiFive7VCQ
# ISFE-NEXT: [6] - VLEN512SiFive7VL
# ISFE-NEXT: [7] - VLEN512SiFive7VS
@ -310,7 +310,7 @@
# ISNB-NEXT: [1] - VLEN512SiFive7IDiv
# ISNB-NEXT: [2] - VLEN512SiFive7PipeA
# ISNB-NEXT: [3] - VLEN512SiFive7PipeB
# ISNB-NEXT: [4] - VLEN512SiFive7VA
# ISNB-NEXT: [4] - VLEN512SiFive7VA1
# ISNB-NEXT: [5] - VLEN512SiFive7VCQ
# ISNB-NEXT: [6] - VLEN512SiFive7VL
# ISNB-NEXT: [7] - VLEN512SiFive7VS
@ -320,7 +320,7 @@
# ISNBE-NEXT: [1] - VLEN512SiFive7IDiv
# ISNBE-NEXT: [2] - VLEN512SiFive7PipeA
# ISNBE-NEXT: [3] - VLEN512SiFive7PipeB
# ISNBE-NEXT: [4] - VLEN512SiFive7VA
# ISNBE-NEXT: [4] - VLEN512SiFive7VA1
# ISNBE-NEXT: [5] - VLEN512SiFive7VCQ
# ISNBE-NEXT: [6] - VLEN512SiFive7VL
# ISNBE-NEXT: [7] - VLEN512SiFive7VS
@ -330,7 +330,7 @@
# ISNE-NEXT: [1] - VLEN512SiFive7IDiv
# ISNE-NEXT: [2] - VLEN512SiFive7PipeA
# ISNE-NEXT: [3] - VLEN512SiFive7PipeB
# ISNE-NEXT: [4] - VLEN512SiFive7VA
# ISNE-NEXT: [4] - VLEN512SiFive7VA1
# ISNE-NEXT: [5] - VLEN512SiFive7VCQ
# ISNE-NEXT: [6] - VLEN512SiFive7VL
# ISNE-NEXT: [7] - VLEN512SiFive7VS
@ -340,7 +340,7 @@
# NISB-NEXT: [1] - VLEN512SiFive7IDiv
# NISB-NEXT: [2] - VLEN512SiFive7PipeA
# NISB-NEXT: [3] - VLEN512SiFive7PipeB
# NISB-NEXT: [4] - VLEN512SiFive7VA
# NISB-NEXT: [4] - VLEN512SiFive7VA1
# NISB-NEXT: [5] - VLEN512SiFive7VCQ
# NISB-NEXT: [6] - VLEN512SiFive7VL
# NISB-NEXT: [7] - VLEN512SiFive7VS
@ -350,7 +350,7 @@
# NISBE-NEXT: [1] - VLEN512SiFive7IDiv
# NISBE-NEXT: [2] - VLEN512SiFive7PipeA
# NISBE-NEXT: [3] - VLEN512SiFive7PipeB
# NISBE-NEXT: [4] - VLEN512SiFive7VA
# NISBE-NEXT: [4] - VLEN512SiFive7VA1
# NISBE-NEXT: [5] - VLEN512SiFive7VCQ
# NISBE-NEXT: [6] - VLEN512SiFive7VL
# NISBE-NEXT: [7] - VLEN512SiFive7VS
@ -360,7 +360,7 @@
# NISE-NEXT: [1] - VLEN512SiFive7IDiv
# NISE-NEXT: [2] - VLEN512SiFive7PipeA
# NISE-NEXT: [3] - VLEN512SiFive7PipeB
# NISE-NEXT: [4] - VLEN512SiFive7VA
# NISE-NEXT: [4] - VLEN512SiFive7VA1
# NISE-NEXT: [5] - VLEN512SiFive7VCQ
# NISE-NEXT: [6] - VLEN512SiFive7VL
# NISE-NEXT: [7] - VLEN512SiFive7VS

52
llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s
View File

@ -39,7 +39,7 @@ vmsof.m v8, v4
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -57,37 +57,37 @@ vmsof.m v8, v4
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, ta, ma
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v0, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSEQ_VV vmseq.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSNE_VV vmsne.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v0, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFEQ_VV vmfeq.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFNE_VV vmfne.vv v8, v4, v20
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMADC_VV vmadc.vv v8, v4, v20
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSBC_VV vmsbc.vv v8, v4, v20
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFIRST_M vfirst.m a2, v4
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VCPOP_M vcpop.m a2, v4
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VIOTA_M viota.m v8, v4
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSBF_M vmsbf.m v8, v4
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSIF_M vmsif.m v8, v4
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSOF_M vmsof.m v8, v4
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v0, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSEQ_VV vmseq.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSNE_VV vmsne.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v0, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMFEQ_VV vmfeq.vv v8, v4, v20
# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMFNE_VV vmfne.vv v8, v4, v20
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMADC_VV vmadc.vv v8, v4, v20
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMSBC_VV vmsbc.vv v8, v4, v20
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VFIRST_M vfirst.m a2, v4
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VCPOP_M vcpop.m a2, v4
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VIOTA_M viota.m v8, v4
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMSBF_M vmsbf.m v8, v4
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMSIF_M vmsif.m v8, v4
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMSOF_M vmsof.m v8, v4
# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

4
llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s
View File

@ -22,7 +22,7 @@ fsd fa5, 0(sp)
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -57,7 +57,7 @@ fsd fa5, 0(sp)
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

3120
llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
View File

File diff suppressed because it is too large Load Diff

244
llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s
View File

@ -248,7 +248,7 @@ vfmv.f.s f7, v16
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -266,244 +266,244 @@ vfmv.f.s f7, v16
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ VMV1R_V vmv1r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ VMV2R_V vmv2r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ VMV4R_V vmv4r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5
# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA1[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16
# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

136
llvm/test/tools/llvm-mca/RISCV/SiFive7/vrgather-vcompress.s
View File

@ -102,7 +102,7 @@ vcompress.vm v8, v16, v24
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -120,100 +120,100 @@ vcompress.vm v8, v16, v24
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 39 12.00 39 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 12.00 39 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 12.00 39 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 12.00 39 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA1[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
# CHECK-NEXT: 1 39 20.00 39 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 20.00 39 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 20.00 39 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 20.00 39 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA1[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
# CHECK-NEXT: 1 39 36.00 39 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 36.00 39 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 36.00 39 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 36.00 39 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA1[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, tu, mu
# CHECK-NEXT: 1 39 68.00 39 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 68.00 39 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 68.00 39 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 68.00 39 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA1[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, tu, mu
# CHECK-NEXT: 1 39 132.00 39 VLEN512SiFive7VA[1,133],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 132.00 39 VLEN512SiFive7VA[1,133],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 135 135.00 135 VLEN512SiFive7VA[1,136],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 132.00 39 VLEN512SiFive7VA1[1,133],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 132.00 39 VLEN512SiFive7VA1[1,133],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 135 135.00 135 VLEN512SiFive7VA1[1,136],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, tu, mu
# CHECK-NEXT: 1 39 260.00 39 VLEN512SiFive7VA[1,261],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 260.00 39 VLEN512SiFive7VA[1,261],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 263 263.00 263 VLEN512SiFive7VA[1,264],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 260.00 39 VLEN512SiFive7VA1[1,261],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 260.00 39 VLEN512SiFive7VA1[1,261],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 263 263.00 263 VLEN512SiFive7VA1[1,264],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, tu, mu
# CHECK-NEXT: 1 39 516.00 39 VLEN512SiFive7VA[1,517],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 516.00 39 VLEN512SiFive7VA[1,517],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 519 519.00 519 VLEN512SiFive7VA[1,520],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 39 516.00 39 VLEN512SiFive7VA1[1,517],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 39 516.00 39 VLEN512SiFive7VA1[1,517],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 519 519.00 519 VLEN512SiFive7VA1[1,520],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
# CHECK-NEXT: 1 23 12.00 23 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 12.00 23 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 23 12.00 23 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 12.00 23 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA1[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
# CHECK-NEXT: 1 23 20.00 23 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 20.00 23 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 23 20.00 23 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 20.00 23 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA1[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu
# CHECK-NEXT: 1 23 36.00 23 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 36.00 23 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 23 36.00 23 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 36.00 23 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA1[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu
# CHECK-NEXT: 1 23 68.00 23 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 68.00 23 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 23 68.00 23 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 68.00 23 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA1[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu
# CHECK-NEXT: 1 23 132.00 23 VLEN512SiFive7VA[1,133],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 132.00 23 VLEN512SiFive7VA[1,133],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 135 135.00 135 VLEN512SiFive7VA[1,136],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 23 132.00 23 VLEN512SiFive7VA1[1,133],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 132.00 23 VLEN512SiFive7VA1[1,133],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 135 135.00 135 VLEN512SiFive7VA1[1,136],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu
# CHECK-NEXT: 1 23 260.00 23 VLEN512SiFive7VA[1,261],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 260.00 23 VLEN512SiFive7VA[1,261],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 263 263.00 263 VLEN512SiFive7VA[1,264],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 23 260.00 23 VLEN512SiFive7VA1[1,261],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 23 260.00 23 VLEN512SiFive7VA1[1,261],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 263 263.00 263 VLEN512SiFive7VA1[1,264],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 15 12.00 15 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 12.00 15 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 15 12.00 15 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 12.00 15 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA1[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 15 20.00 15 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 20.00 15 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 15 20.00 15 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 20.00 15 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA1[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu
# CHECK-NEXT: 1 15 36.00 15 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 36.00 15 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 15 36.00 15 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 36.00 15 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA1[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu
# CHECK-NEXT: 1 15 68.00 15 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 68.00 15 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 15 68.00 15 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 68.00 15 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA1[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu
# CHECK-NEXT: 1 15 132.00 15 VLEN512SiFive7VA[1,133],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 132.00 15 VLEN512SiFive7VA[1,133],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 135 135.00 135 VLEN512SiFive7VA[1,136],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 15 132.00 15 VLEN512SiFive7VA1[1,133],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 15 132.00 15 VLEN512SiFive7VA1[1,133],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 135 135.00 135 VLEN512SiFive7VA1[1,136],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 11 12.00 11 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 12.00 11 VLEN512SiFive7VA[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 11 12.00 11 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 12.00 11 VLEN512SiFive7VA1[1,13],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 15 15.00 15 VLEN512SiFive7VA1[1,16],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu
# CHECK-NEXT: 1 11 20.00 11 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 20.00 11 VLEN512SiFive7VA[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 11 20.00 11 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 20.00 11 VLEN512SiFive7VA1[1,21],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 23 23.00 23 VLEN512SiFive7VA1[1,24],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu
# CHECK-NEXT: 1 11 36.00 11 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 36.00 11 VLEN512SiFive7VA[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 11 36.00 11 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 36.00 11 VLEN512SiFive7VA1[1,37],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 39 39.00 39 VLEN512SiFive7VA1[1,40],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu
# CHECK-NEXT: 1 11 68.00 11 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 68.00 11 VLEN512SiFive7VA[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK-NEXT: 1 11 68.00 11 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHER_VV vrgather.vv v8, v16, v24
# CHECK-NEXT: 1 11 68.00 11 VLEN512SiFive7VA1[1,69],VLEN512SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
# CHECK-NEXT: 1 71 71.00 71 VLEN512SiFive7VA1[1,72],VLEN512SiFive7VCQ VCOMPRESS_VM vcompress.vm v8, v16, v24
# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

14
llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s
View File

@ -23,7 +23,7 @@ sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -41,22 +41,22 @@ sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 7 1.00 7 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 7 1.00 7 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf4, ta, ma
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf2, ta, ma
# CHECK-NEXT: 1 10 4.00 10 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 10 4.00 10 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, m1, ta, ma
# CHECK-NEXT: 1 13 8.00 13 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 13 8.00 13 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, m2, ta, ma
# CHECK-NEXT: 1 19 16.00 19 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK-NEXT: 1 19 16.00 19 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

14
llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
View File

@ -19,7 +19,7 @@ sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -37,22 +37,22 @@ sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, ta, ma
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, ta, ma
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, ta, ma
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v8
# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS

20
llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
View File

@ -26,7 +26,7 @@ sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
@ -44,28 +44,28 @@ sf.vqmacc.4x8x4 v16, v0, v8
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, ta, ma
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, ta, ma
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, ta, ma
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, ta, ma
# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, ta, ma
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, ta, ma
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, ta, ma
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v8
# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
# CHECK-NEXT: [4] - VLEN512SiFive7VA
# CHECK-NEXT: [4] - VLEN512SiFive7VA1
# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
# CHECK-NEXT: [6] - VLEN512SiFive7VL
# CHECK-NEXT: [7] - VLEN512SiFive7VS