[Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 309993
This commit is contained in:
Eugene Zelenko
parent
1046aa3148
commit
79220eaeec
@ -11,6 +11,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "Mips.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCContext.h"
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@ -32,7 +33,7 @@ using namespace llvm;
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#define DEBUG_TYPE "mips-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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@ -286,10 +287,8 @@ static DecodeStatus DecodeLoadByte15(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCacheOp(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
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unsigned Insn,
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@ -367,17 +366,14 @@ static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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@ -581,7 +577,8 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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template <typename InsnType>
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static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder) {
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typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
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using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
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// The size of the n field depends on the element size
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// The register class also depends on this.
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InsnType tmp = fieldFromInstruction(insn, 17, 5);
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@ -1,4 +1,4 @@
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//===---- Mips16HardFloat.cpp for Mips16 Hard Float --------===//
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//===- Mips16HardFloat.cpp for Mips16 Hard Float --------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -25,6 +25,7 @@ using namespace llvm;
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#define DEBUG_TYPE "mips16-hard-float"
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namespace {
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class Mips16HardFloat : public ModulePass {
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public:
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static char ID;
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@ -41,21 +42,21 @@ namespace {
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bool runOnModule(Module &M) override;
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};
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static void EmitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) {
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std::vector<llvm::Type *> AsmArgTypes;
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std::vector<llvm::Value *> AsmArgs;
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} // end anonymous namespace
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llvm::FunctionType *AsmFTy =
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llvm::FunctionType::get(Type::getVoidTy(C), AsmArgTypes, false);
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llvm::InlineAsm *IA =
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llvm::InlineAsm::get(AsmFTy, AsmText, "", true,
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/* IsAlignStack */ false, llvm::InlineAsm::AD_ATT);
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CallInst::Create(IA, AsmArgs, "", BB);
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}
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static void EmitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) {
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std::vector<Type *> AsmArgTypes;
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std::vector<Value *> AsmArgs;
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char Mips16HardFloat::ID = 0;
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FunctionType *AsmFTy =
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FunctionType::get(Type::getVoidTy(C), AsmArgTypes, false);
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InlineAsm *IA = InlineAsm::get(AsmFTy, AsmText, "", true,
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/* IsAlignStack */ false, InlineAsm::AD_ATT);
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CallInst::Create(IA, AsmArgs, "", BB);
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}
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char Mips16HardFloat::ID = 0;
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//
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// Return types that matter for hard float are:
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// float, double, complex float, and complex double
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@ -89,18 +90,15 @@ static FPReturnVariant whichFPReturnVariant(Type *T) {
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return NoFPRet;
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}
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//
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// Parameter type that matter are float, (float, float), (float, double),
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// double, (double, double), (double, float)
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//
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enum FPParamVariant {
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FSig, FFSig, FDSig,
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DSig, DDSig, DFSig, NoSig
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};
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// which floating point parameter signature variant we are dealing with
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//
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typedef Type::TypeID TypeID;
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using TypeID = Type::TypeID;
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const Type::TypeID FloatTyID = Type::FloatTyID;
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const Type::TypeID DoubleTyID = Type::DoubleTyID;
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@ -154,7 +152,6 @@ static FPParamVariant whichFPParamVariantNeeded(Function &F) {
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// Figure out if we need float point based on the function parameters.
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// We need to move variables in and/or out of floating point
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// registers because of the ABI
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//
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static bool needsFPStubFromParams(Function &F) {
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if (F.arg_size() >=1) {
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Type *ArgType = F.getFunctionType()->getParamType(0);
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@ -183,10 +180,8 @@ static bool needsFPHelperFromSig(Function &F) {
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return needsFPStubFromParams(F) || needsFPReturnHelper(F);
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}
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//
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// We swap between FP and Integer registers to allow Mips16 and Mips32 to
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// interoperate
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//
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static std::string swapFPIntParams(FPParamVariant PV, Module *M, bool LE,
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bool ToFP) {
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std::string MI = ToFP ? "mtc1 ": "mfc1 ";
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@ -255,10 +250,8 @@ static std::string swapFPIntParams(FPParamVariant PV, Module *M, bool LE,
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return AsmText;
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}
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//
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// Make sure that we know we already need a stub for this function.
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// Having called needsFPHelperFromSig
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//
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static void assureFPCallStub(Function &F, Module *M,
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const MipsTargetMachine &TM) {
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// for now we only need them for static relocation
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@ -277,9 +270,9 @@ static void assureFPCallStub(Function &F, Module *M,
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FStub = Function::Create(F.getFunctionType(),
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Function::InternalLinkage, StubName, M);
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FStub->addFnAttr("mips16_fp_stub");
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FStub->addFnAttr(llvm::Attribute::Naked);
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FStub->addFnAttr(llvm::Attribute::NoInline);
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FStub->addFnAttr(llvm::Attribute::NoUnwind);
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FStub->addFnAttr(Attribute::Naked);
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FStub->addFnAttr(Attribute::NoInline);
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FStub->addFnAttr(Attribute::NoUnwind);
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FStub->addFnAttr("nomips16");
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FStub->setSection(SectionName);
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BasicBlock *BB = BasicBlock::Create(Context, "entry", FStub);
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@ -350,9 +343,7 @@ static void assureFPCallStub(Function &F, Module *M,
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new UnreachableInst(Context, BB);
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}
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//
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// Functions that are llvm intrinsics and don't need helpers.
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//
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static const char *const IntrinsicInline[] = {
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"fabs", "fabsf",
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"llvm.ceil.f32", "llvm.ceil.f64",
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@ -379,10 +370,9 @@ static bool isIntrinsicInline(Function *F) {
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return std::binary_search(std::begin(IntrinsicInline),
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std::end(IntrinsicInline), F->getName());
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}
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//
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// Returns of float, double and complex need to be handled with a helper
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// function.
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//
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static bool fixupFPReturnAndCall(Function &F, Module *M,
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const MipsTargetMachine &TM) {
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bool Modified = false;
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@ -465,9 +455,9 @@ static void createFPFnStub(Function *F, Module *M, FPParamVariant PV,
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(F->getFunctionType(),
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Function::InternalLinkage, StubName, M);
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FStub->addFnAttr("mips16_fp_stub");
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FStub->addFnAttr(llvm::Attribute::Naked);
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FStub->addFnAttr(llvm::Attribute::NoUnwind);
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FStub->addFnAttr(llvm::Attribute::NoInline);
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FStub->addFnAttr(Attribute::Naked);
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FStub->addFnAttr(Attribute::NoUnwind);
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FStub->addFnAttr(Attribute::NoInline);
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FStub->addFnAttr("nomips16");
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FStub->setSection(SectionName);
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BasicBlock *BB = BasicBlock::Create(Context, "entry", FStub);
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@ -489,9 +479,7 @@ static void createFPFnStub(Function *F, Module *M, FPParamVariant PV,
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new UnreachableInst(FStub->getContext(), BB);
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}
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//
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// remove the use-soft-float attribute
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//
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static void removeUseSoftFloat(Function &F) {
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AttrBuilder B;
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DEBUG(errs() << "removing -use-soft-float\n");
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@ -503,8 +491,6 @@ static void removeUseSoftFloat(Function &F) {
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F.addAttributes(AttributeList::FunctionIndex, B);
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}
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//
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// This pass only makes sense when the underlying chip has floating point but
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// we are compiling as mips16.
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// For all mips16 functions (that are not stubs we have already generated), or
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@ -521,7 +507,6 @@ static void removeUseSoftFloat(Function &F) {
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// 4) TBD. For pic, calls to extern functions of unknown type are handled by
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// predefined helper functions in libc but this work is currently done
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// during call lowering but it should be moved here in the future.
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//
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bool Mips16HardFloat::runOnModule(Module &M) {
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auto &TM = static_cast<const MipsTargetMachine &>(
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getAnalysis<TargetPassConfig>().getTM<TargetMachine>());
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@ -545,7 +530,6 @@ bool Mips16HardFloat::runOnModule(Module &M) {
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return Modified;
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}
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ModulePass *llvm::createMips16HardFloatPass() {
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return new Mips16HardFloat();
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}
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@ -1,4 +1,4 @@
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//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
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//===- Mips16InstrInfo.cpp - Mips16 Instruction Information ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -10,27 +10,38 @@
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16InstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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#include <cctype>
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#include <cstdint>
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#include <cstdlib>
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#include <cstring>
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#include <iterator>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "mips16-instrinfo"
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Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
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: MipsInstrInfo(STI, Mips::Bimm16), RI() {}
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: MipsInstrInfo(STI, Mips::Bimm16) {}
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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return RI;
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@ -71,12 +82,10 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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else if ((SrcReg == Mips::HI0) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mfhi16, SrcReg = 0;
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else if ((SrcReg == Mips::LO0) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mflo16, SrcReg = 0;
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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@ -190,6 +199,7 @@ static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
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}
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}
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}
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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@ -256,7 +266,6 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
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// This can only be called at times that we know that there is at least one free
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// register.
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// This is clearly safe at prologue and epilogue.
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//
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void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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@ -486,7 +495,6 @@ bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
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/// We implement the special case of the .space directive taking only an
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/// integer argument, which is the size in bytes. This is used for creating
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/// inline code spacing for testing purposes using inline assembly.
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///
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unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const {
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@ -1,4 +1,4 @@
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//===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
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//===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -16,9 +16,15 @@
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#include "Mips16RegisterInfo.h"
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#include "MipsInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Support/MathExtras.h"
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#include <cstdint>
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namespace llvm {
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class MCInstrDesc;
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class MipsSubtarget;
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class Mips16InstrInfo : public MipsInstrInfo {
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const Mips16RegisterInfo RI;
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@ -73,7 +79,6 @@ public:
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void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// Adjust SP by Amount bytes.
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void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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@ -81,7 +86,6 @@ public:
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/// Emit a series of instructions to load an immediate.
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// This is to adjust some FrameReg. We return the new register to be used
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// in place of FrameReg and the adjusted immediate field (&NewImm)
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//
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unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, const DebugLoc &DL,
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unsigned &NewImm) const;
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@ -92,9 +96,7 @@ public:
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return ((offset & 7) == 0) && isInt<11>(offset);
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}
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//
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// build the proper one based on the Imm field
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//
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const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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@ -118,9 +120,8 @@ private:
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void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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};
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}
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} // end namespace llvm
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#endif
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#endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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@ -1,4 +1,4 @@
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//===-- MipsAnalyzeImmediate.cpp - Analyze Immediates ---------------------===//
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//===- MipsAnalyzeImmediate.cpp - Analyze Immediates ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -6,9 +6,13 @@
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsAnalyzeImmediate.h"
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#include "Mips.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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using namespace llvm;
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@ -1,4 +1,4 @@
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//===-- MipsAnalyzeImmediate.h - Analyze Immediates ------------*- C++ -*--===//
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//===- MipsAnalyzeImmediate.h - Analyze Immediates -------------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -6,11 +6,12 @@
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSANALYZEIMMEDIATE_H
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#define LLVM_LIB_TARGET_MIPS_MIPSANALYZEIMMEDIATE_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/DataTypes.h"
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#include <cstdint>
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namespace llvm {
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@ -18,16 +19,18 @@ namespace llvm {
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public:
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struct Inst {
|
||||
unsigned Opc, ImmOpnd;
|
||||
|
||||
Inst(unsigned Opc, unsigned ImmOpnd);
|
||||
};
|
||||
typedef SmallVector<Inst, 7 > InstSeq;
|
||||
using InstSeq = SmallVector<Inst, 7>;
|
||||
|
||||
/// Analyze - Get an instruction sequence to load immediate Imm. The last
|
||||
/// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
|
||||
/// true;
|
||||
const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
|
||||
|
||||
private:
|
||||
typedef SmallVector<InstSeq, 5> InstSeqLs;
|
||||
using InstSeqLs = SmallVector<InstSeq, 5>;
|
||||
|
||||
/// AddInstr - Add I to all instruction sequences in SeqLs.
|
||||
void AddInstr(InstSeqLs &SeqLs, const Inst &I);
|
||||
@ -58,6 +61,7 @@ namespace llvm {
|
||||
unsigned ADDiu, ORi, SLL, LUi;
|
||||
InstSeq Insts;
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSANALYZEIMMEDIATE_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
|
||||
//===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -14,41 +14,55 @@
|
||||
|
||||
#include "MipsAsmPrinter.h"
|
||||
#include "InstPrinter/MipsInstPrinter.h"
|
||||
#include "MCTargetDesc/MipsABIInfo.h"
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "MCTargetDesc/MipsMCNaCl.h"
|
||||
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
||||
#include "Mips.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "MipsMCInstLower.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "MipsTargetStreamer.h"
|
||||
#include "llvm/ADT/SmallString.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/ADT/Triple.h"
|
||||
#include "llvm/ADT/Twine.h"
|
||||
#include "llvm/BinaryFormat/ELF.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineJumpTableInfo.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/IR/Attributes.h"
|
||||
#include "llvm/IR/BasicBlock.h"
|
||||
#include "llvm/IR/DataLayout.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/InlineAsm.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/IR/Mangler.h"
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
#include "llvm/MC/MCContext.h"
|
||||
#include "llvm/MC/MCELFStreamer.h"
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCInstBuilder.h"
|
||||
#include "llvm/MC/MCSection.h"
|
||||
#include "llvm/MC/MCObjectFileInfo.h"
|
||||
#include "llvm/MC/MCSectionELF.h"
|
||||
#include "llvm/MC/MCSymbol.h"
|
||||
#include "llvm/MC/MCSymbolELF.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetLoweringObjectFile.h"
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -65,11 +79,11 @@ bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
|
||||
if (Subtarget->inMips16Mode())
|
||||
for (std::map<
|
||||
const char *,
|
||||
const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
|
||||
const Mips16HardFloatInfo::FuncSignature *>::const_iterator
|
||||
it = MipsFI->StubsNeeded.begin();
|
||||
it != MipsFI->StubsNeeded.end(); ++it) {
|
||||
const char *Symbol = it->first;
|
||||
const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
|
||||
const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
|
||||
if (StubsNeeded.find(Symbol) == StubsNeeded.end())
|
||||
StubsNeeded[Symbol] = Signature;
|
||||
}
|
||||
@ -404,7 +418,7 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
|
||||
|
||||
void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) {
|
||||
MipsTargetStreamer &TS = getTargetStreamer();
|
||||
if (MBB.size() == 0)
|
||||
if (MBB.empty())
|
||||
TS.emitDirectiveInsn();
|
||||
}
|
||||
|
||||
@ -483,7 +497,7 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
||||
return true;
|
||||
O << MO.getImm() - 1;
|
||||
return false;
|
||||
case 'z': {
|
||||
case 'z':
|
||||
// $0 if zero, regular printing otherwise
|
||||
if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
|
||||
O << "$0";
|
||||
@ -491,7 +505,6 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
||||
}
|
||||
// If not, call printOperand as normal.
|
||||
break;
|
||||
}
|
||||
case 'D': // Second part of a double word register operand
|
||||
case 'L': // Low order register of a double word register operand
|
||||
case 'M': // High order register of a double word register operand
|
||||
@ -671,7 +684,6 @@ printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
||||
printOperand(MI, opNum, O);
|
||||
O << ", ";
|
||||
printOperand(MI, opNum+1, O);
|
||||
return;
|
||||
}
|
||||
|
||||
void MipsAsmPrinter::
|
||||
@ -834,6 +846,7 @@ void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
|
||||
Mips16HardFloatInfo::FPParamVariant PV,
|
||||
bool LE, bool ToFP) {
|
||||
using namespace Mips16HardFloatInfo;
|
||||
|
||||
unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
|
||||
switch (PV) {
|
||||
case FSig:
|
||||
@ -866,6 +879,7 @@ void MipsAsmPrinter::EmitSwapFPIntRetval(
|
||||
const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
|
||||
bool LE) {
|
||||
using namespace Mips16HardFloatInfo;
|
||||
|
||||
unsigned MovOpc = Mips::MFC1;
|
||||
switch (RV) {
|
||||
case FRet:
|
||||
@ -888,8 +902,9 @@ void MipsAsmPrinter::EmitSwapFPIntRetval(
|
||||
|
||||
void MipsAsmPrinter::EmitFPCallStub(
|
||||
const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
|
||||
MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
|
||||
using namespace Mips16HardFloatInfo;
|
||||
|
||||
MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
|
||||
bool LE = getDataLayout().isLittleEndian();
|
||||
// Construct a local MCSubtargetInfo here.
|
||||
// This is because the MachineFunction won't exist (but have not yet been
|
||||
@ -1039,11 +1054,11 @@ void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
||||
//
|
||||
for (std::map<
|
||||
const char *,
|
||||
const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
|
||||
const Mips16HardFloatInfo::FuncSignature *>::const_iterator
|
||||
it = StubsNeeded.begin();
|
||||
it != StubsNeeded.end(); ++it) {
|
||||
const char *Symbol = it->first;
|
||||
const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
|
||||
const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
|
||||
EmitFPCallStub(Symbol, Signature);
|
||||
}
|
||||
// return to the text section
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsAsmPrinter.h - Mips LLVM Assembly Printer ----------*- C++ -*--===//
|
||||
//===- MipsAsmPrinter.h - Mips LLVM Assembly Printer -----------*- C++ -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -16,19 +16,29 @@
|
||||
|
||||
#include "Mips16HardFloatInfo.h"
|
||||
#include "MipsMCInstLower.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "llvm/CodeGen/AsmPrinter.h"
|
||||
#include "llvm/MC/MCStreamer.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include <algorithm>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
|
||||
namespace llvm {
|
||||
class MCStreamer;
|
||||
class MachineInstr;
|
||||
|
||||
class MCOperand;
|
||||
class MCSubtargetInfo;
|
||||
class MCSymbol;
|
||||
class MachineBasicBlock;
|
||||
class MachineConstantPool;
|
||||
class MachineFunction;
|
||||
class MachineInstr;
|
||||
class MachineOperand;
|
||||
class MipsFunctionInfo;
|
||||
class MipsTargetStreamer;
|
||||
class Module;
|
||||
class raw_ostream;
|
||||
class TargetMachine;
|
||||
|
||||
class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
|
||||
MipsTargetStreamer &getTargetStreamer() const;
|
||||
@ -38,6 +48,7 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
|
||||
//===------------------------------------------------------------------===//
|
||||
// XRay implementation
|
||||
//===------------------------------------------------------------------===//
|
||||
|
||||
public:
|
||||
// XRay-specific lowering for Mips.
|
||||
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
|
||||
@ -48,6 +59,17 @@ public:
|
||||
void EmitXRayTable();
|
||||
|
||||
private:
|
||||
/// MCP - Keep a pointer to constantpool entries of the current
|
||||
/// MachineFunction.
|
||||
const MachineConstantPool *MCP = nullptr;
|
||||
|
||||
/// InConstantPool - Maintain state when emitting a sequence of constant
|
||||
/// pool entries so we can properly mark them as data regions.
|
||||
bool InConstantPool = false;
|
||||
|
||||
std::map<const char *, const Mips16HardFloatInfo::FuncSignature *>
|
||||
StubsNeeded;
|
||||
|
||||
void EmitSled(const MachineInstr &MI, SledKind Kind);
|
||||
|
||||
// tblgen'erated function.
|
||||
@ -63,17 +85,6 @@ private:
|
||||
// lowerOperand - Convert a MachineOperand into the equivalent MCOperand.
|
||||
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
|
||||
|
||||
/// MCP - Keep a pointer to constantpool entries of the current
|
||||
/// MachineFunction.
|
||||
const MachineConstantPool *MCP;
|
||||
|
||||
/// InConstantPool - Maintain state when emitting a sequence of constant
|
||||
/// pool entries so we can properly mark them as data regions.
|
||||
bool InConstantPool;
|
||||
|
||||
std::map<const char *, const llvm::Mips16HardFloatInfo::FuncSignature *>
|
||||
StubsNeeded;
|
||||
|
||||
void emitInlineAsmStart() const override;
|
||||
|
||||
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
|
||||
@ -107,15 +118,13 @@ private:
|
||||
bool isLongBranchPseudo(int Opcode) const;
|
||||
|
||||
public:
|
||||
|
||||
const MipsSubtarget *Subtarget;
|
||||
const MipsFunctionInfo *MipsFI;
|
||||
MipsMCInstLower MCInstLowering;
|
||||
|
||||
explicit MipsAsmPrinter(TargetMachine &TM,
|
||||
std::unique_ptr<MCStreamer> Streamer)
|
||||
: AsmPrinter(TM, std::move(Streamer)), MCP(nullptr),
|
||||
InConstantPool(false), MCInstLowering(*this) {}
|
||||
: AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) {}
|
||||
|
||||
StringRef getPassName() const override { return "Mips Assembly Printer"; }
|
||||
|
||||
@ -156,7 +165,7 @@ public:
|
||||
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
|
||||
void EmitDebugThreadLocal(const MCExpr *Value, unsigned Size) const override;
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSASMPRINTER_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsConstantIslandPass.cpp - Emit Pc Relative loads----------------===//
|
||||
//===- MipsConstantIslandPass.cpp - Emit Pc Relative loads ----------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -53,7 +53,6 @@
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <iterator>
|
||||
#include <new>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
@ -72,17 +71,14 @@ AlignConstantIslands("mips-align-constant-islands", cl::Hidden, cl::init(true),
|
||||
|
||||
// Rather than do make check tests with huge amounts of code, we force
|
||||
// the test to use this amount.
|
||||
//
|
||||
static cl::opt<int> ConstantIslandsSmallOffset(
|
||||
"mips-constant-islands-small-offset",
|
||||
cl::init(0),
|
||||
cl::desc("Make small offsets be this amount for testing purposes"),
|
||||
cl::Hidden);
|
||||
|
||||
//
|
||||
// For testing purposes we tell it to not use relaxed load forms so that it
|
||||
// will split blocks.
|
||||
//
|
||||
static cl::opt<bool> NoLoadRelaxation(
|
||||
"mips-constant-islands-no-load-relaxation",
|
||||
cl::init(false),
|
||||
@ -131,12 +127,10 @@ static unsigned int longformBranchOpcode(unsigned int Opcode) {
|
||||
llvm_unreachable("Unknown branch type");
|
||||
}
|
||||
|
||||
//
|
||||
// FIXME: need to go through this whole constant islands port and check the math
|
||||
// for branch ranges and clean this up and make some functions to calculate things
|
||||
// that are done many times identically.
|
||||
// Need to refactor some of the code to call this routine.
|
||||
//
|
||||
static unsigned int branchMaxOffsets(unsigned int Opcode) {
|
||||
unsigned Bits, Scale;
|
||||
switch (Opcode) {
|
||||
@ -189,8 +183,8 @@ static unsigned int branchMaxOffsets(unsigned int Opcode) {
|
||||
|
||||
namespace {
|
||||
|
||||
typedef MachineBasicBlock::iterator Iter;
|
||||
typedef MachineBasicBlock::reverse_iterator ReverseIter;
|
||||
using Iter = MachineBasicBlock::iterator;
|
||||
using ReverseIter = MachineBasicBlock::reverse_iterator;
|
||||
|
||||
/// MipsConstantIslands - Due to limited PC-relative displacements, Mips
|
||||
/// requires constant pool entries to be scattered among the instructions
|
||||
@ -247,7 +241,7 @@ namespace {
|
||||
/// previous iteration by inserting unconditional branches.
|
||||
SmallSet<MachineBasicBlock*, 4> NewWaterList;
|
||||
|
||||
typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
|
||||
using water_iterator = std::vector<MachineBasicBlock *>::iterator;
|
||||
|
||||
/// CPUser - One user of a constant pool, keeping the machine instruction
|
||||
/// pointer, the constant pool being referenced, and the max displacement
|
||||
@ -420,10 +414,10 @@ namespace {
|
||||
void prescanForConstants();
|
||||
};
|
||||
|
||||
char MipsConstantIslands::ID = 0;
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char MipsConstantIslands::ID = 0;
|
||||
|
||||
bool MipsConstantIslands::isOffsetInRange
|
||||
(unsigned UserOffset, unsigned TrialOffset,
|
||||
const CPUser &U) {
|
||||
@ -748,7 +742,6 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
|
||||
// Scan the instructions for constant pool operands.
|
||||
for (unsigned op = 0, e = MI.getNumOperands(); op != e; ++op)
|
||||
if (MI.getOperand(op).isCPI()) {
|
||||
|
||||
// We found one. The addressing mode tells us the max displacement
|
||||
// from the PC that this instruction permits.
|
||||
|
||||
@ -1038,7 +1031,6 @@ void MipsConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
|
||||
/// and instruction CPEMI, and decrement its refcount. If the refcount
|
||||
/// becomes 0 remove the entry and instruction. Returns true if we removed
|
||||
/// the entry, false if we didn't.
|
||||
|
||||
bool MipsConstantIslands::decrementCPEReferenceCount(unsigned CPI,
|
||||
MachineInstr *CPEMI) {
|
||||
// Find the old entry. Eliminate it if it is no longer used.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
|
||||
//===- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler -------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -14,8 +14,8 @@
|
||||
#include "MCTargetDesc/MipsMCNaCl.h"
|
||||
#include "Mips.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/PointerUnion.h"
|
||||
@ -42,6 +42,7 @@
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <iterator>
|
||||
@ -103,9 +104,9 @@ static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
|
||||
|
||||
namespace {
|
||||
|
||||
typedef MachineBasicBlock::iterator Iter;
|
||||
typedef MachineBasicBlock::reverse_iterator ReverseIter;
|
||||
typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
|
||||
using Iter = MachineBasicBlock::iterator;
|
||||
using ReverseIter = MachineBasicBlock::reverse_iterator;
|
||||
using BB2BrMap = SmallDenseMap<MachineBasicBlock *, MachineInstr *, 2>;
|
||||
|
||||
class RegDefsUses {
|
||||
public:
|
||||
@ -186,7 +187,7 @@ namespace {
|
||||
MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI);
|
||||
|
||||
private:
|
||||
typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
|
||||
using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
|
||||
|
||||
bool hasHazard_(const MachineInstr &MI) override;
|
||||
|
||||
@ -211,7 +212,7 @@ namespace {
|
||||
|
||||
class Filler : public MachineFunctionPass {
|
||||
public:
|
||||
Filler() : MachineFunctionPass(ID), TM(nullptr) {}
|
||||
Filler() : MachineFunctionPass(ID) {}
|
||||
|
||||
StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
|
||||
|
||||
@ -290,15 +291,15 @@ namespace {
|
||||
|
||||
bool terminateSearch(const MachineInstr &Candidate) const;
|
||||
|
||||
const TargetMachine *TM;
|
||||
const TargetMachine *TM = nullptr;
|
||||
|
||||
static char ID;
|
||||
};
|
||||
|
||||
char Filler::ID = 0;
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char Filler::ID = 0;
|
||||
|
||||
static bool hasUnoccupiedSlot(const MachineInstr *MI) {
|
||||
return MI->hasDelaySlot() && !MI->isBundledWithSucc();
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsFastISel.cpp - Mips FastISel implementation -------------------===//
|
||||
//===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -69,7 +69,6 @@
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <new>
|
||||
|
||||
#define DEBUG_TYPE "mips-fastisel"
|
||||
|
||||
@ -82,7 +81,7 @@ class MipsFastISel final : public FastISel {
|
||||
// All possible address modes.
|
||||
class Address {
|
||||
public:
|
||||
typedef enum { RegBase, FrameIndexBase } BaseKind;
|
||||
using BaseKind = enum { RegBase, FrameIndexBase };
|
||||
|
||||
private:
|
||||
BaseKind Kind = RegBase;
|
||||
@ -231,7 +230,6 @@ private:
|
||||
|
||||
// for some reason, this default is not generated by tablegen
|
||||
// so we explicitly generate it here.
|
||||
//
|
||||
unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
|
||||
unsigned Op0, bool Op0IsKill, uint64_t imm1,
|
||||
uint64_t imm2, unsigned Op3, bool Op3IsKill) {
|
||||
@ -629,6 +627,7 @@ bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
// Because of how EmitCmp is called with fast-isel, you can
|
||||
// end up with redundant "andi" instructions after the sequences emitted below.
|
||||
// We should try and solve this issue in the future.
|
||||
@ -937,10 +936,8 @@ bool MipsFastISel::selectStore(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
//
|
||||
// This can cause a redundant sltiu to be generated.
|
||||
// FIXME: try and eliminate this in a future patch.
|
||||
//
|
||||
bool MipsFastISel::selectBranch(const Instruction *I) {
|
||||
const BranchInst *BI = cast<BranchInst>(I);
|
||||
MachineBasicBlock *BrBB = FuncInfo.MBB;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsHazardSchedule.cpp - Workaround pipeline hazards --------------===//
|
||||
//===- MipsHazardSchedule.cpp - Workaround pipeline hazards ---------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -44,15 +44,15 @@
|
||||
|
||||
#include "Mips.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "MipsSEInstrInfo.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include <algorithm>
|
||||
#include <iterator>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -62,11 +62,10 @@ STATISTIC(NumInsertedNops, "Number of nops inserted");
|
||||
|
||||
namespace {
|
||||
|
||||
typedef MachineBasicBlock::iterator Iter;
|
||||
typedef MachineBasicBlock::reverse_iterator ReverseIter;
|
||||
using Iter = MachineBasicBlock::iterator;
|
||||
using ReverseIter = MachineBasicBlock::reverse_iterator;
|
||||
|
||||
class MipsHazardSchedule : public MachineFunctionPass {
|
||||
|
||||
public:
|
||||
MipsHazardSchedule() : MachineFunctionPass(ID) {}
|
||||
|
||||
@ -83,9 +82,10 @@ private:
|
||||
static char ID;
|
||||
};
|
||||
|
||||
char MipsHazardSchedule::ID = 0;
|
||||
} // end of anonymous namespace
|
||||
|
||||
char MipsHazardSchedule::ID = 0;
|
||||
|
||||
/// Returns a pass that clears pipeline hazards.
|
||||
FunctionPass *llvm::createMipsHazardSchedule() {
|
||||
return new MipsHazardSchedule();
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
|
||||
//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -11,33 +11,70 @@
|
||||
// selection DAG.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MipsISelLowering.h"
|
||||
#include "InstPrinter/MipsInstPrinter.h"
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
||||
#include "MipsCCState.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "MipsTargetObjectFile.h"
|
||||
#include "llvm/ADT/APFloat.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/ADT/StringSwitch.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/CodeGen/CallingConvLower.h"
|
||||
#include "llvm/CodeGen/FunctionLoweringInfo.h"
|
||||
#include "llvm/CodeGen/ISDOpcodes.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineJumpTableInfo.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/SelectionDAGISel.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/CodeGen/RuntimeLibcalls.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/CodeGen/SelectionDAGNodes.h"
|
||||
#include "llvm/CodeGen/ValueTypes.h"
|
||||
#include "llvm/IR/CallingConv.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
#include "llvm/IR/DataLayout.h"
|
||||
#include "llvm/IR/DebugLoc.h"
|
||||
#include "llvm/IR/DerivedTypes.h"
|
||||
#include "llvm/IR/GlobalVariable.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/GlobalValue.h"
|
||||
#include "llvm/IR/Type.h"
|
||||
#include "llvm/IR/Value.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/CodeGen.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Target/TargetFrameLowering.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cctype>
|
||||
#include <cstdint>
|
||||
#include <deque>
|
||||
#include <iterator>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -102,7 +139,6 @@ unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
|
||||
unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
|
||||
LLVMContext &Context, EVT VT, EVT &IntermediateVT,
|
||||
unsigned &NumIntermediates, MVT &RegisterVT) const {
|
||||
|
||||
// Break down vector types to either 2 i64s or 4 i32s.
|
||||
RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
|
||||
IntermediateVT = RegisterVT;
|
||||
@ -451,7 +487,6 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
|
||||
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
|
||||
}
|
||||
|
||||
|
||||
if (!Subtarget.hasMips32r2()) {
|
||||
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
|
||||
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
||||
@ -510,9 +545,9 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
|
||||
const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
|
||||
const MipsSubtarget &STI) {
|
||||
if (STI.inMips16Mode())
|
||||
return llvm::createMips16TargetLowering(TM, STI);
|
||||
return createMips16TargetLowering(TM, STI);
|
||||
|
||||
return llvm::createMipsSETargetLowering(TM, STI);
|
||||
return createMipsSETargetLowering(TM, STI);
|
||||
}
|
||||
|
||||
// Create a fast isel object.
|
||||
@ -605,7 +640,6 @@ static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/// This function returns true if the floating point conditional branches and
|
||||
/// conditional moves which use condition code CC should be inverted.
|
||||
static bool invertFPCondCodeUser(Mips::CondCode CC) {
|
||||
@ -1109,7 +1143,6 @@ static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
|
||||
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget &Subtarget) {
|
||||
@ -2873,7 +2906,7 @@ SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
|
||||
|
||||
void MipsTargetLowering::
|
||||
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
||||
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
||||
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
||||
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
||||
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
||||
SDValue Chain) const {
|
||||
@ -2918,7 +2951,7 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
|
||||
assert(Mask && "Missing call preserved mask for calling convention");
|
||||
if (Subtarget.inMips16HardFloat()) {
|
||||
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
|
||||
llvm::StringRef Sym = G->getGlobal()->getName();
|
||||
StringRef Sym = G->getGlobal()->getName();
|
||||
Function *F = G->getGlobal()->getParent()->getFunction(Sym);
|
||||
if (F && F->hasFnAttribute("__Mips16RetHelper")) {
|
||||
Mask = MipsRegisterInfo::getMips16RetHelperMask();
|
||||
@ -3006,7 +3039,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
|
||||
getPointerTy(DAG.getDataLayout()));
|
||||
|
||||
std::deque< std::pair<unsigned, SDValue> > RegsToPass;
|
||||
std::deque<std::pair<unsigned, SDValue>> RegsToPass;
|
||||
SmallVector<SDValue, 8> MemOpChains;
|
||||
|
||||
CCInfo.rewindByValRegsInfo();
|
||||
@ -3525,7 +3558,6 @@ SDValue
|
||||
MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
|
||||
const SDLoc &DL,
|
||||
SelectionDAG &DAG) const {
|
||||
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
|
||||
//===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -17,16 +17,45 @@
|
||||
|
||||
#include "MCTargetDesc/MipsABIInfo.h"
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
||||
#include "Mips.h"
|
||||
#include "llvm/CodeGen/CallingConvLower.h"
|
||||
#include "llvm/CodeGen/ISDOpcodes.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/CodeGen/SelectionDAGNodes.h"
|
||||
#include "llvm/CodeGen/ValueTypes.h"
|
||||
#include "llvm/IR/CallingConv.h"
|
||||
#include "llvm/IR/InlineAsm.h"
|
||||
#include "llvm/IR/Type.h"
|
||||
#include "llvm/Target/TargetLowering.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <deque>
|
||||
#include <string>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class Argument;
|
||||
class CCState;
|
||||
class CCValAssign;
|
||||
class FastISel;
|
||||
class FunctionLoweringInfo;
|
||||
class MachineBasicBlock;
|
||||
class MachineFrameInfo;
|
||||
class MachineInstr;
|
||||
class MipsCCState;
|
||||
class MipsFunctionInfo;
|
||||
class MipsSubtarget;
|
||||
class MipsTargetMachine;
|
||||
class TargetLibraryInfo;
|
||||
class TargetRegisterClass;
|
||||
|
||||
namespace MipsISD {
|
||||
|
||||
enum NodeType : unsigned {
|
||||
// Start the numbering from where ISD NodeType finishes.
|
||||
FIRST_NUMBER = ISD::BUILTIN_OP_END,
|
||||
@ -224,17 +253,16 @@ namespace llvm {
|
||||
SDL,
|
||||
SDR
|
||||
};
|
||||
}
|
||||
|
||||
} // ene namespace MipsISD
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// TargetLowering Implementation
|
||||
//===--------------------------------------------------------------------===//
|
||||
class MipsFunctionInfo;
|
||||
class MipsSubtarget;
|
||||
class MipsCCState;
|
||||
|
||||
class MipsTargetLowering : public TargetLowering {
|
||||
bool isMicroMips;
|
||||
|
||||
public:
|
||||
explicit MipsTargetLowering(const MipsTargetMachine &TM,
|
||||
const MipsSubtarget &STI);
|
||||
@ -256,26 +284,26 @@ namespace llvm {
|
||||
|
||||
/// Return the register type for a given MVT, ensuring vectors are treated
|
||||
/// as a series of gpr sized integers.
|
||||
virtual MVT getRegisterTypeForCallingConv(MVT VT) const override;
|
||||
MVT getRegisterTypeForCallingConv(MVT VT) const override;
|
||||
|
||||
/// Return the register type for a given MVT, ensuring vectors are treated
|
||||
/// as a series of gpr sized integers.
|
||||
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
|
||||
EVT VT) const override;
|
||||
MVT getRegisterTypeForCallingConv(LLVMContext &Context,
|
||||
EVT VT) const override;
|
||||
|
||||
/// Return the number of registers for a given MVT, ensuring vectors are
|
||||
/// treated as a series of gpr sized integers.
|
||||
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
|
||||
EVT VT) const override;
|
||||
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
|
||||
EVT VT) const override;
|
||||
|
||||
/// Break down vectors to the correct number of gpr sized integers.
|
||||
virtual unsigned getVectorTypeBreakdownForCallingConv(
|
||||
unsigned getVectorTypeBreakdownForCallingConv(
|
||||
LLVMContext &Context, EVT VT, EVT &IntermediateVT,
|
||||
unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
||||
|
||||
/// Return the correct alignment for the current calling convention.
|
||||
virtual unsigned
|
||||
getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override {
|
||||
unsigned getABIAlignmentForCallingConv(Type *ArgTy,
|
||||
DataLayout DL) const override {
|
||||
if (ArgTy->isVectorTy())
|
||||
return std::min(DL.getABITypeAlignment(ArgTy), 8U);
|
||||
return DL.getABITypeAlignment(ArgTy);
|
||||
@ -461,7 +489,7 @@ namespace llvm {
|
||||
/// copyToReg nodes to set up argument registers.
|
||||
virtual void
|
||||
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
||||
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
||||
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
||||
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
||||
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
||||
SDValue Chain) const;
|
||||
@ -681,10 +709,13 @@ namespace llvm {
|
||||
createMipsSETargetLowering(const MipsTargetMachine &TM,
|
||||
const MipsSubtarget &STI);
|
||||
|
||||
namespace Mips {
|
||||
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
const TargetLibraryInfo *libInfo);
|
||||
}
|
||||
}
|
||||
namespace Mips {
|
||||
|
||||
#endif
|
||||
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
const TargetLibraryInfo *libInfo);
|
||||
|
||||
} // end namespace Mips
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
|
||||
//===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -12,14 +12,22 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "InstPrinter/MipsInstPrinter.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/IR/DebugLoc.h"
|
||||
#include "llvm/MC/MCInstrDesc.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOpcodes.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -35,9 +43,9 @@ MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
|
||||
|
||||
const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
|
||||
if (STI.inMips16Mode())
|
||||
return llvm::createMips16InstrInfo(STI);
|
||||
return createMips16InstrInfo(STI);
|
||||
|
||||
return llvm::createMipsSEInstrInfo(STI);
|
||||
return createMipsSEInstrInfo(STI);
|
||||
}
|
||||
|
||||
bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
|
||||
@ -80,7 +88,7 @@ void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
||||
BB = Inst->getOperand(NumOp-1).getMBB();
|
||||
Cond.push_back(MachineOperand::CreateImm(Opc));
|
||||
|
||||
for (int i=0; i<NumOp-1; i++)
|
||||
for (int i = 0; i < NumOp-1; i++)
|
||||
Cond.push_back(Inst->getOperand(i));
|
||||
}
|
||||
|
||||
@ -185,7 +193,6 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
|
||||
MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
|
||||
SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
|
||||
|
||||
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
|
||||
|
||||
// Skip all the debug instructions.
|
||||
@ -396,7 +403,6 @@ bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
|
||||
return false;
|
||||
|
||||
return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
|
||||
|
||||
}
|
||||
|
||||
/// Predicate for distingushing instructions that have forbidden slots.
|
||||
@ -514,7 +520,7 @@ bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
||||
case Mips::DPADD_U_D:
|
||||
case Mips::DPADD_S_H:
|
||||
case Mips::DPADD_S_W:
|
||||
case Mips::DPADD_S_D: {
|
||||
case Mips::DPADD_S_D:
|
||||
// The first operand is both input and output, so it should not commute
|
||||
if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
|
||||
return false;
|
||||
@ -523,6 +529,5 @@ bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
|
||||
//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -18,19 +18,30 @@
|
||||
#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
|
||||
#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
|
||||
|
||||
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
||||
#include "Mips.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include <cstdint>
|
||||
|
||||
#define GET_INSTRINFO_HEADER
|
||||
#include "MipsGenInstrInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MachineInstr;
|
||||
class MachineOperand;
|
||||
class MipsSubtarget;
|
||||
class TargetRegisterClass;
|
||||
class TargetRegisterInfo;
|
||||
|
||||
class MipsInstrInfo : public MipsGenInstrInfo {
|
||||
virtual void anchor();
|
||||
|
||||
protected:
|
||||
const MipsSubtarget &Subtarget;
|
||||
unsigned UncondBrOpc;
|
||||
@ -88,7 +99,6 @@ public:
|
||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||
/// such, whenever a client has an instance of instruction info, it should
|
||||
/// always be able to get register info as well (through this method).
|
||||
///
|
||||
virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
|
||||
|
||||
virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
|
||||
@ -159,6 +169,6 @@ private:
|
||||
const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
|
||||
const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
|
||||
|
||||
}
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsLongBranch.cpp - Emit long branches ---------------------------===//
|
||||
//===- MipsLongBranch.cpp - Emit long branches ----------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -16,6 +16,7 @@
|
||||
#include "MCTargetDesc/MipsABIInfo.h"
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "MCTargetDesc/MipsMCNaCl.h"
|
||||
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
||||
#include "Mips.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
@ -35,6 +36,7 @@
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <iterator>
|
||||
@ -59,8 +61,8 @@ static cl::opt<bool> ForceLongBranch(
|
||||
|
||||
namespace {
|
||||
|
||||
typedef MachineBasicBlock::iterator Iter;
|
||||
typedef MachineBasicBlock::reverse_iterator ReverseIter;
|
||||
using Iter = MachineBasicBlock::iterator;
|
||||
using ReverseIter = MachineBasicBlock::reverse_iterator;
|
||||
|
||||
struct MBBInfo {
|
||||
uint64_t Size = 0;
|
||||
@ -102,10 +104,10 @@ namespace {
|
||||
unsigned LongBranchSeqSize;
|
||||
};
|
||||
|
||||
char MipsLongBranch::ID = 0;
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char MipsLongBranch::ID = 0;
|
||||
|
||||
/// Iterate over list of Br's operands and search for a MachineBasicBlock
|
||||
/// operand.
|
||||
static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
|
||||
@ -468,7 +470,6 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
|
||||
const MipsInstrInfo *TII =
|
||||
static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
|
||||
|
||||
|
||||
const TargetMachine& TM = F.getTarget();
|
||||
IsPIC = TM.isPositionIndependent();
|
||||
ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
|
||||
//===- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ----------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -11,18 +11,18 @@
|
||||
// MCInst records.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MipsMCInstLower.h"
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "MCTargetDesc/MipsMCExpr.h"
|
||||
#include "MipsAsmPrinter.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/IR/Mangler.h"
|
||||
#include "llvm/MC/MCContext.h"
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCStreamer.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include <cassert>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -278,4 +278,3 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
|
||||
OutMI.addOperand(MCOp);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsMCInstLower.h - Lower MachineInstr to MCInst -------*- C++ -*--===//
|
||||
//===- MipsMCInstLower.h - Lower MachineInstr to MCInst --------*- C++ -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -9,26 +9,31 @@
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
|
||||
#define LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
|
||||
|
||||
#include "MCTargetDesc/MipsMCExpr.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
|
||||
namespace llvm {
|
||||
class MCContext;
|
||||
class MCInst;
|
||||
class MCOperand;
|
||||
class MachineInstr;
|
||||
class MachineFunction;
|
||||
class MipsAsmPrinter;
|
||||
|
||||
class MachineBasicBlock;
|
||||
class MachineInstr;
|
||||
class MCContext;
|
||||
class MCInst;
|
||||
class MCOperand;
|
||||
class MipsAsmPrinter;
|
||||
|
||||
/// MipsMCInstLower - This class is used to lower an MachineInstr into an
|
||||
// MCInst.
|
||||
/// MCInst.
|
||||
class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
|
||||
typedef MachineOperand::MachineOperandType MachineOperandType;
|
||||
using MachineOperandType = MachineOperand::MachineOperandType;
|
||||
|
||||
MCContext *Ctx;
|
||||
MipsAsmPrinter &AsmPrinter;
|
||||
|
||||
public:
|
||||
MipsMCInstLower(MipsAsmPrinter &asmprinter);
|
||||
|
||||
void Initialize(MCContext *C);
|
||||
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
|
||||
MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
|
||||
@ -43,6 +48,7 @@ private:
|
||||
MipsMCExpr::MipsExprKind Kind) const;
|
||||
bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===--------- MipsOptimizePICCall.cpp - Optimize PIC Calls ---------------===//
|
||||
//===- MipsOptimizePICCall.cpp - Optimize PIC Calls -----------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -14,12 +14,31 @@
|
||||
|
||||
#include "MCTargetDesc/MipsBaseInfo.h"
|
||||
#include "Mips.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "llvm/ADT/PointerUnion.h"
|
||||
#include "llvm/ADT/ScopedHashTable.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineDominators.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/Support/Allocator.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/RecyclingAllocator.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetOpcodes.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -35,18 +54,18 @@ static cl::opt<bool> EraseGPOpnd("mips-erase-gp-opnd",
|
||||
cl::Hidden);
|
||||
|
||||
namespace {
|
||||
typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
|
||||
|
||||
typedef std::pair<unsigned, unsigned> CntRegP;
|
||||
typedef RecyclingAllocator<BumpPtrAllocator,
|
||||
ScopedHashTableVal<ValueType, CntRegP> >
|
||||
AllocatorTy;
|
||||
typedef ScopedHashTable<ValueType, CntRegP, DenseMapInfo<ValueType>,
|
||||
AllocatorTy> ScopedHTType;
|
||||
using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
|
||||
using CntRegP = std::pair<unsigned, unsigned>;
|
||||
using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
|
||||
ScopedHashTableVal<ValueType, CntRegP>>;
|
||||
using ScopedHTType = ScopedHashTable<ValueType, CntRegP,
|
||||
DenseMapInfo<ValueType>, AllocatorTy>;
|
||||
|
||||
class MBBInfo {
|
||||
public:
|
||||
MBBInfo(MachineDomTreeNode *N);
|
||||
|
||||
const MachineDomTreeNode *getNode() const;
|
||||
bool isVisited() const;
|
||||
void preVisit(ScopedHTType &ScopedHT);
|
||||
@ -94,12 +113,14 @@ private:
|
||||
void incCntAndSetReg(ValueType Entry, unsigned Reg);
|
||||
|
||||
ScopedHTType ScopedHT;
|
||||
|
||||
static char ID;
|
||||
};
|
||||
|
||||
char OptimizePICCall::ID = 0;
|
||||
} // end of anonymous namespace
|
||||
|
||||
char OptimizePICCall::ID = 0;
|
||||
|
||||
/// Return the first MachineOperand of MI if it is a used virtual register.
|
||||
static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) {
|
||||
if (MI.getNumOperands() == 0)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
|
||||
//===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -12,8 +12,8 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "MCTargetDesc/MipsABIInfo.h"
|
||||
#include "Mips.h"
|
||||
#include "MipsInstrInfo.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
@ -21,19 +21,17 @@
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
#include "llvm/IR/DebugInfo.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/Type.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetFrameLowering.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cstdint>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -162,7 +160,8 @@ getReservedRegs(const MachineFunction &MF) const {
|
||||
|
||||
BitVector Reserved(getNumRegs());
|
||||
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
|
||||
typedef TargetRegisterClass::const_iterator RegIter;
|
||||
|
||||
using RegIter = TargetRegisterClass::const_iterator;
|
||||
|
||||
for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
|
||||
Reserved.set(ReservedGPR32[I]);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
|
||||
//===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -15,12 +15,16 @@
|
||||
#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
|
||||
|
||||
#include "Mips.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include <cstdint>
|
||||
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "MipsGenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class TargetRegisterClass;
|
||||
|
||||
class MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||
public:
|
||||
enum class MipsPtrClass {
|
||||
@ -79,4 +83,4 @@ private:
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
|
||||
//===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -71,7 +71,7 @@ public:
|
||||
bool expand();
|
||||
|
||||
private:
|
||||
typedef MachineBasicBlock::iterator Iter;
|
||||
using Iter = MachineBasicBlock::iterator;
|
||||
|
||||
bool expandInstr(MachineBasicBlock &MBB, Iter I);
|
||||
void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
|
||||
|
||||
@ -6,20 +6,19 @@
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEFRAMELOWERING_H
|
||||
#define LLVM_LIB_TARGET_MIPS_MIPSSEFRAMELOWERING_H
|
||||
|
||||
#include "MipsFrameLowering.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include <vector>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MachineBasicBlock;
|
||||
class MachineFunction;
|
||||
class MipsSubtarget;
|
||||
|
||||
class MipsSEFrameLowering : public MipsFrameLowering {
|
||||
public:
|
||||
explicit MipsSEFrameLowering(const MipsSubtarget &STI);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
|
||||
//===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -10,19 +10,43 @@
|
||||
// Subclass of MipsTargetLowering specialized for mips32/64.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "MipsSEISelLowering.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "MipsTargetMachine.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "llvm/ADT/APInt.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/Triple.h"
|
||||
#include "llvm/CodeGen/CallingConvLower.h"
|
||||
#include "llvm/CodeGen/ISDOpcodes.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/CodeGen/SelectionDAGNodes.h"
|
||||
#include "llvm/CodeGen/ValueTypes.h"
|
||||
#include "llvm/IR/DebugLoc.h"
|
||||
#include "llvm/IR/Intrinsics.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <iterator>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -368,7 +392,6 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
|
||||
}
|
||||
|
||||
SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
if(!Subtarget.hasMips32r6())
|
||||
return MipsTargetLowering::LowerOperation(Op, DAG);
|
||||
|
||||
@ -1090,7 +1113,7 @@ bool MipsSETargetLowering::isEligibleForTailCallOptimization(
|
||||
|
||||
void MipsSETargetLowering::
|
||||
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
||||
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
||||
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
||||
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
||||
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
||||
SDValue Chain) const {
|
||||
@ -1706,11 +1729,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
|
||||
Op->getOperand(2));
|
||||
case Intrinsic::mips_fadd_w:
|
||||
case Intrinsic::mips_fadd_d: {
|
||||
case Intrinsic::mips_fadd_d:
|
||||
// TODO: If intrinsics have fast-math-flags, propagate them.
|
||||
return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
|
||||
Op->getOperand(2));
|
||||
}
|
||||
// Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
|
||||
case Intrinsic::mips_fceq_w:
|
||||
case Intrinsic::mips_fceq_d:
|
||||
@ -1753,11 +1775,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
|
||||
Op->getOperand(2), ISD::SETUNE);
|
||||
case Intrinsic::mips_fdiv_w:
|
||||
case Intrinsic::mips_fdiv_d: {
|
||||
case Intrinsic::mips_fdiv_d:
|
||||
// TODO: If intrinsics have fast-math-flags, propagate them.
|
||||
return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
|
||||
Op->getOperand(2));
|
||||
}
|
||||
case Intrinsic::mips_ffint_u_w:
|
||||
case Intrinsic::mips_ffint_u_d:
|
||||
return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
|
||||
@ -1794,11 +1815,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
|
||||
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
|
||||
case Intrinsic::mips_fmul_w:
|
||||
case Intrinsic::mips_fmul_d: {
|
||||
case Intrinsic::mips_fmul_d:
|
||||
// TODO: If intrinsics have fast-math-flags, propagate them.
|
||||
return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
|
||||
Op->getOperand(2));
|
||||
}
|
||||
case Intrinsic::mips_fmsub_w:
|
||||
case Intrinsic::mips_fmsub_d: {
|
||||
// TODO: If intrinsics have fast-math-flags, propagate them.
|
||||
@ -1814,11 +1834,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
case Intrinsic::mips_fsqrt_d:
|
||||
return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
|
||||
case Intrinsic::mips_fsub_w:
|
||||
case Intrinsic::mips_fsub_d: {
|
||||
case Intrinsic::mips_fsub_d:
|
||||
// TODO: If intrinsics have fast-math-flags, propagate them.
|
||||
return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
|
||||
Op->getOperand(2));
|
||||
}
|
||||
case Intrinsic::mips_ftrunc_u_w:
|
||||
case Intrinsic::mips_ftrunc_u_d:
|
||||
return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
|
||||
@ -3472,7 +3491,6 @@ MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
|
||||
// memory it's not supposed to.
|
||||
// b) The load crosses an implementation specific boundary, requiring OS
|
||||
// intervention.
|
||||
//
|
||||
MachineBasicBlock *
|
||||
MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
@ -3559,7 +3577,6 @@ MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
|
||||
// insert.w for one element, we avoid that potiential case. If
|
||||
// fexdo.[hw] causes an exception in, the exception is valid and it
|
||||
// occurs for all elements.
|
||||
//
|
||||
MachineBasicBlock *
|
||||
MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB,
|
||||
@ -3665,7 +3682,6 @@ MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
|
||||
// mtc1 $rtemp, $ftemp
|
||||
// copy_s.w $rtemp2, $wtemp2[1]
|
||||
// $fd = mthc1 $rtemp2, $ftemp
|
||||
//
|
||||
MachineBasicBlock *
|
||||
MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB,
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
|
||||
//===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -15,9 +15,18 @@
|
||||
#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
|
||||
|
||||
#include "MipsISelLowering.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/CodeGen/SelectionDAGNodes.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MachineBasicBlock;
|
||||
class MachineInstr;
|
||||
class MipsSubtarget;
|
||||
class MipsTargetMachine;
|
||||
class SelectionDAG;
|
||||
class TargetRegisterClass;
|
||||
|
||||
class MipsSETargetLowering : public MipsTargetLowering {
|
||||
public:
|
||||
explicit MipsSETargetLowering(const MipsTargetMachine &TM,
|
||||
@ -26,6 +35,7 @@ namespace llvm {
|
||||
/// \brief Enable MSA support for the given integer type and Register
|
||||
/// class.
|
||||
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
|
||||
|
||||
/// \brief Enable MSA support for the given floating-point type and
|
||||
/// Register class.
|
||||
void addMSAFloatType(MVT::SimpleValueType Ty,
|
||||
@ -56,7 +66,7 @@ namespace llvm {
|
||||
|
||||
void
|
||||
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
||||
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
||||
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
||||
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
||||
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
||||
SDValue Chain) const override;
|
||||
@ -126,6 +136,7 @@ namespace llvm {
|
||||
MachineBasicBlock *BBi,
|
||||
bool IsFGR64) const;
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user