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[AMDGPU] Standardize on using AMDGPU::getNullPointerValue. NFC. (#187037)

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AMDGPUTargetMachine also had a static method which did the same thing.
Remove it so that we have a single source of truth.
This commit is contained in:
Jay Foad 2026-03-17 17:08:16 +00:00 committed by GitHub
parent adf458cbac
commit 79d1a2c418
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GPG Key ID: B5690EEEBB952194
11 changed files with 18 additions and 35 deletions
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2
llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
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@ -1953,7 +1953,7 @@ static bool isPtrKnownNeverNull(const Value *V, const DataLayout &DL,
// TODO: Use ValueTracking's isKnownNeverNull if it becomes aware that some
// address spaces have non-zero null values.
auto SrcPtrKB = computeKnownBits(V, DL);
const auto NullVal = TM.getNullPointerValue(AS);
const auto NullVal = AMDGPU::getNullPointerValue(AS);
assert(SrcPtrKB.getBitWidth() == DL.getPointerSizeInBits(AS));
assert((NullVal == 0 || NullVal == -1) &&

2
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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@ -1673,7 +1673,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Parent,
if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
int64_t Imm = CAddr->getSExtValue();
const int64_t NullPtr =
AMDGPUTargetMachine::getNullPointerValue(AMDGPUAS::PRIVATE_ADDRESS);
AMDGPU::getNullPointerValue(AMDGPUAS::PRIVATE_ADDRESS);
// Don't fold null pointer.
if (Imm != NullPtr) {
const uint32_t MaxOffset = SIInstrInfo::getMaxMUBUFImmOffset(*Subtarget);

2
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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@ -6218,7 +6218,7 @@ AMDGPUInstructionSelector::selectMUBUFScratchOffen(MachineOperand &Root) const {
int64_t Offset = 0;
if (mi_match(Root.getReg(), *MRI, m_ICst(Offset)) &&
Offset != TM.getNullPointerValue(AMDGPUAS::PRIVATE_ADDRESS)) {
Offset != AMDGPU::getNullPointerValue(AMDGPUAS::PRIVATE_ADDRESS)) {
Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
// TODO: Should this be inside the render function? The iterator seems to

9
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -2424,7 +2424,7 @@ static bool isKnownNonNull(Register Val, MachineRegisterInfo &MRI,
return true;
case AMDGPU::G_CONSTANT: {
const ConstantInt *CI = Def->getOperand(1).getCImm();
return CI->getSExtValue() != TM.getNullPointerValue(AddrSpace);
return CI->getSExtValue() != AMDGPU::getNullPointerValue(AddrSpace);
}
default:
return false;
@ -2496,7 +2496,7 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
return true;
}
unsigned NullVal = TM.getNullPointerValue(DestAS);
unsigned NullVal = AMDGPU::getNullPointerValue(DestAS);
auto SegmentNull = B.buildConstant(DstTy, NullVal);
auto FlatNull = B.buildConstant(SrcTy, 0);
@ -2570,8 +2570,9 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
Register BuildPtr = castLocalOrPrivateToFlat(DstTy);
auto SegmentNull = B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
auto FlatNull = B.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
auto SegmentNull =
B.buildConstant(SrcTy, AMDGPU::getNullPointerValue(SrcAS));
auto FlatNull = B.buildConstant(DstTy, AMDGPU::getNullPointerValue(DestAS));
auto CmpRes = B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src,
SegmentNull.getReg(0));

2
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
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@ -283,7 +283,7 @@ const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV,
}
}
if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
if (const MCExpr *E = lowerAddrSpaceCast(CV, OutContext))
return E;
return AsmPrinter::lowerConstant(CV, BaseCV, Offset);
}

12
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
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@ -17,6 +17,7 @@
#include "AMDGPUTargetMachine.h"
#include "llvm/IR/Constants.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
#include "llvm/Support/Casting.h"
namespace llvm {
@ -42,13 +43,8 @@ public:
};
namespace {
static inline const MCExpr *lowerAddrSpaceCast(const TargetMachine &TM,
const Constant *CV,
static inline const MCExpr *lowerAddrSpaceCast(const Constant *CV,
MCContext &OutContext) {
// TargetMachine does not support llvm-style cast. Use C++-style cast.
// This is safe since TM is always of type AMDGPUTargetMachine or its
// derived class.
auto &AT = static_cast<const AMDGPUTargetMachine &>(TM);
auto *CE = dyn_cast<ConstantExpr>(CV);
// Lower null pointers in private and local address space.
@ -57,9 +53,9 @@ static inline const MCExpr *lowerAddrSpaceCast(const TargetMachine &TM,
if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
auto *Op = CE->getOperand(0);
auto SrcAddr = Op->getType()->getPointerAddressSpace();
if (Op->isNullValue() && AT.getNullPointerValue(SrcAddr) == 0) {
if (Op->isNullValue() && AMDGPU::getNullPointerValue(SrcAddr) == 0) {
auto DstAddr = CE->getType()->getPointerAddressSpace();
return MCConstantExpr::create(AT.getNullPointerValue(DstAddr),
return MCConstantExpr::create(AMDGPU::getNullPointerValue(DstAddr),
OutContext);
}
}

8
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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@ -1095,14 +1095,6 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
});
}
int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
AddrSpace == AMDGPUAS::REGION_ADDRESS)
? -1
: 0;
}
bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
unsigned DestAS) const {
return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&

3
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
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@ -55,9 +55,6 @@ public:
void registerPassBuilderCallbacks(PassBuilder &PB) override;
void registerDefaultAliasAnalyses(AAManager &) override;
/// Get the integer value of a null pointer in the given address space.
static int64_t getNullPointerValue(unsigned AddrSpace);
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
unsigned getAssumedAddrSpace(const Value *V) const override;

5
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
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@ -949,15 +949,12 @@ SDValue R600TargetLowering::lowerADDRSPACECAST(SDValue Op,
SDLoc SL(Op);
EVT VT = Op.getValueType();
const R600TargetMachine &TM =
static_cast<const R600TargetMachine &>(getTargetMachine());
const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
unsigned SrcAS = ASC->getSrcAddressSpace();
unsigned DestAS = ASC->getDestAddressSpace();
if (isNullConstant(Op.getOperand(0)) && SrcAS == AMDGPUAS::FLAT_ADDRESS)
return DAG.getSignedConstant(TM.getNullPointerValue(DestAS), SL, VT);
return DAG.getSignedConstant(AMDGPU::getNullPointerValue(DestAS), SL, VT);
return Op;
}

2
llvm/lib/Target/AMDGPU/R600MCInstLower.cpp
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@ -77,7 +77,7 @@ void R600AsmPrinter::emitInstruction(const MachineInstr *MI) {
const MCExpr *R600AsmPrinter::lowerConstant(const Constant *CV,
const Constant *BaseCV,
uint64_t Offset) {
if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
if (const MCExpr *E = lowerAddrSpaceCast(CV, OutContext))
return E;
return AsmPrinter::lowerConstant(CV, BaseCV, Offset);
}

6
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -8628,7 +8628,7 @@ static bool isKnownNonNull(SDValue Val, SelectionDAG &DAG,
return true;
if (auto *ConstVal = dyn_cast<ConstantSDNode>(Val))
return ConstVal->getSExtValue() != TM.getNullPointerValue(AddrSpace);
return ConstVal->getSExtValue() != AMDGPU::getNullPointerValue(AddrSpace);
// TODO: Search through arithmetic, handle arguments and loads
// marked nonnull.
@ -8682,7 +8682,7 @@ SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
if (IsNonNull || isKnownNonNull(Op, DAG, TM, SrcAS))
return Ptr;
unsigned NullVal = TM.getNullPointerValue(DestAS);
unsigned NullVal = AMDGPU::getNullPointerValue(DestAS);
SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
@ -8733,7 +8733,7 @@ SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
if (IsNonNull || isKnownNonNull(Op, DAG, TM, SrcAS))
return CvtPtr;
unsigned NullVal = TM.getNullPointerValue(SrcAS);
unsigned NullVal = AMDGPU::getNullPointerValue(SrcAS);
SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
SDValue NonNull =