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[TableGen] Let -register-info-debug dump the Artificial flag (#185899)

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Dump the Artificial flag for RegisterClasses, SubRegIndices and
Registers. To avoid clutter it is only dumped when the flag is set (has
value 1).
This commit is contained in:
Jay Foad 2026-03-11 16:00:49 +00:00 committed by GitHub
parent 5842a0f76c
commit 79d2444dae
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GPG Key ID: B5690EEEBB952194
3 changed files with 23 additions and 0 deletions
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7
llvm/test/TableGen/ArtificialRegs.td
View File

@ -52,5 +52,12 @@ def DA : RegisterClass<"D", [i64], 64, (add D0, A)>;
// CHECK-NEXT: BaseClassOrder:
// CHECK-NEXT: Regs: A D0{{$}}
// CHECK-NEXT: SubClasses: DA{{$}}
//
// CHECK-LABEL: Register A:
// CHECK-NEXT: CostPerUse: 0
// CHECK-NEXT: CoveredBySubregs: 0
// CHECK-NEXT: HasDisjunctSubRegs: 0
// CHECK-NEXT: RegUnit 0
// CHECK-NEXT: Artificial: 1
def TestTarget : Target;

10
llvm/test/TableGen/ArtificialSubregs.td
View File

@ -129,6 +129,7 @@ def TestTarget : Target;
// CHECK-NEXT: LaneMask: 0000000000000120
// CHECK-LABEL: SubRegIndex dsub_hi:
// CHECK-NEXT: LaneMask: 0000000000000001
// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex ssub:
// CHECK-NEXT: LaneMask: 0000000000000004
// CHECK-LABEL: SubRegIndex ssub0:
@ -139,10 +140,13 @@ def TestTarget : Target;
// CHECK-NEXT: LaneMask: 0000000000000020
// CHECK-LABEL: SubRegIndex ssub_hi:
// CHECK-NEXT: LaneMask: 0000000000000040
// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex dsub1_then_ssub_hi:
// CHECK-NEXT: LaneMask: 0000000000000080
// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex dsub2_then_ssub_hi:
// CHECK-NEXT: LaneMask: 0000000000000100
// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex ssub_ssub1:
// CHECK-NEXT: LaneMask: 0000000000000014
// CHECK-LABEL: SubRegIndex dsub0_dsub1:
@ -174,6 +178,12 @@ def TestTarget : Target;
// CHECK: CoveredBySubregs: 0
// CHECK: HasDisjunctSubRegs: 0
//
// CHECK-LABEL: Register D0_HI:
// CHECK: Artificial: 1
//
// CHECK-LABEL: Register S0_HI:
// CHECK: Artificial: 1
//
// CHECK-LABEL: Register D0_D1:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 1

6
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -1990,6 +1990,8 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
OS << " " << SRC->getName();
}
OS << '\n';
if (RC.Artificial)
OS << "\tArtificial: 1\n";
}
for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {
@ -2002,6 +2004,8 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
OS << "\tSize: " << printByHwMode(SRI.Range, [](const SubRegRange &Info) {
return Info.Size;
}) << '\n';
if (SRI.Artificial)
OS << "\tArtificial: 1\n";
}
for (const CodeGenRegister &R : RegBank.getRegisters()) {
@ -2018,6 +2022,8 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
}
for (unsigned U : R.getNativeRegUnits())
OS << "\tRegUnit " << U << '\n';
if (R.Artificial)
OS << "\tArtificial: 1\n";
}
}