[AArch64] Allow peephole to optimize AND + signed compare with 0 (#153608)
This should be the peephole's job. Because and sets V flag to 0, this is why signed comparisons with 0 are okay to replace with tst. Note this is only for AArch64, because ANDS on ARM leaves the V flag the same. Fixes: https://github.com/llvm/llvm-project/issues/154387
This commit is contained in:
AZero13
GitHub
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d5125b3089
commit
7b12a08f5e
@ -1780,6 +1780,16 @@ static unsigned sForm(MachineInstr &Instr) {
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case AArch64::SUBSWri:
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case AArch64::SUBSXrr:
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case AArch64::SUBSXri:
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case AArch64::ANDSWri:
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case AArch64::ANDSWrr:
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case AArch64::ANDSWrs:
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case AArch64::ANDSXri:
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case AArch64::ANDSXrr:
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case AArch64::ANDSXrs:
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case AArch64::BICSWrr:
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case AArch64::BICSXrr:
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case AArch64::BICSWrs:
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case AArch64::BICSXrs:
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return Instr.getOpcode();
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case AArch64::ADDWrr:
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@ -1810,6 +1820,22 @@ static unsigned sForm(MachineInstr &Instr) {
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return AArch64::ANDSWri;
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case AArch64::ANDXri:
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return AArch64::ANDSXri;
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case AArch64::ANDWrr:
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return AArch64::ANDSWrr;
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case AArch64::ANDWrs:
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return AArch64::ANDSWrs;
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case AArch64::ANDXrr:
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return AArch64::ANDSXrr;
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case AArch64::ANDXrs:
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return AArch64::ANDSXrs;
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case AArch64::BICWrr:
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return AArch64::BICSWrr;
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case AArch64::BICXrr:
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return AArch64::BICSXrr;
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case AArch64::BICWrs:
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return AArch64::BICSWrs;
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case AArch64::BICXrs:
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return AArch64::BICSXrs;
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}
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}
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@ -1947,6 +1973,25 @@ static bool isSUBSRegImm(unsigned Opcode) {
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return Opcode == AArch64::SUBSWri || Opcode == AArch64::SUBSXri;
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}
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static bool isANDOpcode(MachineInstr &MI) {
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unsigned Opc = sForm(MI);
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switch (Opc) {
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case AArch64::ANDSWri:
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case AArch64::ANDSWrr:
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case AArch64::ANDSWrs:
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case AArch64::ANDSXri:
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case AArch64::ANDSXrr:
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case AArch64::ANDSXrs:
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case AArch64::BICSWrr:
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case AArch64::BICSXrr:
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case AArch64::BICSWrs:
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case AArch64::BICSXrs:
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return true;
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default:
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return false;
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}
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}
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/// Check if CmpInstr can be substituted by MI.
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///
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/// CmpInstr can be substituted:
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@ -1984,7 +2029,8 @@ static bool canInstrSubstituteCmpInstr(MachineInstr &MI, MachineInstr &CmpInstr,
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// 1) MI and CmpInstr set N and V to the same value.
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// 2) If MI is add/sub with no-signed-wrap, it produces a poison value when
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// signed overflow occurs, so CmpInstr could still be simplified away.
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if (NZVCUsed->V && !MI.getFlag(MachineInstr::NoSWrap))
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// Note that Ands and Bics instructions always clear the V flag.
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if (NZVCUsed->V && !MI.getFlag(MachineInstr::NoSWrap) && !isANDOpcode(MI))
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return false;
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AccessKind AccessToCheck = AK_Write;
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55
llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp-signed.mir
Normal file
55
llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp-signed.mir
Normal file
@ -0,0 +1,55 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s
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--- |
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define i32 @test01() nounwind {
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entry:
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%0 = select i1 true, i32 1, i32 0
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%1 = and i32 %0, 65535
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%2 = icmp sgt i32 %1, 0
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br i1 %2, label %if.then, label %if.end
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if.then: ; preds = %entry
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ret i32 1
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if.end: ; preds = %entry
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ret i32 0
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}
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...
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---
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name: test01
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32common }
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body: |
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; CHECK-LABEL: name: test01
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32common = ANDSWri killed [[ANDSWri]], 15, implicit-def $nzcv
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; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.if.then:
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; CHECK-NEXT: $w0 = MOVi32imm 1
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.if.end:
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; CHECK-NEXT: $w0 = MOVi32imm 0
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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bb.0.entry:
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successors: %bb.2.if.end, %bb.1.if.then
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%0 = MOVi32imm 1
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%1 = ANDWri killed %1, 15
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$wzr = SUBSWri killed %1, 0, 0, implicit-def $nzcv
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Bcc 12, %bb.2.if.end, implicit $nzcv
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bb.1.if.then:
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$w0 = MOVi32imm 1
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RET_ReallyLR implicit $w0
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bb.2.if.end:
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$w0 = MOVi32imm 0
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RET_ReallyLR implicit $w0
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...
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@ -161,6 +161,338 @@ define i1 @lt64_u16_and_23(i64 %0) {
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ret i1 %3
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}
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define i1 @test_disjoint(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: tst w9, w8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp eq i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint2(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: tst w9, w8
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp sgt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint3(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: tst w9, w8
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp slt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint4(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: cset w8, lt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp sle i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_inverse_4(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint_inverse_4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bic w8, w9, w8
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: cset w8, lt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp sle i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_inverse(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bics wzr, w9, w8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp eq i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint2_inverse(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint2_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bics wzr, w9, w8
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp sgt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint3_inverse(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint3_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bics wzr, w9, w8
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp slt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: tst x9, x8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp eq i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint2_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint2_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: tst x9, x8
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp sgt i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint3_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint3_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: tst x9, x8
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp slt i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint4_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint4_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: and x8, x9, x8
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; CHECK-NEXT: cmp x8, #1
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; CHECK-NEXT: cset w8, lt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp sle i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_inverse_4_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint_inverse_4_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: bic x8, x9, x8
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; CHECK-NEXT: cmp x8, #1
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; CHECK-NEXT: cset w8, lt
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; CHECK-NEXT: orr w8, w0, w8
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%3 = or disjoint i64 %2, 36028797018963968
|
||||
%4 = shl nuw i64 1, %1
|
||||
%not = xor i64 %4, -1
|
||||
%5 = and i64 %3, %not
|
||||
%6 = icmp sle i64 %5, 0
|
||||
%7 = select i1 %0, i1 true, i1 %6
|
||||
ret i1 %7
|
||||
}
|
||||
|
||||
define i1 @test_disjoint_inverse_64(i1 %0, i64 %1, i64 %2) {
|
||||
; CHECK-LABEL: test_disjoint_inverse_64:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov w8, #1 // =0x1
|
||||
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
||||
; CHECK-NEXT: lsl x8, x8, x1
|
||||
; CHECK-NEXT: bics xzr, x9, x8
|
||||
; CHECK-NEXT: cset w8, eq
|
||||
; CHECK-NEXT: orr w8, w0, w8
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%3 = or disjoint i64 %2, 36028797018963968
|
||||
%4 = shl nuw i64 1, %1
|
||||
%not = xor i64 %4, -1
|
||||
%5 = and i64 %3, %not
|
||||
%6 = icmp eq i64 %5, 0
|
||||
%7 = select i1 %0, i1 true, i1 %6
|
||||
ret i1 %7
|
||||
}
|
||||
|
||||
define i1 @test_disjoint2_inverse_64(i1 %0, i64 %1, i64 %2) {
|
||||
; CHECK-LABEL: test_disjoint2_inverse_64:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov w8, #1 // =0x1
|
||||
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
||||
; CHECK-NEXT: lsl x8, x8, x1
|
||||
; CHECK-NEXT: bics xzr, x9, x8
|
||||
; CHECK-NEXT: cset w8, gt
|
||||
; CHECK-NEXT: orr w8, w0, w8
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%3 = or disjoint i64 %2, 36028797018963968
|
||||
%4 = shl nuw i64 1, %1
|
||||
%not = xor i64 %4, -1
|
||||
%5 = and i64 %3, %not
|
||||
%6 = icmp sgt i64 %5, 0
|
||||
%7 = select i1 %0, i1 true, i1 %6
|
||||
ret i1 %7
|
||||
}
|
||||
|
||||
define i1 @test_disjoint3_inverse_64(i1 %0, i64 %1, i64 %2) {
|
||||
; CHECK-LABEL: test_disjoint3_inverse_64:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: mov w8, #1 // =0x1
|
||||
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
||||
; CHECK-NEXT: lsl x8, x8, x1
|
||||
; CHECK-NEXT: bics xzr, x9, x8
|
||||
; CHECK-NEXT: cset w8, mi
|
||||
; CHECK-NEXT: orr w8, w0, w8
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%3 = or disjoint i64 %2, 36028797018963968
|
||||
%4 = shl nuw i64 1, %1
|
||||
%not = xor i64 %4, -1
|
||||
%5 = and i64 %3, %not
|
||||
%6 = icmp slt i64 %5, 0
|
||||
%7 = select i1 %0, i1 true, i1 %6
|
||||
ret i1 %7
|
||||
}
|
||||
|
||||
; negative test
|
||||
define i1 @lt3_u8(i8 %0) {
|
||||
; CHECK-LABEL: lt3_u8:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user