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[SelectionDAG] Use Register and MCRegister. NFC

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Add operators to Register to supporting adding an offset to get
another Register.
This commit is contained in:
Craig Topper 2025-03-02 16:16:19 -08:00
parent 0301580580
commit 7bd2be4266
18 changed files with 75 additions and 57 deletions
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4
llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
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@ -180,13 +180,13 @@ public:
/// be updated after processing the current basic block.
/// TODO: This isn't per-function state, it's per-basic-block state. But
/// there's no other convenient place for it to live right now.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
std::vector<std::pair<MachineInstr*, Register>> PHINodesToUpdate;
unsigned OrigNumPHINodesToUpdate;
/// If the current MBB is a landing pad, the exception pointer and exception
/// selector registers are copied into these virtual registers by
/// SelectionDAGISel::PrepareEHLandingPad().
unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
Register ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
/// The current call site index being processed, if any. 0 if none.
unsigned CurCallSite = 0;

20
llvm/include/llvm/CodeGen/Register.h
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@ -134,6 +134,26 @@ public:
constexpr bool operator!=(MCPhysReg Other) const {
return Reg != unsigned(Other);
}
/// Operators to move from one register to another nearby register by adding
/// an offset.
Register &operator++() {
assert(isValid());
++Reg;
return *this;
}
Register operator++(int) {
Register R(*this);
++(*this);
return R;
}
Register &operator+=(unsigned RHS) {
assert(isValid());
Reg += RHS;
return *this;
}
};
// Provide DenseMapInfo for Register

2
llvm/include/llvm/CodeGen/SelectionDAG.h
View File

@ -1767,7 +1767,7 @@ public:
/// Creates a VReg SDDbgValue node.
SDDbgValue *getVRegDbgValue(DIVariable *Var, DIExpression *Expr,
unsigned VReg, bool IsIndirect,
Register VReg, bool IsIndirect,
const DebugLoc &DL, unsigned O);
/// Creates a SDDbgValue node from a list of locations.

2
llvm/include/llvm/CodeGen/TargetLowering.h
View File

@ -4523,7 +4523,7 @@ public:
virtual bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII,
unsigned &PhysReg, int &Cost) const {
MCRegister &PhysReg, int &Cost) const {
return false;
}

2
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -2304,7 +2304,7 @@ bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
return false;
}
FuncInfo.PHINodesToUpdate.push_back(std::make_pair(&*MBBI++, Reg));
FuncInfo.PHINodesToUpdate.emplace_back(&*MBBI++, Reg);
MIMD = {};
}
}

4
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -295,7 +295,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
continue;
DebugLoc DL = PN.getDebugLoc();
unsigned PHIReg = ValueMap[&PN];
Register PHIReg = ValueMap[&PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
SmallVector<EVT, 4> ValueVTs;
@ -578,7 +578,7 @@ FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
ValueVTs.clear();
ComputeValueVTs(*TLI, Fn->getDataLayout(),
P.first->getType(), ValueVTs);
unsigned Reg = P.second;
Register Reg = P.second;
for (EVT VT : ValueVTs) {
unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
for (unsigned i = 0, e = NumRegisters; i != e; ++i)

4
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -827,7 +827,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
//
// i.e., point the instruction at the vreg, and patch it up later in
// MachineFunction::finalizeDebugInstrRefs.
auto AddVRegOp = [&](unsigned VReg) {
auto AddVRegOp = [&](Register VReg) {
MOs.push_back(MachineOperand::CreateReg(
/* Reg */ VReg, /* isDef */ false, /* isImp */ false,
/* isKill */ false, /* isDead */ false,
@ -840,7 +840,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
// Try to find both the defined register and the instruction defining it.
MachineInstr *DefMI = nullptr;
unsigned VReg;
Register VReg;
if (DbgOperand.getKind() == SDDbgOperand::VREG) {
VReg = DbgOperand.getVReg();

7
llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
View File

@ -13,6 +13,7 @@
#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SDNODEDBGVALUE_H
#define LLVM_LIB_CODEGEN_SELECTIONDAG_SDNODEDBGVALUE_H
#include "llvm/CodeGen/Register.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/DataTypes.h"
@ -63,7 +64,7 @@ public:
}
/// Returns the Virtual Register for a VReg
unsigned getVReg() const {
Register getVReg() const {
assert(kind == VREG);
return u.VReg;
}
@ -74,8 +75,8 @@ public:
static SDDbgOperand fromFrameIdx(unsigned FrameIdx) {
return SDDbgOperand(FrameIdx, FRAMEIX);
}
static SDDbgOperand fromVReg(unsigned VReg) {
return SDDbgOperand(VReg, VREG);
static SDDbgOperand fromVReg(Register VReg) {
return SDDbgOperand(VReg.id(), VREG);
}
static SDDbgOperand fromConst(const Value *Const) {
return SDDbgOperand(Const);

6
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -436,7 +436,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
/// CheckForLiveRegDef - Return true and update live register vector if the
/// specified register def of the specified SUnit clobbers any "live" registers.
static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
static bool CheckForLiveRegDef(SUnit *SU, MCRegister Reg,
std::vector<SUnit *> &LiveRegDefs,
SmallSet<unsigned, 4> &RegAdded,
SmallVectorImpl<unsigned> &LRegs,
@ -501,8 +501,8 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
F.isClobberKind()) {
// Check for def of register or earlyclobber register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
if (Register::isPhysicalRegister(Reg))
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
if (Reg.isPhysical())
CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
}
} else

2
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -1292,7 +1292,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
/// CheckForLiveRegDef - Return true and update live register vector if the
/// specified register def of the specified SUnit clobbers any "live" registers.
static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs,
static void CheckForLiveRegDef(SUnit *SU, MCRegister Reg, SUnit **LiveRegDefs,
SmallSet<unsigned, 4> &RegAdded,
SmallVectorImpl<unsigned> &LRegs,
const TargetRegisterInfo *TRI,

19
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -112,15 +112,15 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII,
const TargetLowering &TLI,
unsigned &PhysReg, int &Cost) {
MCRegister &PhysReg, int &Cost) {
if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
return;
unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
Register Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (TLI.checkForPhysRegDependency(Def, User, Op, TRI, TII, PhysReg, Cost))
return;
if (Register::isVirtualRegister(Reg))
if (Reg.isVirtual())
return;
unsigned ResNo = User->getOperand(2).getResNo();
@ -133,7 +133,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
PhysReg = Reg;
}
if (PhysReg != 0) {
if (PhysReg) {
const TargetRegisterClass *RC =
TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
Cost = RC->getCopyCost();
@ -487,20 +487,19 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
bool isChain = OpVT == MVT::Other;
unsigned PhysReg = 0;
MCRegister PhysReg;
int Cost = 1;
// Determine if this is a physical register dependency.
const TargetLowering &TLI = DAG->getTargetLoweringInfo();
CheckForPhysRegDependency(OpN, N, i, TRI, TII, TLI, PhysReg, Cost);
assert((PhysReg == 0 || !isChain) &&
"Chain dependence via physreg data?");
assert((!PhysReg || !isChain) && "Chain dependence via physreg data?");
// FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
// emits a copy from the physical register to a virtual register unless
// it requires a cross class copy (cost < 0). That means we are only
// treating "expensive to copy" register dependency as physical register
// dependency. This may change in the future though.
if (Cost >= 0 && !StressSched)
PhysReg = 0;
PhysReg = MCRegister();
// If this is a ctrl dep, latency is 1.
unsigned OpLatency = isChain ? 1 : OpSU->Latency;
@ -664,8 +663,8 @@ void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
if (Latency > 1U && Use->getOpcode() == ISD::CopyToReg &&
!BB->succ_empty()) {
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (Register::isVirtualRegister(Reg))
Register Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (Reg.isVirtual())
// This copy is a liveout value. It is likely coalesced, so reduce the
// latency so not to penalize the def.
// FIXME: need target specific adjustment here?

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -11345,7 +11345,7 @@ SDDbgValue *SelectionDAG::getFrameIndexDbgValue(DIVariable *Var,
/// VReg
SDDbgValue *SelectionDAG::getVRegDbgValue(DIVariable *Var, DIExpression *Expr,
unsigned VReg, bool IsIndirect,
Register VReg, bool IsIndirect,
const DebugLoc &DL, unsigned O) {
assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
"Expected inlined-at fields to agree");

29
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -908,8 +908,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
// If the source register was virtual and if we know something about it,
// add an assert node.
if (!Register::isVirtualRegister(Regs[Part + i]) ||
!RegisterVT.isInteger())
if (!Regs[Part + i].isVirtual() || !RegisterVT.isInteger())
continue;
const FunctionLoweringInfo::LiveOutInfo *LOI =
@ -1023,7 +1022,7 @@ void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
InlineAsm::Flag Flag(Code, Regs.size());
if (HasMatching)
Flag.setMatchingOp(MatchingIdx);
else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
else if (!Regs.empty() && Regs.front().isVirtual()) {
// Put the register class of the virtual registers in the flag word. That
// way, later passes can recompute register class constraints for inline
// assembly as well as normal instructions.
@ -1061,7 +1060,7 @@ void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
RegisterVT);
for (unsigned i = 0; i != NumRegs; ++i) {
assert(Reg < Regs.size() && "Mismatch in # registers expected");
unsigned TheReg = Regs[Reg++];
Register TheReg = Regs[Reg++];
Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
}
}
@ -1660,7 +1659,7 @@ bool SelectionDAGBuilder::handleDebugValue(ArrayRef<const Value *> Values,
// an associated VReg, we can refer to that instead.
auto VMI = FuncInfo.ValueMap.find(V);
if (VMI != FuncInfo.ValueMap.end()) {
unsigned Reg = VMI->second;
Register Reg = VMI->second;
// If this is a PHI node, it may be split up into several MI PHI nodes
// (in FunctionLoweringInfo::set).
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
@ -10138,9 +10137,8 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
auto DetectWriteToReservedRegister = [&]() {
const MachineFunction &MF = DAG.getMachineFunction();
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
for (unsigned Reg : OpInfo.AssignedRegs.Regs) {
if (Register::isPhysicalRegister(Reg) &&
TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
for (Register Reg : OpInfo.AssignedRegs.Regs) {
if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
const char *RegName = TRI.getName(Reg);
emitInlineAsmError(Call, "write to reserved register '" +
Twine(RegName) + "'");
@ -11396,13 +11394,13 @@ SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
}
void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V,
unsigned Reg,
Register Reg,
ISD::NodeType ExtendType) {
SDValue Op = getNonRegisterValue(V);
assert((Op.getOpcode() != ISD::CopyFromReg ||
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
"Copy from a reg to the same reg!");
assert(!Register::isPhysicalRegister(Reg) && "Is a physreg");
assert(!Reg.isPhysical() && "Is a physreg");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
// If this is an InlineAsm we have to match the registers required, not the
@ -12016,12 +12014,12 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
if (PN.getType()->isEmptyTy())
continue;
unsigned Reg;
Register Reg;
const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
if (const auto *C = dyn_cast<Constant>(PHIOp)) {
unsigned &RegOut = ConstantsOut[C];
if (RegOut == 0) {
Register &RegOut = ConstantsOut[C];
if (!RegOut) {
RegOut = FuncInfo.CreateRegs(C);
// We need to zero/sign extend ConstantInt phi operands to match
// assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo.
@ -12053,8 +12051,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
for (EVT VT : ValueVTs) {
const unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
for (unsigned i = 0; i != NumRegisters; ++i)
FuncInfo.PHINodesToUpdate.push_back(
std::make_pair(&*MBBI++, Reg + i));
FuncInfo.PHINodesToUpdate.emplace_back(&*MBBI++, Reg + i);
Reg += NumRegisters;
}
}
@ -12761,7 +12758,7 @@ void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
unsigned InitialDef = FuncInfo.ValueMap[CBR];
Register InitialDef = FuncInfo.ValueMap[CBR];
SDValue Chain = DAG.getRoot();
// Re-parse the asm constraints string.

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -254,7 +254,7 @@ public:
// Emit PHI-node-operand constants only once even if used by multiple
// PHI nodes.
DenseMap<const Constant *, unsigned> ConstantsOut;
DenseMap<const Constant *, Register> ConstantsOut;
/// Information about the function as a whole.
FunctionLoweringInfo &FuncInfo;
@ -320,7 +320,7 @@ public:
return CurInst ? CurInst->getDebugLoc() : DebugLoc();
}
void CopyValueToVirtualRegister(const Value *V, unsigned Reg,
void CopyValueToVirtualRegister(const Value *V, Register Reg,
ISD::NodeType ExtendType = ISD::ANY_EXTEND);
void visit(const Instruction &I);

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
View File

@ -989,7 +989,7 @@ LLVM_DUMP_METHOD void SDDbgValue::print(raw_ostream &OS) const {
OS << "FRAMEIX=" << Op.getFrameIx();
break;
case SDDbgOperand::VREG:
OS << "VREG=" << Op.getVReg();
OS << "VREG=" << printReg(Op.getVReg());
break;
}
Comma = true;

17
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1424,10 +1424,10 @@ bool SelectionDAGISel::PrepareEHLandingPad() {
if (hasExceptionPointerOrCodeUser(CPI)) {
// Get or create the virtual register to hold the pointer or code. Mark
// the live in physreg and copy into the vreg.
MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
MCRegister EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
assert(EHPhysReg && "target lacks exception pointer register");
MBB->addLiveIn(EHPhysReg);
unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
Register VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
TII->get(TargetOpcode::COPY), VReg)
.addReg(EHPhysReg, RegState::Kill);
@ -1457,10 +1457,10 @@ bool SelectionDAGISel::PrepareEHLandingPad() {
// Assign the call site to the landing pad's begin label.
MF->setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
// Mark exception register as live in.
if (unsigned Reg = TLI->getExceptionPointerRegister(PersonalityFn))
if (MCRegister Reg = TLI->getExceptionPointerRegister(PersonalityFn))
FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
// Mark exception selector register as live in.
if (unsigned Reg = TLI->getExceptionSelectorRegister(PersonalityFn))
if (MCRegister Reg = TLI->getExceptionSelectorRegister(PersonalityFn))
FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
}
@ -1737,8 +1737,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
FuncInfo->InsertPt = FuncInfo->MBB->end();
// Setup an EH landing-pad block.
FuncInfo->ExceptionPointerVirtReg = 0;
FuncInfo->ExceptionSelectorVirtReg = 0;
FuncInfo->ExceptionPointerVirtReg = Register();
FuncInfo->ExceptionSelectorVirtReg = Register();
if (LLVMBB->isEHPad())
if (!PrepareEHLandingPad())
continue;
@ -1931,7 +1931,8 @@ SelectionDAGISel::FinishBasicBlock() {
for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e;
++i) dbgs()
<< "Node " << i << " : (" << FuncInfo->PHINodesToUpdate[i].first
<< ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
<< ", " << printReg(FuncInfo->PHINodesToUpdate[i].second)
<< ")\n");
// Next, now that we know what the last MBB the LLVM BB expanded is, update
// PHI nodes in successors.
@ -2060,7 +2061,7 @@ SelectionDAGISel::FinishBasicBlock() {
}
// Update PHI Nodes
for (const std::pair<MachineInstr *, unsigned> &P :
for (const std::pair<MachineInstr *, Register> &P :
FuncInfo->PHINodesToUpdate) {
MachineInstrBuilder PHI(*MF, P.first);
MachineBasicBlock *PHIBB = PHI->getParent();

2
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -17134,7 +17134,7 @@ SITargetLowering::getTargetMMOFlags(const Instruction &I) const {
bool SITargetLowering::checkForPhysRegDependency(
SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const {
const TargetInstrInfo *TII, MCRegister &PhysReg, int &Cost) const {
if (User->getOpcode() != ISD::CopyToReg)
return false;
if (!Def->isMachineOpcode())

4
llvm/lib/Target/AMDGPU/SIISelLowering.h
View File

@ -538,8 +538,8 @@ public:
bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII, unsigned &PhysReg,
int &Cost) const override;
const TargetInstrInfo *TII,
MCRegister &PhysReg, int &Cost) const override;
bool isProfitableToHoist(Instruction *I) const override;