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[RISCV] Add another packh+packw pattern. (#152744)

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If the upper 32 bits are demanded, we might have a sext_inreg in
the pattern on the byte shifted by 24. We can also match this case
since packw sign extends from bit 31.
This commit is contained in:
Craig Topper 2025-08-09 09:23:44 -05:00 committed by GitHub
parent 92a966bd8f
commit 7fb8630e71
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5
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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@ -692,6 +692,11 @@ def : Pat<(binop_allwusers<or>
(shl GPR:$op1rs1, (XLenVT 24))),
(shl (zexti8 (XLenVT GPR:$op1rs2)), (XLenVT 16))),
(PACKW GPR:$rs1, (XLenVT (PACKH GPR:$op1rs1, GPR:$op1rs2)))>;
def : Pat<(i64 (or (or (zexti16 (XLenVT GPR:$rs1)),
(shl (zexti8 (XLenVT GPR:$op1rs2)), (XLenVT 16))),
(sext_inreg (shl GPR:$op1rs1, (XLenVT 24)), i32))),
(PACKW GPR:$rs1, (XLenVT (PACKH GPR:$op1rs1, GPR:$op1rs2)))>;
} // Predicates = [HasStdExtZbkb, IsRV64]
let Predicates = [HasStdExtZbb, IsRV32] in

30
llvm/test/CodeGen/RISCV/rv64zbkb.ll
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@ -495,6 +495,36 @@ define void @pack_lo_packh_hi_packh_3(i8 %0, i8 %1, i8 %2, i8 %3, ptr %p) nounwi
ret void
}
define i32 @pack_lo_packh_hi_packh_4(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {
; RV64I-LABEL: pack_lo_packh_hi_packh_4:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: slli a2, a2, 16
; RV64I-NEXT: slliw a3, a3, 24
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret
;
; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_4:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: packh a0, a0, a1
; RV64ZBKB-NEXT: packh a1, a3, a2
; RV64ZBKB-NEXT: packw a0, a0, a1
; RV64ZBKB-NEXT: ret
%a = zext i8 %0 to i32
%b = zext i8 %1 to i32
%c = zext i8 %2 to i32
%d = zext i8 %3 to i32
%e = shl i32 %b, 8
%f = shl i32 %c, 16
%g = shl i32 %d, 24
%h = or i32 %a, %e
%i = or i32 %h, %f
%j = or i32 %i, %g
ret i32 %j
}
define void @pack_lo_zext_hi_packh(i16 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) nounwind {
; RV64I-LABEL: pack_lo_zext_hi_packh:
; RV64I: # %bb.0: