[AArch64][SVE] Add missing patterns for unpredicated subr intrinsics
Differential Revision: https://reviews.llvm.org/D109369
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Bradley Smith
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55d9396278
commit
8089f9ed5a
@ -14517,20 +14517,20 @@ static bool isAllActivePredicate(SDValue N) {
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// or unpredicated operation, which potentially allows better isel (perhaps
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// using immediate forms) or relaxing register reuse requirements.
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static SDValue convertMergedOpToPredOp(SDNode *N, unsigned Opc,
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SelectionDAG &DAG,
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bool UnpredOp = false) {
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SelectionDAG &DAG, bool UnpredOp = false,
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bool SwapOperands = false) {
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assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN && "Expected intrinsic!");
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assert(N->getNumOperands() == 4 && "Expected 3 operand intrinsic!");
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SDValue Pg = N->getOperand(1);
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SDValue Op1 = N->getOperand(SwapOperands ? 3 : 2);
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SDValue Op2 = N->getOperand(SwapOperands ? 2 : 3);
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// ISD way to specify an all active predicate.
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if (isAllActivePredicate(Pg)) {
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if (UnpredOp)
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return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), N->getOperand(2),
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N->getOperand(3));
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else
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return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Pg,
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N->getOperand(2), N->getOperand(3));
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return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Op1, Op2);
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return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Pg, Op1, Op2);
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}
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// FUTURE: SplatVector(true)
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@ -14652,6 +14652,8 @@ static SDValue performIntrinsicCombine(SDNode *N,
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return convertMergedOpToPredOp(N, ISD::ADD, DAG, true);
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case Intrinsic::aarch64_sve_sub:
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return convertMergedOpToPredOp(N, ISD::SUB, DAG, true);
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case Intrinsic::aarch64_sve_subr:
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return convertMergedOpToPredOp(N, ISD::SUB, DAG, true, true);
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case Intrinsic::aarch64_sve_and:
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return convertMergedOpToPredOp(N, ISD::AND, DAG, true);
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case Intrinsic::aarch64_sve_bic:
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@ -263,6 +263,159 @@ define <vscale x 4 x i32> @sub_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {
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ret <vscale x 4 x i32> %out
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}
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; SUBR
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define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: subr_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subr z0.b, z0.b, #127
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; CHECK-NEXT: ret
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%pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%elt = insertelement <vscale x 16 x i8> undef, i8 127, i32 0
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%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %splat)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: subr_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subr z0.h, z0.h, #127
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; CHECK-NEXT: ret
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%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%elt = insertelement <vscale x 8 x i16> undef, i16 127, i32 0
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%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %splat)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 8 x i16> @subr_i16_out_of_range(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: subr_i16_out_of_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #257
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; CHECK-NEXT: mov z1.h, w8
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; CHECK-NEXT: sub z0.h, z1.h, z0.h
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; CHECK-NEXT: ret
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%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0
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%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %splat)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: subr_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subr z0.s, z0.s, #127
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; CHECK-NEXT: ret
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%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%elt = insertelement <vscale x 4 x i32> undef, i32 127, i32 0
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%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %splat)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @subr_i32_out_of_range(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: subr_i32_out_of_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #257
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; CHECK-NEXT: mov z1.s, w8
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; CHECK-NEXT: sub z0.s, z1.s, z0.s
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; CHECK-NEXT: ret
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%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0
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%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %splat)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: subr_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subr z0.d, z0.d, #127
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; CHECK-NEXT: ret
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%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%elt = insertelement <vscale x 2 x i64> undef, i64 127, i64 0
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%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %splat)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 2 x i64> @subr_i64_out_of_range(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: subr_i64_out_of_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #257
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; CHECK-NEXT: mov z1.d, x8
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; CHECK-NEXT: sub z0.d, z1.d, z0.d
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; CHECK-NEXT: ret
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%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%elt = insertelement <vscale x 2 x i64> undef, i64 257, i64 0
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%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %splat)
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ret <vscale x 2 x i64> %out
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}
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; As subr_i32 but where pg is i8 based and thus compatible for i32.
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define <vscale x 4 x i32> @subr_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: subr_i32_ptrue_all_b:
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; CHECK: subr z0.s, z0.s, #1
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; CHECK-NEXT: ret
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%pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
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%b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)
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%out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s,
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<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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; As subr_i32 but where pg is i16 based and thus compatible for i32.
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define <vscale x 4 x i32> @subr_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: subr_i32_ptrue_all_h:
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; CHECK: subr z0.s, z0.s, #1
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; CHECK-NEXT: ret
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%pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)
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%pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
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%b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)
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%out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s,
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<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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; As subr_i32 but where pg is i64 based, which is not compatibile for i32 and
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; thus inactive lanes are important and the immediate form cannot be used.
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define <vscale x 4 x i32> @subr_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: subr_i32_ptrue_all_d:
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; CHECK-DAG: ptrue [[PG:p[0-9]+]].d
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; CHECK-DAG: mov [[DUP:z[0-9]+]].s, #1
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; CHECK-DAG: subr z0.s, [[PG]]/m, z0.s, [[DUP]].s
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; CHECK-NEXT: ret
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%pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)
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%pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
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%b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)
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%out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s,
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<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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; SMAX
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define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i8> %a) {
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@ -1894,6 +2047,11 @@ declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vsc
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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