[LoongArch] Pre-commit tests for vecreduce_and/or/... (#154879)
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95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll
Normal file
@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_and_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v16i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll
Normal file
@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_or_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_or_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_or_v16i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_or_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_or_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_or_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_or_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_or_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll
Normal file
@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_smax_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smax_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smax_v16i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smax_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smax_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smax_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smax_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smax_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll
Normal file
@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_smin_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v32i8:
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; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
|
||||
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <32 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v16i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v8i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v4i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
|
||||
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
|
||||
; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
|
||||
; CHECK-NEXT: xvmin.d $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.d $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll
Normal file
@ -0,0 +1,95 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_umax_v32i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v32i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
|
||||
; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <32 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v16i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v8i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmax.wu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmax.wu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmax.wu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v4i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
|
||||
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
|
||||
; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
|
||||
; CHECK-NEXT: xvmax.du $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmax.du $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll
Normal file
@ -0,0 +1,95 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_umin_v32i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v32i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
|
||||
; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <32 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v16i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v8i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvmin.wu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvmin.wu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.wu $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v4i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
|
||||
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
|
||||
; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
|
||||
; CHECK-NEXT: xvmin.du $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvmin.du $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll
Normal file
95
llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll
Normal file
@ -0,0 +1,95 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_xor_v32i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v32i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <32 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v16i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v8i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v4i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xvld $xr0, $a0, 0
|
||||
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
|
||||
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
|
||||
; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
|
||||
; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
|
||||
; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
|
||||
; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
|
||||
; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_and_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_and_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_and_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_or_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_or_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_or_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_smax_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smax_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smax_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.d $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_smin_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_smin_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_smin_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.d $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_umax_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umax_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umax_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmax.du $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_umin_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_umin_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_umin_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vmin.du $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
Normal file
168
llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
Normal file
@ -0,0 +1,168 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
|
||||
|
||||
define void @vec_reduce_xor_v16i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <16 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v8i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v4i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v2i8(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.h $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i8>, ptr %src
|
||||
%res = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v)
|
||||
store i8 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v8i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <8 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v4i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v2i16(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.w $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i16>, ptr %src
|
||||
%res = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v)
|
||||
store i16 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v4i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <4 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v2i32(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ld.d $a0, $a0, 0
|
||||
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i32>, ptr %src
|
||||
%res = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v)
|
||||
store i32 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vec_reduce_xor_v2i64(ptr %src, ptr %dst) nounwind {
|
||||
; CHECK-LABEL: vec_reduce_xor_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vld $vr0, $a0, 0
|
||||
; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
|
||||
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
|
||||
; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
|
||||
; CHECK-NEXT: ret
|
||||
%v = load <2 x i64>, ptr %src
|
||||
%res = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %v)
|
||||
store i64 %res, ptr %dst
|
||||
ret void
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user