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This commit is contained in:
pvanhout 2025-08-22 10:12:03 +02:00
parent 3b51b225ba
commit 857644e104
2 changed files with 5 additions and 4 deletions
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7
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
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@ -590,7 +590,7 @@ public:
SIGfx12CacheControl(const GCNSubtarget &ST) : SIGfx11CacheControl(ST) {
// GFX12.0 and GFX12.5 memory models greatly overlap, and in some cases
// the behavior is the same if assuming GFX12.0 in CU mode.
assert(ST.hasGFX1250Insts() ? ST.isCuModeEnabled() : true);
assert(!ST.hasGFX1250Insts() || ST.isCuModeEnabled());
}
bool insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
@ -2592,14 +2592,15 @@ bool SIGfx12CacheControl::finalizeStore(MachineInstr &MI, bool Atomic) const {
const bool IsRMW = (MI.mayLoad() && MI.mayStore());
bool Changed = false;
// GFX12.5 only: xcnt wait is needed before flat and global atomics stores/rmw
// GFX12.5 only: xcnt wait is needed before flat and global atomics
// stores/rmw.
if (Atomic && ST.requiresWaitXCntBeforeAtomicStores() && TII->isFLAT(MI)) {
MachineBasicBlock &MBB = *MI.getParent();
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(S_WAIT_XCNT_soft)).addImm(0);
Changed = true;
}
// Remaining fixes do not apply to RMWs
// Remaining fixes do not apply to RMWs.
if (IsRMW)
return Changed;

2
llvm/lib/Target/AMDGPU/SOPInstructions.td
View File

@ -1658,7 +1658,7 @@ let OtherPredicates = [HasImageInsts] in {
let SubtargetPredicate = HasWaitXcnt in {
def S_WAIT_XCNT_soft : SOPP_Pseudo<"s_soft_wait_xcnt", (ins s16imm:$simm16), "$simm16">;
def S_WAIT_XCNT_soft : SOPP_Pseudo<"", (ins s16imm:$simm16), "$simm16">;
}
// Represents the point at which a wave must wait for all outstanding direct loads to LDS.