From 857b68f112ecb61c43a9aa5bc50fc1e0e7dcaf57 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 10 Dec 2025 07:17:58 +0000 Subject: [PATCH] [MC] Reorder TARGETInstrTable to shrink MCInstrDesc::ImplicitOffset (#171199) Put ImplicitOps[] before OperandInfo[] in the generated TARGETInstrTable. This means that offsets to entries into the (small) ImplicitOps table do not need to skip over the (large) OperandInfo table. This allows shrinking ImplicitOffset from 32 bits to 16 bits (effectively reverting #138127) which will allow expanding Opcode instead without increasing the size of MCInstrDesc. --- llvm/include/llvm/MC/MCInstrDesc.h | 2 +- llvm/test/TableGen/RegClassByHwMode.td | 2 +- .../TableGen/target-specialized-pseudos.td | 12 ++--- llvm/utils/TableGen/InstrInfoEmitter.cpp | 46 ++++++++++++------- 4 files changed, 38 insertions(+), 24 deletions(-) diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h index 5722213347d5..69dd3e284883 100644 --- a/llvm/include/llvm/MC/MCInstrDesc.h +++ b/llvm/include/llvm/MC/MCInstrDesc.h @@ -211,7 +211,7 @@ public: unsigned char NumImplicitUses; // Num of regs implicitly used unsigned char NumImplicitDefs; // Num of regs implicitly defined unsigned short OpInfoOffset; // Offset to info about operands - unsigned int ImplicitOffset; // Offset to start of implicit op list + unsigned short ImplicitOffset; // Offset to start of implicit op list uint64_t Flags; // Flags identifying machine instr class uint64_t TSFlags; // Target Specific Flag values diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td index 56a61eec3732..a29c8747a7c2 100644 --- a/llvm/test/TableGen/RegClassByHwMode.td +++ b/llvm/test/TableGen/RegClassByHwMode.td @@ -24,7 +24,7 @@ include "Common/RegClassByHwModeCommon.td" // INSTRINFO-NEXT: } // namespace llvm::MyTarget -// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<= alignof(MCPhysReg), " + "\"Unwanted padding between Insts and ImplicitOps\");\n"; + OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U) + << "];\n"; + // Emit enough padding to make ImplicitOps plus Padding add up to the size + // of a whole number of MCOperandInfo structs. This allows us to index into + // the OperandInfo array starting from the end of the Insts array, by + // biasing the indices by the OpInfoBase value calculated below. + OS << " char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % " + "sizeof(MCOperandInfo)];\n"; OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), " "\"Unwanted padding between Insts and OperandInfo\");\n"; OS << " MCOperandInfo OperandInfo[" << OperandInfoSize << "];\n"; - OS << " static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), " - "\"Unwanted padding between OperandInfo and ImplicitOps\");\n"; - OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U) - << "];\n"; OS << "};"; } @@ -991,9 +997,12 @@ void InstrInfoEmitter::run(raw_ostream &OS) { // Emit all of the MCInstrDesc records in reverse ENUM ordering. Timer.startTimer("Emit InstrDesc records"); - OS << "static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);\n"; - OS << "static constexpr unsigned " << TargetName << "ImpOpBase = sizeof " - << TargetName << "InstrTable::OperandInfo / (sizeof(MCPhysReg));\n\n"; + OS << "static_assert((sizeof " << TargetName + << "InstrTable::ImplicitOps + sizeof " << TargetName + << "InstrTable::Padding) % sizeof(MCOperandInfo) == 0);\n"; + OS << "static constexpr unsigned " << TargetName << "OpInfoBase = (sizeof " + << TargetName << "InstrTable::ImplicitOps + sizeof " << TargetName + << "InstrTable::Padding) / sizeof(MCOperandInfo);\n\n"; OS << "extern const " << TargetName << "InstrTable " << TargetName << "Descs = {\n {\n"; @@ -1013,12 +1022,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << " }, {\n"; - // Emit all of the operand info records. - Timer.startTimer("Emit operand info"); - EmitOperandInfo(OS, OperandInfoList); - - OS << " }, {\n"; - // Emit all of the instruction's implicit uses and defs. Timer.startTimer("Emit uses/defs"); for (auto &List : ImplicitLists) { @@ -1028,6 +1031,17 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << '\n'; } + OS << " }, {\n"; + + // Emit the padding. + OS << " 0\n"; + + OS << " }, {\n"; + + // Emit all of the operand info records. + Timer.startTimer("Emit operand info"); + EmitOperandInfo(OS, OperandInfoList); + OS << " }\n};\n\n"; // Emit the array of instruction names. @@ -1291,11 +1305,11 @@ void InstrInfoEmitter::emitRecord( // Emit the operand info offset. OperandInfoTy OperandInfo = GetOperandInfo(Inst); - OS << OperandInfoMap.find(OperandInfo)->second << ",\t"; + OS << Target.getName() << "OpInfoBase + " + << OperandInfoMap.find(OperandInfo)->second << ",\t"; // Emit implicit operand base. - OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps] - << ",\t0"; + OS << EmittedLists[ImplicitOps] << ",\t0"; // Emit all of the target independent flags... if (Inst.isPreISelOpcode)