diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index faea931aeccd..29779fa28abc 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -3359,12 +3359,11 @@ static SDValue performAnyAllCombine(SDNode *N, SelectionDAG &DAG) {
       return SDValue();
 
     SDLoc DL(N);
-    SDValue Ret = DAG.getZExtOrTrunc(
-        DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
-                    {DAG.getConstant(InPost, DL, MVT::i32), LHS}),
-        DL, MVT::i1);
+    SDValue Ret = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+                              {DAG.getConstant(InPost, DL, MVT::i32), LHS});
     if (SetType == ISD::SETEQ)
-      Ret = DAG.getNOT(DL, Ret, MVT::i1);
+      Ret = DAG.getNode(ISD::XOR, DL, MVT::i32, Ret,
+                        DAG.getConstant(1, DL, MVT::i32));
     return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
   };
 
@@ -3397,13 +3396,13 @@ static SDValue TryMatchTrue(SDNode *N, EVT VecVT, SelectionDAG &DAG) {
     return SDValue();
 
   SDLoc DL(N);
-  SDValue Ret = DAG.getZExtOrTrunc(
+  SDValue Ret =
       DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
                   {DAG.getConstant(Intrin, DL, MVT::i32),
-                   DAG.getSExtOrTrunc(LHS->getOperand(0), DL, VecVT)}),
-      DL, MVT::i1);
+                   DAG.getSExtOrTrunc(LHS->getOperand(0), DL, VecVT)});
   if (RequiresNegate)
-    Ret = DAG.getNOT(DL, Ret, MVT::i1);
+    Ret = DAG.getNode(ISD::XOR, DL, MVT::i32, Ret,
+                      DAG.getConstant(1, DL, MVT::i32));
   return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
 }
 
diff --git a/llvm/test/CodeGen/WebAssembly/simd-memcmp.ll b/llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
new file mode 100644
index 000000000000..7756bad16f95
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
+target triple = "wasm32"
+
+declare void @llvm.memset.p0.i32(ptr writeonly, i8, i32, i1 immarg)
+declare i32 @memcmp(ptr noundef, ptr noundef, i32 noundef)
+
+define i1 @memcmp_zero(ptr %d) {
+; CHECK-LABEL: memcmp_zero:
+; CHECK:         .functype memcmp_zero (i32) -> (i32)
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.const 0, 0
+; CHECK-NEXT:    v128.store 0:p2align=0
+; CHECK-NEXT:    i32.const 0
+; CHECK-NEXT:    v128.load 0:p2align=0
+; CHECK-NEXT:    v128.any_true
+; CHECK-NEXT:    i32.const 1
+; CHECK-NEXT:    i32.ne
+; CHECK-NEXT:    # fallthrough-return
+entry:
+  call void @llvm.memset.p0.i32(ptr %d, i8 0, i32 16, i1 false)
+  %call = call i32 @memcmp(ptr null, ptr %d, i32 16)
+  %tobool.not = icmp eq i32 %call, 0
+  ret i1 %tobool.not
+}