From 87bec4715266a145fea6676a6f08a19de7bfc00f Mon Sep 17 00:00:00 2001 From: vangthao95 Date: Fri, 27 Mar 2026 10:10:09 -0700 Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for div_fmas/fixup/scale (#188305) --- .../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 20 + .../GlobalISel/constant-bus-restriction.ll | 32 +- .../AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll | 473 ++++++++---------- .../GlobalISel/llvm.amdgcn.div.scale.ll | 8 +- .../regbankselect-amdgcn.div.fmas.mir | 9 +- .../regbankselect-amdgcn.div.scale.mir | 3 +- .../AMDGPU/llvm.amdgcn.div.fixup.f16.ll | 265 ++++++++-- .../CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll | 19 +- 8 files changed, 481 insertions(+), 348 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index 198e52a6f9ae..682026482f40 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1739,4 +1739,24 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}}) .Div(S16, {{Vgpr16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}}); + addRulesForIOpcs({amdgcn_div_fmas}, Standard) + .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}}) + .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}}) + .Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr64, Vgpr64, Vcc}}) + .Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64, Vgpr64, Vgpr64, Vcc}}); + + addRulesForIOpcs({amdgcn_div_fixup}, Standard) + .Div(S16, {{Vgpr16}, {IntrId, Vgpr16, Vgpr16, Vgpr16}}) + .Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16, Vgpr16, Vgpr16}}) + .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}}) + .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}}) + .Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr64, Vgpr64}}) + .Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64, Vgpr64, Vgpr64}}); + + addRulesForIOpcs({amdgcn_div_scale}, Standard) + .Div(S32, {{Vgpr32, Vcc}, {IntrId, Vgpr32, Vgpr32}}) + .Uni(S32, {{UniInVgprS32, UniInVcc}, {IntrId, Vgpr32, Vgpr32}}) + .Div(S64, {{Vgpr64, Vcc}, {IntrId, Vgpr64, Vgpr64}}) + .Uni(S64, {{UniInVgprS64, UniInVcc}, {IntrId, Vgpr64, Vgpr64}}); + } // end initialize rules diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll index aceff554bafe..6d57f53860ed 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX10 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX10 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX11 %s ; Make sure we don't violate the constant bus restriction @@ -120,13 +120,17 @@ define amdgpu_ps float @fcmp_s_s(float inreg %src0, float inreg %src1) { ; GFX9: ; %bb.0: ; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s2, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc +; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 +; GFX9-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10PLUS-LABEL: fcmp_s_s: ; GFX10PLUS: ; %bb.0: ; GFX10PLUS-NEXT: v_cmp_eq_f32_e64 s0, s2, s3 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0 +; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10PLUS-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 ; GFX10PLUS-NEXT: ; return to shader part epilog %cmp = fcmp oeq float %src0, %src1 %result = select i1 %cmp, float 1.0, float 0.0 @@ -156,17 +160,17 @@ define amdgpu_ps float @select_vcc_s_s(float %cmp0, float %cmp1, float inreg %sr define amdgpu_ps float @select_vcc_fneg_s_s(float %cmp0, float %cmp1, float inreg %src0, float inreg %src1) { ; GFX9-LABEL: select_vcc_fneg_s_s: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -v3, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, -v2, vcc ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10PLUS-LABEL: select_vcc_fneg_s_s: ; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s2 +; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s3 ; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s3, -v2, vcc_lo +; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, -s2, vcc_lo ; GFX10PLUS-NEXT: ; return to shader part epilog %cmp = fcmp oeq float %cmp0, %cmp1 %neg.src0 = fneg float %src0 @@ -199,13 +203,17 @@ define amdgpu_ps float @class_s_s(float inreg %src0, i32 inreg %src1) { ; GFX9: ; %bb.0: ; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_cmp_class_f32_e32 vcc, s2, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc +; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 +; GFX9-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10PLUS-LABEL: class_s_s: ; GFX10PLUS: ; %bb.0: ; GFX10PLUS-NEXT: v_cmp_class_f32_e64 s0, s2, s3 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0 +; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10PLUS-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 ; GFX10PLUS-NEXT: ; return to shader part epilog %class = call i1 @llvm.amdgcn.class.f32(float %src0, i32 %src1) %result = select i1 %class, float 1.0, float 0.0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll index aa25294ba17b..bdf54bd66c86 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10_W32 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GFX10_W64 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11_W32 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GFX11_W64 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10_W32 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GFX10_W64 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11_W32 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GFX11_W64 %s define float @v_div_fmas_f32(float %a, float %b, float %c, i1 %d) { ; GFX7-LABEL: v_div_fmas_f32: @@ -118,69 +118,55 @@ define amdgpu_ps float @s_div_fmas_f32(float inreg %a, float inreg %b, float inr ; GFX7-LABEL: s_div_fmas_f32: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_cmp_eq_u32 s3, 0 -; GFX7-NEXT: s_cselect_b32 s3, 1, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 -; GFX7-NEXT: s_and_b32 s0, 1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v2, s2 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX7-NEXT: s_nop 3 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: s_div_fmas_f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_cmp_eq_u32 s3, 0 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 -; GFX8-NEXT: s_and_b32 s0, 1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_nop 3 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX10_W32-LABEL: s_div_fmas_f32: ; GFX10_W32: ; %bb.0: -; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1 -; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2 -; GFX10_W32-NEXT: s_and_b32 s3, 1, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 +; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX10_W32-NEXT: ; return to shader part epilog ; ; GFX10_W64-LABEL: s_div_fmas_f32: ; GFX10_W64: ; %bb.0: -; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1 -; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2 -; GFX10_W64-NEXT: s_and_b32 s3, 1, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 +; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX10_W64-NEXT: ; return to shader part epilog ; ; GFX11_W32-LABEL: s_div_fmas_f32: ; GFX11_W32: ; %bb.0: -; GFX11_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX11_W32-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s2 -; GFX11_W32-NEXT: s_cselect_b32 s3, 1, 0 -; GFX11_W32-NEXT: s_and_b32 s3, 1, s3 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 +; GFX11_W32-NEXT: s_cmp_eq_u32 s3, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX11_W32-NEXT: ; return to shader part epilog ; ; GFX11_W64-LABEL: s_div_fmas_f32: ; GFX11_W64: ; %bb.0: -; GFX11_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX11_W64-NEXT: v_mov_b32_e32 v0, s1 -; GFX11_W64-NEXT: s_cselect_b32 s3, 1, 0 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, s2 -; GFX11_W64-NEXT: s_and_b32 s3, 1, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 +; GFX11_W64-NEXT: s_cmp_eq_u32 s3, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX11_W64-NEXT: ; return to shader part epilog %vcc = icmp eq i32 %d, 0 @@ -192,16 +178,13 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double ; GFX7-LABEL: s_div_fmas_f64: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_cmp_eq_u32 s6, 0 -; GFX7-NEXT: s_cselect_b32 s6, 1, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 -; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v2, s2 ; GFX7-NEXT: v_mov_b32_e32 v4, s4 -; GFX7-NEXT: s_and_b32 s0, 1, s6 +; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v3, s3 ; GFX7-NEXT: v_mov_b32_e32 v5, s5 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX7-NEXT: s_nop 3 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX7-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5] ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s1, v1 @@ -210,16 +193,13 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double ; GFX8-LABEL: s_div_fmas_f64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_cmp_eq_u32 s6, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 -; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v4, s4 -; GFX8-NEXT: s_and_b32 s0, 1, s6 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s3 ; GFX8-NEXT: v_mov_b32_e32 v5, s5 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_nop 3 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5] ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 @@ -227,14 +207,12 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double ; ; GFX10_W32-LABEL: s_div_fmas_f64: ; GFX10_W32: ; %bb.0: -; GFX10_W32-NEXT: s_cmp_eq_u32 s6, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2 -; GFX10_W32-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v2, s4 -; GFX10_W32-NEXT: s_and_b32 s6, 1, s6 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 ; GFX10_W32-NEXT: v_mov_b32_e32 v3, s5 +; GFX10_W32-NEXT: s_cmp_eq_u32 s6, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] ; GFX10_W32-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10_W32-NEXT: v_readfirstlane_b32 s1, v1 @@ -242,14 +220,12 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double ; ; GFX10_W64-LABEL: s_div_fmas_f64: ; GFX10_W64: ; %bb.0: -; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 -; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4 -; GFX10_W64-NEXT: s_and_b32 s6, 1, s6 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5 +; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] ; GFX10_W64-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10_W64-NEXT: v_readfirstlane_b32 s1, v1 @@ -257,12 +233,10 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double ; ; GFX11_W32-LABEL: s_div_fmas_f64: ; GFX11_W32: ; %bb.0: -; GFX11_W32-NEXT: s_cmp_eq_u32 s6, 0 ; GFX11_W32-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11_W32-NEXT: s_cselect_b32 s6, 1, 0 ; GFX11_W32-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 -; GFX11_W32-NEXT: s_and_b32 s6, 1, s6 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 +; GFX11_W32-NEXT: s_cmp_eq_u32 s6, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] ; GFX11_W32-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11_W32-NEXT: v_readfirstlane_b32 s1, v1 @@ -270,14 +244,12 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double ; ; GFX11_W64-LABEL: s_div_fmas_f64: ; GFX11_W64: ; %bb.0: -; GFX11_W64-NEXT: s_cmp_eq_u32 s6, 0 ; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2 -; GFX11_W64-NEXT: s_cselect_b32 s6, 1, 0 ; GFX11_W64-NEXT: v_mov_b32_e32 v2, s4 -; GFX11_W64-NEXT: s_and_b32 s6, 1, s6 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX11_W64-NEXT: v_mov_b32_e32 v3, s5 +; GFX11_W64-NEXT: s_cmp_eq_u32 s6, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] ; GFX11_W64-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11_W64-NEXT: v_readfirstlane_b32 s1, v1 @@ -299,12 +271,11 @@ define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], f ; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v2, s6 -; GFX7-NEXT: s_and_b32 s2, 1, s7 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX7-NEXT: s_cmp_lg_u32 s7, 0 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s3, 0xf000 -; GFX7-NEXT: s_nop 1 -; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; @@ -318,11 +289,10 @@ define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], f ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: s_and_b32 s0, 1, s3 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX8-NEXT: s_nop 2 +; GFX8-NEXT: s_cmp_lg_u32 s3, 0 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f32 v2, v0, v1, v2 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -332,16 +302,16 @@ define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], f ; GFX10_W32-LABEL: test_div_fmas_f32: ; GFX10_W32: ; %bb.0: ; GFX10_W32-NEXT: s_clause 0x4 -; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x94 -; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x4c -; GFX10_W32-NEXT: s_load_dword s6, s[4:5], 0x70 +; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x4c +; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x70 +; GFX10_W32-NEXT: s_load_dword s6, s[4:5], 0x94 ; GFX10_W32-NEXT: s_load_dword s7, s[4:5], 0x28 ; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 -; GFX10_W32-NEXT: v_mov_b32_e32 v1, s6 +; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX10_W32-NEXT: s_cmp_lg_u32 s6, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s7, v0, v1 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[0:1] @@ -350,16 +320,16 @@ define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], f ; GFX10_W64-LABEL: test_div_fmas_f32: ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_clause 0x4 -; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x94 -; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x4c -; GFX10_W64-NEXT: s_load_dword s6, s[4:5], 0x70 +; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x4c +; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x70 +; GFX10_W64-NEXT: s_load_dword s6, s[4:5], 0x94 ; GFX10_W64-NEXT: s_load_dword s7, s[4:5], 0x28 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 -; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6 +; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3 +; GFX10_W64-NEXT: s_cmp_lg_u32 s6, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s7, v0, v1 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[0:1] @@ -368,15 +338,15 @@ define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], f ; GFX11_W32-LABEL: test_div_fmas_f32: ; GFX11_W32: ; %bb.0: ; GFX11_W32-NEXT: s_clause 0x4 -; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x94 -; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x4c -; GFX11_W32-NEXT: s_load_b32 s6, s[4:5], 0x70 +; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x4c +; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x70 +; GFX11_W32-NEXT: s_load_b32 s6, s[4:5], 0x94 ; GFX11_W32-NEXT: s_load_b32 s7, s[4:5], 0x28 ; GFX11_W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W32-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s6 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX11_W32-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11_W32-NEXT: s_cmp_lg_u32 s6, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, s7, v0, v1 ; GFX11_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W32-NEXT: global_store_b32 v1, v0, s[0:1] @@ -385,16 +355,16 @@ define amdgpu_kernel void @test_div_fmas_f32(ptr addrspace(1) %out, [8 x i32], f ; GFX11_W64-LABEL: test_div_fmas_f32: ; GFX11_W64: ; %bb.0: ; GFX11_W64-NEXT: s_clause 0x4 -; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x94 -; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x4c -; GFX11_W64-NEXT: s_load_b32 s6, s[4:5], 0x70 +; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x4c +; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x70 +; GFX11_W64-NEXT: s_load_b32 s6, s[4:5], 0x94 ; GFX11_W64-NEXT: s_load_b32 s7, s[4:5], 0x28 ; GFX11_W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 -; GFX11_W64-NEXT: v_mov_b32_e32 v1, s6 +; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX11_W64-NEXT: v_mov_b32_e32 v1, s3 +; GFX11_W64-NEXT: s_cmp_lg_u32 s6, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f32 v0, s7, v0, v1 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W64-NEXT: global_store_b32 v1, v0, s[0:1] @@ -414,12 +384,11 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s3 -; GFX7-NEXT: s_and_b32 s2, 1, s6 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX7-NEXT: s_cmp_lg_u32 s6, 0 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX7-NEXT: v_div_fmas_f32 v0, 1.0, v0, v1 ; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s3, 0xf000 -; GFX7-NEXT: s_nop 1 -; GFX7-NEXT: v_div_fmas_f32 v0, 1.0, v0, v1 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; @@ -431,11 +400,10 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 -; GFX8-NEXT: s_and_b32 s0, 1, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX8-NEXT: s_nop 2 +; GFX8-NEXT: s_cmp_lg_u32 s2, 0 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f32 v2, 1.0, v0, v1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -445,15 +413,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, ; GFX10_W32-LABEL: test_div_fmas_f32_inline_imm_0: ; GFX10_W32: ; %bb.0: ; GFX10_W32-NEXT: s_clause 0x3 -; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x94 -; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x70 +; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x70 +; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x94 ; GFX10_W32-NEXT: s_load_dword s6, s[4:5], 0x4c ; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, 1.0, s6, v0 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10_W32-NEXT: s_endpgm @@ -461,15 +429,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, ; GFX10_W64-LABEL: test_div_fmas_f32_inline_imm_0: ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_clause 0x3 -; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x94 -; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x70 +; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x70 +; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x94 ; GFX10_W64-NEXT: s_load_dword s6, s[4:5], 0x4c ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, 1.0, s6, v0 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10_W64-NEXT: s_endpgm @@ -477,15 +445,14 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, ; GFX11_W32-LABEL: test_div_fmas_f32_inline_imm_0: ; GFX11_W32: ; %bb.0: ; GFX11_W32-NEXT: s_clause 0x3 -; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x94 -; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x70 +; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x70 +; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x94 ; GFX11_W32-NEXT: s_load_b32 s6, s[4:5], 0x4c ; GFX11_W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; GFX11_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX11_W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2 +; GFX11_W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, 1.0, s6, v0 ; GFX11_W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11_W32-NEXT: s_endpgm @@ -493,15 +460,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(ptr addrspace(1) %out, ; GFX11_W64-LABEL: test_div_fmas_f32_inline_imm_0: ; GFX11_W64: ; %bb.0: ; GFX11_W64-NEXT: s_clause 0x3 -; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x94 -; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x70 +; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x70 +; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x94 ; GFX11_W64-NEXT: s_load_b32 s6, s[4:5], 0x4c ; GFX11_W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX11_W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f32 v0, 1.0, s6, v0 ; GFX11_W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11_W64-NEXT: s_endpgm @@ -520,12 +487,11 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s3 -; GFX7-NEXT: s_and_b32 s2, 1, s6 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX7-NEXT: s_cmp_lg_u32 s6, 0 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX7-NEXT: v_div_fmas_f32 v0, v0, 1.0, v1 ; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s3, 0xf000 -; GFX7-NEXT: s_nop 1 -; GFX7-NEXT: v_div_fmas_f32 v0, v0, 1.0, v1 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; @@ -537,11 +503,10 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 -; GFX8-NEXT: s_and_b32 s0, 1, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX8-NEXT: s_nop 2 +; GFX8-NEXT: s_cmp_lg_u32 s2, 0 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f32 v2, v0, 1.0, v1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -551,15 +516,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, ; GFX10_W32-LABEL: test_div_fmas_f32_inline_imm_1: ; GFX10_W32: ; %bb.0: ; GFX10_W32-NEXT: s_clause 0x3 -; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x34 -; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x10 +; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x10 +; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x34 ; GFX10_W32-NEXT: s_load_dword s6, s[4:5], 0x8 ; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s6, 1.0, v0 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10_W32-NEXT: s_endpgm @@ -567,15 +532,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, ; GFX10_W64-LABEL: test_div_fmas_f32_inline_imm_1: ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_clause 0x3 -; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x34 -; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x10 +; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x10 +; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x34 ; GFX10_W64-NEXT: s_load_dword s6, s[4:5], 0x8 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s6, 1.0, v0 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10_W64-NEXT: s_endpgm @@ -583,15 +548,14 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, ; GFX11_W32-LABEL: test_div_fmas_f32_inline_imm_1: ; GFX11_W32: ; %bb.0: ; GFX11_W32-NEXT: s_clause 0x3 -; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x34 -; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x10 +; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x10 +; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x34 ; GFX11_W32-NEXT: s_load_b32 s6, s[4:5], 0x8 ; GFX11_W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; GFX11_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX11_W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2 +; GFX11_W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, s6, 1.0, v0 ; GFX11_W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11_W32-NEXT: s_endpgm @@ -599,15 +563,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(ptr addrspace(1) %out, ; GFX11_W64-LABEL: test_div_fmas_f32_inline_imm_1: ; GFX11_W64: ; %bb.0: ; GFX11_W64-NEXT: s_clause 0x3 -; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x34 -; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x10 +; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x10 +; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x34 ; GFX11_W64-NEXT: s_load_b32 s6, s[4:5], 0x8 ; GFX11_W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX11_W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f32 v0, s6, 1.0, v0 ; GFX11_W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11_W64-NEXT: s_endpgm @@ -626,12 +590,11 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s3 -; GFX7-NEXT: s_and_b32 s2, 1, s6 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX7-NEXT: s_cmp_lg_u32 s6, 0 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, 1.0 ; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s3, 0xf000 -; GFX7-NEXT: s_nop 1 -; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, 1.0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; @@ -643,11 +606,10 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 -; GFX8-NEXT: s_and_b32 s0, 1, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX8-NEXT: s_nop 2 +; GFX8-NEXT: s_cmp_lg_u32 s2, 0 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f32 v2, v0, v1, 1.0 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -657,15 +619,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, ; GFX10_W32-LABEL: test_div_fmas_f32_inline_imm_2: ; GFX10_W32: ; %bb.0: ; GFX10_W32-NEXT: s_clause 0x3 -; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x94 -; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x4c +; GFX10_W32-NEXT: s_load_dword s2, s[4:5], 0x4c +; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x94 ; GFX10_W32-NEXT: s_load_dword s6, s[4:5], 0x28 ; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s6, v0, 1.0 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10_W32-NEXT: s_endpgm @@ -673,15 +635,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, ; GFX10_W64-LABEL: test_div_fmas_f32_inline_imm_2: ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_clause 0x3 -; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x94 -; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x4c +; GFX10_W64-NEXT: s_load_dword s2, s[4:5], 0x4c +; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x94 ; GFX10_W64-NEXT: s_load_dword s6, s[4:5], 0x28 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX10_W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s6, v0, 1.0 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10_W64-NEXT: s_endpgm @@ -689,15 +651,14 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, ; GFX11_W32-LABEL: test_div_fmas_f32_inline_imm_2: ; GFX11_W32: ; %bb.0: ; GFX11_W32-NEXT: s_clause 0x3 -; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x94 -; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x4c +; GFX11_W32-NEXT: s_load_b32 s2, s[4:5], 0x4c +; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x94 ; GFX11_W32-NEXT: s_load_b32 s6, s[4:5], 0x28 ; GFX11_W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; GFX11_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W32-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 +; GFX11_W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2 +; GFX11_W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, s6, v0, 1.0 ; GFX11_W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11_W32-NEXT: s_endpgm @@ -705,15 +666,15 @@ define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(ptr addrspace(1) %out, ; GFX11_W64-LABEL: test_div_fmas_f32_inline_imm_2: ; GFX11_W64: ; %bb.0: ; GFX11_W64-NEXT: s_clause 0x3 -; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x94 -; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x4c +; GFX11_W64-NEXT: s_load_b32 s2, s[4:5], 0x4c +; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x94 ; GFX11_W64-NEXT: s_load_b32 s6, s[4:5], 0x28 ; GFX11_W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2 +; GFX11_W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f32 v0, s6, v0, 1.0 ; GFX11_W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11_W64-NEXT: s_endpgm @@ -731,15 +692,14 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d ; GFX7-NEXT: v_mov_b32_e32 v0, s10 ; GFX7-NEXT: v_mov_b32_e32 v2, s12 ; GFX7-NEXT: v_mov_b32_e32 v4, s14 -; GFX7-NEXT: s_and_b32 s0, 1, s0 +; GFX7-NEXT: s_cmp_lg_u32 s0, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, s11 ; GFX7-NEXT: v_mov_b32_e32 v3, s13 ; GFX7-NEXT: v_mov_b32_e32 v5, s15 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX7-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5] ; GFX7-NEXT: s_mov_b32 s10, -1 ; GFX7-NEXT: s_mov_b32 s11, 0xf000 -; GFX7-NEXT: s_nop 1 -; GFX7-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5] ; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GFX7-NEXT: s_endpgm ; @@ -751,12 +711,11 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d ; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mov_b32_e32 v2, s12 ; GFX8-NEXT: v_mov_b32_e32 v4, s14 -; GFX8-NEXT: s_and_b32 s0, 1, s0 +; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, s11 ; GFX8-NEXT: v_mov_b32_e32 v3, s13 ; GFX8-NEXT: v_mov_b32_e32 v5, s15 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_nop 3 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5] ; GFX8-NEXT: v_mov_b32_e32 v2, s8 ; GFX8-NEXT: v_mov_b32_e32 v3, s9 @@ -766,15 +725,15 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d ; GFX10_W32-LABEL: test_div_fmas_f64: ; GFX10_W32: ; %bb.0: ; GFX10_W32-NEXT: s_clause 0x1 -; GFX10_W32-NEXT: s_load_dword s0, s[4:5], 0x20 ; GFX10_W32-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 +; GFX10_W32-NEXT: s_load_dword s0, s[4:5], 0x20 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W32-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s12 ; GFX10_W32-NEXT: v_mov_b32_e32 v2, s14 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s13 ; GFX10_W32-NEXT: v_mov_b32_e32 v3, s15 +; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f64 v[0:1], s[10:11], v[0:1], v[2:3] ; GFX10_W32-NEXT: v_mov_b32_e32 v2, 0 ; GFX10_W32-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] @@ -783,15 +742,15 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d ; GFX10_W64-LABEL: test_div_fmas_f64: ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_clause 0x1 -; GFX10_W64-NEXT: s_load_dword s0, s[4:5], 0x20 ; GFX10_W64-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 +; GFX10_W64-NEXT: s_load_dword s0, s[4:5], 0x20 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W64-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s12 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s14 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s13 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s15 +; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[10:11], v[0:1], v[2:3] ; GFX10_W64-NEXT: v_mov_b32_e32 v2, 0 ; GFX10_W64-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] @@ -800,33 +759,33 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d ; GFX11_W32-LABEL: test_div_fmas_f64: ; GFX11_W32: ; %bb.0: ; GFX11_W32-NEXT: s_clause 0x1 -; GFX11_W32-NEXT: s_load_b32 s8, s[4:5], 0x20 -; GFX11_W32-NEXT: s_load_b256 s[0:7], s[4:5], 0x0 +; GFX11_W32-NEXT: s_load_b256 s[8:15], s[4:5], 0x0 +; GFX11_W32-NEXT: s_load_b32 s0, s[4:5], 0x20 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W32-NEXT: s_and_b32 s8, 1, s8 -; GFX11_W32-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8 -; GFX11_W32-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 -; GFX11_W32-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3] +; GFX11_W32-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13 +; GFX11_W32-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15 +; GFX11_W32-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 +; GFX11_W32-NEXT: v_div_fmas_f64 v[0:1], s[10:11], v[0:1], v[2:3] ; GFX11_W32-NEXT: v_mov_b32_e32 v2, 0 -; GFX11_W32-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11_W32-NEXT: global_store_b64 v2, v[0:1], s[8:9] ; GFX11_W32-NEXT: s_endpgm ; ; GFX11_W64-LABEL: test_div_fmas_f64: ; GFX11_W64: ; %bb.0: ; GFX11_W64-NEXT: s_clause 0x1 -; GFX11_W64-NEXT: s_load_b32 s8, s[4:5], 0x20 -; GFX11_W64-NEXT: s_load_b256 s[0:7], s[4:5], 0x0 +; GFX11_W64-NEXT: s_load_b256 s[8:15], s[4:5], 0x0 +; GFX11_W64-NEXT: s_load_b32 s0, s[4:5], 0x20 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W64-NEXT: s_and_b32 s8, 1, s8 -; GFX11_W64-NEXT: v_mov_b32_e32 v0, s4 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8 -; GFX11_W64-NEXT: v_mov_b32_e32 v2, s6 -; GFX11_W64-NEXT: v_mov_b32_e32 v1, s5 -; GFX11_W64-NEXT: v_mov_b32_e32 v3, s7 -; GFX11_W64-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3] +; GFX11_W64-NEXT: v_mov_b32_e32 v0, s12 +; GFX11_W64-NEXT: v_mov_b32_e32 v2, s14 +; GFX11_W64-NEXT: v_mov_b32_e32 v1, s13 +; GFX11_W64-NEXT: v_mov_b32_e32 v3, s15 +; GFX11_W64-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 +; GFX11_W64-NEXT: v_div_fmas_f64 v[0:1], s[10:11], v[0:1], v[2:3] ; GFX11_W64-NEXT: v_mov_b32_e32 v2, 0 -; GFX11_W64-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11_W64-NEXT: global_store_b64 v2, v[0:1], s[8:9] ; GFX11_W64-NEXT: s_endpgm %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) store double %result, ptr addrspace(1) %out, align 8 @@ -842,13 +801,10 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_cmp_eq_u32 s3, 0 -; GFX7-NEXT: s_cselect_b32 s3, 1, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 -; GFX7-NEXT: s_and_b32 s0, 1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v2, s2 -; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX7-NEXT: s_nop 3 +; GFX7-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2 ; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX7-NEXT: s_endpgm @@ -858,15 +814,12 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_cmp_eq_u32 s3, 0 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 -; GFX8-NEXT: s_and_b32 s0, 1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX8-NEXT: s_nop 2 +; GFX8-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX8-NEXT: v_div_fmas_f32 v2, v0, v1, v2 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -879,12 +832,10 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, ; GFX10_W32-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8 ; GFX10_W32-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1 -; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2 -; GFX10_W32-NEXT: s_and_b32 s3, 1, s3 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 +; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 +; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[6:7] @@ -896,12 +847,10 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, ; GFX10_W64-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8 ; GFX10_W64-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1 -; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2 -; GFX10_W64-NEXT: s_and_b32 s3, 1, s3 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 +; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 +; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[6:7] @@ -913,11 +862,9 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, ; GFX11_W32-NEXT: s_load_b128 s[0:3], s[4:5], 0x8 ; GFX11_W32-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX11_W32-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s2 -; GFX11_W32-NEXT: s_cselect_b32 s3, 1, 0 -; GFX11_W32-NEXT: s_and_b32 s3, 1, s3 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 +; GFX11_W32-NEXT: s_cmp_eq_u32 s3, 0 +; GFX11_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX11_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W32-NEXT: global_store_b32 v1, v0, s[4:5] @@ -929,12 +876,10 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(ptr addrspace(1) %out, ; GFX11_W64-NEXT: s_load_b128 s[0:3], s[4:5], 0x8 ; GFX11_W64-NEXT: s_load_b64 s[4:5], s[4:5], 0x0 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX11_W64-NEXT: v_mov_b32_e32 v0, s1 -; GFX11_W64-NEXT: s_cselect_b32 s3, 1, 0 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, s2 -; GFX11_W64-NEXT: s_and_b32 s3, 1, s3 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 +; GFX11_W64-NEXT: s_cmp_eq_u32 s3, 0 +; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0 ; GFX11_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11_W64-NEXT: global_store_b32 v1, v0, s[4:5] @@ -1055,7 +1000,7 @@ define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace( ; GFX7-NEXT: s_load_dword s3, s[4:5], 0x13 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x1c ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX7-NEXT: s_mov_b64 vcc, -1 +; GFX7-NEXT: s_mov_b64 vcc, exec ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v1, s3 @@ -1071,7 +1016,7 @@ define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace( ; GFX8-NEXT: s_load_dword s0, s[4:5], 0x28 ; GFX8-NEXT: s_load_dword s1, s[4:5], 0x4c ; GFX8-NEXT: s_load_dword s2, s[4:5], 0x70 -; GFX8-NEXT: s_mov_b64 vcc, -1 +; GFX8-NEXT: s_mov_b64 vcc, exec ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -1091,7 +1036,7 @@ define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace( ; GFX10_W32-NEXT: s_load_dword s3, s[4:5], 0x70 ; GFX10_W32-NEXT: s_load_dword s6, s[4:5], 0x28 ; GFX10_W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX10_W32-NEXT: s_mov_b32 vcc_lo, -1 +; GFX10_W32-NEXT: s_mov_b32 vcc_lo, exec_lo ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s3 @@ -1107,7 +1052,7 @@ define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace( ; GFX10_W64-NEXT: s_load_dword s3, s[4:5], 0x70 ; GFX10_W64-NEXT: s_load_dword s6, s[4:5], 0x28 ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GFX10_W64-NEXT: s_mov_b64 vcc, -1 +; GFX10_W64-NEXT: s_mov_b64 vcc, exec ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3 @@ -1123,7 +1068,7 @@ define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace( ; GFX11_W32-NEXT: s_load_b32 s3, s[4:5], 0x70 ; GFX11_W32-NEXT: s_load_b32 s6, s[4:5], 0x28 ; GFX11_W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; GFX11_W32-NEXT: s_mov_b32 vcc_lo, -1 +; GFX11_W32-NEXT: s_mov_b32 vcc_lo, exec_lo ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX11_W32-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, s6, v0, v1 @@ -1138,7 +1083,7 @@ define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(ptr addrspace( ; GFX11_W64-NEXT: s_load_b32 s3, s[4:5], 0x70 ; GFX11_W64-NEXT: s_load_b32 s6, s[4:5], 0x28 ; GFX11_W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; GFX11_W64-NEXT: s_mov_b64 vcc, -1 +; GFX11_W64-NEXT: s_mov_b64 vcc, exec ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, s3 @@ -1169,10 +1114,8 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1 ; GFX7-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64 offset:8 glc ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_cmp_lg_u32 s4, 0 -; GFX7-NEXT: s_cselect_b32 s0, 1, 0 -; GFX7-NEXT: s_and_b32 s0, 1, s0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 +; GFX7-NEXT: s_cselect_b64 s[0:1], exec, 0 ; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_and_b64 vcc, vcc, s[0:1] ; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3] @@ -1203,10 +1146,8 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1 ; GFX8-NEXT: s_add_u32 s0, s0, 8 ; GFX8-NEXT: s_addc_u32 s1, s1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 -; GFX8-NEXT: s_and_b32 s2, 1, s2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 +; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0 ; GFX8-NEXT: s_and_b64 vcc, vcc, s[2:3] ; GFX8-NEXT: s_nop 1 ; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3 @@ -1230,9 +1171,7 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1 ; GFX10_W32-NEXT: s_waitcnt vmcnt(0) ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10_W32-NEXT: s_cselect_b32 s2, 1, 0 -; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2 +; GFX10_W32-NEXT: s_cselect_b32 s2, exec_lo, 0 ; GFX10_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s2 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, v2, v3, v4 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[0:1] offset:8 @@ -1253,9 +1192,7 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1 ; GFX10_W64-NEXT: s_waitcnt vmcnt(0) ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: s_cmp_lg_u32 s4, 0 -; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0 -; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 +; GFX10_W64-NEXT: s_cselect_b64 s[2:3], exec, 0 ; GFX10_W64-NEXT: s_and_b64 vcc, vcc, s[2:3] ; GFX10_W64-NEXT: v_div_fmas_f32 v0, v2, v3, v4 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[0:1] offset:8 @@ -1276,9 +1213,7 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1 ; GFX11_W32-NEXT: global_load_b32 v1, v1, s[2:3] offset:8 glc dlc ; GFX11_W32-NEXT: s_waitcnt vmcnt(0) ; GFX11_W32-NEXT: s_cmp_lg_u32 s4, 0 -; GFX11_W32-NEXT: s_cselect_b32 s2, 1, 0 -; GFX11_W32-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2 +; GFX11_W32-NEXT: s_cselect_b32 s2, exec_lo, 0 ; GFX11_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s2 ; GFX11_W32-NEXT: v_div_fmas_f32 v0, v2, v3, v1 ; GFX11_W32-NEXT: v_mov_b32_e32 v1, 0 @@ -1300,9 +1235,7 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1 ; GFX11_W64-NEXT: global_load_b32 v1, v1, s[2:3] offset:8 glc dlc ; GFX11_W64-NEXT: s_waitcnt vmcnt(0) ; GFX11_W64-NEXT: s_cmp_lg_u32 s4, 0 -; GFX11_W64-NEXT: s_cselect_b32 s2, 1, 0 -; GFX11_W64-NEXT: s_and_b32 s2, 1, s2 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 +; GFX11_W64-NEXT: s_cselect_b64 s[2:3], exec, 0 ; GFX11_W64-NEXT: s_and_b64 vcc, vcc, s[2:3] ; GFX11_W64-NEXT: v_div_fmas_f32 v0, v2, v3, v1 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, 0 @@ -1347,9 +1280,7 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [ ; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_cmp_lg_u32 s0, 0 -; GFX7-NEXT: s_cselect_b32 s0, 1, 0 -; GFX7-NEXT: s_and_b32 s0, 1, s0 -; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 +; GFX7-NEXT: s_cselect_b64 s[0:1], exec, 0 ; GFX7-NEXT: s_andn2_b64 s[8:9], 0, exec ; GFX7-NEXT: s_and_b64 s[0:1], exec, s[0:1] ; GFX7-NEXT: s_or_b64 vcc, s[8:9], s[0:1] @@ -1383,9 +1314,7 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [ ; GFX8-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_cmp_lg_u32 s0, 0 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 -; GFX8-NEXT: s_and_b32 s0, 1, s0 -; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 +; GFX8-NEXT: s_cselect_b64 s[0:1], exec, 0 ; GFX8-NEXT: s_andn2_b64 s[6:7], 0, exec ; GFX8-NEXT: s_and_b64 s[0:1], exec, s[0:1] ; GFX8-NEXT: s_or_b64 vcc, s[6:7], s[0:1] @@ -1418,10 +1347,8 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [ ; GFX10_W32-NEXT: s_load_dword s0, s[2:3], 0x0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W32-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10_W32-NEXT: s_cselect_b32 s0, exec_lo, 0 ; GFX10_W32-NEXT: s_andn2_b32 s2, 0, exec_lo -; GFX10_W32-NEXT: s_and_b32 s0, 1, s0 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GFX10_W32-NEXT: s_and_b32 s0, exec_lo, s0 ; GFX10_W32-NEXT: s_or_b32 vcc_lo, s2, s0 ; GFX10_W32-NEXT: .LBB13_2: ; %exit @@ -1450,10 +1377,8 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [ ; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W64-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10_W64-NEXT: s_cselect_b64 s[0:1], exec, 0 ; GFX10_W64-NEXT: s_andn2_b64 s[6:7], 0, exec -; GFX10_W64-NEXT: s_and_b32 s0, 1, s0 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX10_W64-NEXT: s_and_b64 s[0:1], exec, s[0:1] ; GFX10_W64-NEXT: s_or_b64 vcc, s[6:7], s[0:1] ; GFX10_W64-NEXT: .LBB13_2: ; %exit @@ -1483,10 +1408,8 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [ ; GFX11_W32-NEXT: s_load_b32 s0, s[2:3], 0x0 ; GFX11_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX11_W32-NEXT: s_cmp_lg_u32 s0, 0 -; GFX11_W32-NEXT: s_cselect_b32 s0, 1, 0 +; GFX11_W32-NEXT: s_cselect_b32 s0, exec_lo, 0 ; GFX11_W32-NEXT: s_and_not1_b32 s2, 0, exec_lo -; GFX11_W32-NEXT: s_and_b32 s0, 1, s0 -; GFX11_W32-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GFX11_W32-NEXT: s_and_b32 s0, exec_lo, s0 ; GFX11_W32-NEXT: s_or_b32 vcc_lo, s2, s0 ; GFX11_W32-NEXT: .LBB13_2: ; %exit @@ -1516,10 +1439,8 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [ ; GFX11_W64-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11_W64-NEXT: s_cmp_lg_u32 s0, 0 -; GFX11_W64-NEXT: s_cselect_b32 s0, 1, 0 +; GFX11_W64-NEXT: s_cselect_b64 s[0:1], exec, 0 ; GFX11_W64-NEXT: s_and_not1_b64 s[6:7], 0, exec -; GFX11_W64-NEXT: s_and_b32 s0, 1, s0 -; GFX11_W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX11_W64-NEXT: s_and_b64 s[0:1], exec, s[0:1] ; GFX11_W64-NEXT: s_or_b64 vcc, s[6:7], s[0:1] ; GFX11_W64-NEXT: .LBB13_2: ; %exit diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll index 0535394d1025..f44f719846e9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s define amdgpu_kernel void @test_div_scale_f32_1(ptr addrspace(1) %out, ptr addrspace(1) %in) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir index 3fd01395c7f2..97410906e081 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: div_fmas_sss_scc @@ -18,12 +17,12 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) - ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s1) + ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32) + ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[AMDGPU_COPY_VCC_SCC]](s1) + ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[INT]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $sgpr2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir index ea9ec47e594a..ed164d67c027 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: div_scale_ss diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll index fb29a57bc0b6..565cceec103d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll @@ -1,15 +1,46 @@ -; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "load" --filter-out "store" --filter-out "wait" --version 6 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c) -; GCN-LABEL: {{^}}div_fixup_f16 -; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] -; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] -; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16( +; VI-SDAG-LABEL: div_fixup_f16: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s11, 0xf000 +; VI-SDAG: s_mov_b32 s10, -1 +; VI-SDAG: s_mov_b32 s14, s10 +; VI-SDAG: s_mov_b32 s15, s11 +; VI-SDAG: s_mov_b32 s12, s2 +; VI-SDAG: s_mov_b32 s13, s3 +; VI-SDAG: s_mov_b32 s16, s4 +; VI-SDAG: s_mov_b32 s17, s5 +; VI-SDAG: s_mov_b32 s18, s10 +; VI-SDAG: s_mov_b32 s19, s11 +; VI-SDAG: s_mov_b32 s4, s6 +; VI-SDAG: s_mov_b32 s5, s7 +; VI-SDAG: s_mov_b32 s6, s10 +; VI-SDAG: s_mov_b32 s7, s11 +; VI-SDAG: s_mov_b32 s8, s0 +; VI-SDAG: s_mov_b32 s9, s1 +; VI-SDAG: v_div_fixup_f16 v0, v0, v1, v2 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s10, -1 +; VI-GISEL: s_mov_b32 s11, 0xf000 +; VI-GISEL: s_mov_b64 s[8:9], s[2:3] +; VI-GISEL: s_mov_b64 s[8:9], s[4:5] +; VI-GISEL: s_mov_b64 s[8:9], s[6:7] +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_readfirstlane_b32 s3, v1 +; VI-GISEL: v_mov_b32_e32 v0, s3 +; VI-GISEL: v_readfirstlane_b32 s4, v2 +; VI-GISEL: v_mov_b32_e32 v1, s4 +; VI-GISEL: v_div_fixup_f16 v0, s2, v0, v1 +; VI-GISEL: s_mov_b64 s[2:3], s[10:11] +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -23,14 +54,37 @@ entry: ret void } -; GCN-LABEL: {{^}}div_fixup_f16_imm_a -; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] -; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] -; VI: s_movk_i32 s[[A_F16:[0-9]+]], 0x4200{{$}} -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], s[[A_F16]], v[[B_F16]], v[[C_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_a( +; VI-SDAG-LABEL: div_fixup_f16_imm_a: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s7, 0xf000 +; VI-SDAG: s_mov_b32 s6, -1 +; VI-SDAG: s_mov_b32 s14, s6 +; VI-SDAG: s_mov_b32 s12, s2 +; VI-SDAG: s_mov_b32 s13, s3 +; VI-SDAG: s_mov_b32 s15, s7 +; VI-SDAG: s_mov_b32 s10, s6 +; VI-SDAG: s_mov_b32 s11, s7 +; VI-SDAG: s_mov_b32 s4, s0 +; VI-SDAG: s_movk_i32 s0, 0x4200 +; VI-SDAG: s_mov_b32 s5, s1 +; VI-SDAG: v_div_fixup_f16 v0, s0, v0, v1 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16_imm_a: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s6, -1 +; VI-GISEL: s_mov_b32 s7, 0xf000 +; VI-GISEL: s_mov_b64 s[10:11], s[6:7] +; VI-GISEL: s_mov_b64 s[4:5], s[2:3] +; VI-GISEL: v_mov_b32_e32 v2, 0x4200 +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_readfirstlane_b32 s3, v1 +; VI-GISEL: v_mov_b32_e32 v0, s3 +; VI-GISEL: v_div_fixup_f16 v0, v2, s2, v0 +; VI-GISEL: s_mov_b64 s[2:3], s[6:7] +; VI-GISEL: s_nop 1 +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %b, ptr addrspace(1) %c) { @@ -42,14 +96,37 @@ entry: ret void } -; GCN-LABEL: {{^}}div_fixup_f16_imm_b -; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] -; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] -; VI: s_movk_i32 s[[B_F16:[0-9]+]], 0x4200{{$}} -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], s[[B_F16]], v[[C_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_b( +; VI-SDAG-LABEL: div_fixup_f16_imm_b: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s7, 0xf000 +; VI-SDAG: s_mov_b32 s6, -1 +; VI-SDAG: s_mov_b32 s14, s6 +; VI-SDAG: s_mov_b32 s12, s2 +; VI-SDAG: s_mov_b32 s13, s3 +; VI-SDAG: s_mov_b32 s15, s7 +; VI-SDAG: s_mov_b32 s10, s6 +; VI-SDAG: s_mov_b32 s11, s7 +; VI-SDAG: s_mov_b32 s4, s0 +; VI-SDAG: s_movk_i32 s0, 0x4200 +; VI-SDAG: s_mov_b32 s5, s1 +; VI-SDAG: v_div_fixup_f16 v0, v0, s0, v1 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16_imm_b: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s6, -1 +; VI-GISEL: s_mov_b32 s7, 0xf000 +; VI-GISEL: s_mov_b64 s[10:11], s[6:7] +; VI-GISEL: s_mov_b64 s[4:5], s[2:3] +; VI-GISEL: v_mov_b32_e32 v2, 0x4200 +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_readfirstlane_b32 s3, v1 +; VI-GISEL: v_mov_b32_e32 v0, s3 +; VI-GISEL: v_div_fixup_f16 v0, s2, v2, v0 +; VI-GISEL: s_mov_b64 s[2:3], s[6:7] +; VI-GISEL: s_nop 1 +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %c) { @@ -61,14 +138,37 @@ entry: ret void } -; GCN-LABEL: {{^}}div_fixup_f16_imm_c -; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] -; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] -; VI: s_movk_i32 s[[C_F16:[0-9]+]], 0x4200{{$}} -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], s[[C_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_c( +; VI-SDAG-LABEL: div_fixup_f16_imm_c: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s7, 0xf000 +; VI-SDAG: s_mov_b32 s6, -1 +; VI-SDAG: s_mov_b32 s14, s6 +; VI-SDAG: s_mov_b32 s12, s2 +; VI-SDAG: s_mov_b32 s13, s3 +; VI-SDAG: s_mov_b32 s15, s7 +; VI-SDAG: s_mov_b32 s10, s6 +; VI-SDAG: s_mov_b32 s11, s7 +; VI-SDAG: s_mov_b32 s4, s0 +; VI-SDAG: s_movk_i32 s0, 0x4200 +; VI-SDAG: s_mov_b32 s5, s1 +; VI-SDAG: v_div_fixup_f16 v0, v0, v1, s0 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16_imm_c: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s6, -1 +; VI-GISEL: s_mov_b32 s7, 0xf000 +; VI-GISEL: s_mov_b64 s[10:11], s[6:7] +; VI-GISEL: s_mov_b64 s[4:5], s[2:3] +; VI-GISEL: v_mov_b32_e32 v2, 0x4200 +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_readfirstlane_b32 s3, v1 +; VI-GISEL: v_mov_b32_e32 v0, s3 +; VI-GISEL: v_div_fixup_f16 v0, s2, v0, v2 +; VI-GISEL: s_mov_b64 s[2:3], s[6:7] +; VI-GISEL: s_nop 1 +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b) { @@ -80,13 +180,32 @@ entry: ret void } -; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_b -; VI-DAG: s_movk_i32 [[AB_F16:s[0-9]+]], 0x4200{{$}} -; GCN-DAG: buffer_load_ushort v[[C_F16:[0-9]+]] -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AB_F16]], [[AB_F16]], v[[C_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_a_imm_b( +; VI-SDAG-LABEL: div_fixup_f16_imm_a_imm_b: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s7, 0xf000 +; VI-SDAG: s_mov_b32 s6, -1 +; VI-SDAG: s_mov_b32 s10, s6 +; VI-SDAG: s_mov_b32 s11, s7 +; VI-SDAG: s_mov_b32 s8, s2 +; VI-SDAG: s_mov_b32 s9, s3 +; VI-SDAG: s_mov_b32 s4, s0 +; VI-SDAG: s_movk_i32 s0, 0x4200 +; VI-SDAG: s_mov_b32 s5, s1 +; VI-SDAG: v_div_fixup_f16 v0, s0, s0, v0 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16_imm_a_imm_b: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s6, -1 +; VI-GISEL: s_mov_b32 s7, 0xf000 +; VI-GISEL: v_mov_b32_e32 v1, 0x4200 +; VI-GISEL: s_mov_b64 s[4:5], s[2:3] +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_div_fixup_f16 v0, v1, v1, s2 +; VI-GISEL: s_mov_b64 s[2:3], s[6:7] +; VI-GISEL: s_nop 2 +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %c) { entry: @@ -96,13 +215,32 @@ entry: ret void } -; GCN-LABEL: {{^}}div_fixup_f16_imm_b_imm_c -; VI-DAG: s_movk_i32 [[BC_F16:s[0-9]+]], 0x4200{{$}} -; GCN-DAG: buffer_load_ushort v[[A_F16:[0-9]+]] -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], [[BC_F16]], [[BC_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_b_imm_c( +; VI-SDAG-LABEL: div_fixup_f16_imm_b_imm_c: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s7, 0xf000 +; VI-SDAG: s_mov_b32 s6, -1 +; VI-SDAG: s_mov_b32 s10, s6 +; VI-SDAG: s_mov_b32 s11, s7 +; VI-SDAG: s_mov_b32 s8, s2 +; VI-SDAG: s_mov_b32 s9, s3 +; VI-SDAG: s_mov_b32 s4, s0 +; VI-SDAG: s_movk_i32 s0, 0x4200 +; VI-SDAG: s_mov_b32 s5, s1 +; VI-SDAG: v_div_fixup_f16 v0, v0, s0, s0 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16_imm_b_imm_c: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s6, -1 +; VI-GISEL: s_mov_b32 s7, 0xf000 +; VI-GISEL: v_mov_b32_e32 v1, 0x4200 +; VI-GISEL: s_mov_b64 s[4:5], s[2:3] +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_div_fixup_f16 v0, s2, v1, v1 +; VI-GISEL: s_mov_b64 s[2:3], s[6:7] +; VI-GISEL: s_nop 2 +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a) { entry: @@ -112,13 +250,32 @@ entry: ret void } -; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_c -; VI-DAG: s_movk_i32 [[AC_F16:s[0-9]+]], 0x4200{{$}} -; GCN-DAG: buffer_load_ushort v[[B_F16:[0-9]+]] -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AC_F16]], v[[B_F16]], [[AC_F16]] -; GCN: buffer_store_short v[[R_F16]] -; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_a_imm_c( +; VI-SDAG-LABEL: div_fixup_f16_imm_a_imm_c: +; VI-SDAG: ; %bb.0: ; %entry +; VI-SDAG: s_mov_b32 s7, 0xf000 +; VI-SDAG: s_mov_b32 s6, -1 +; VI-SDAG: s_mov_b32 s10, s6 +; VI-SDAG: s_mov_b32 s11, s7 +; VI-SDAG: s_mov_b32 s8, s2 +; VI-SDAG: s_mov_b32 s9, s3 +; VI-SDAG: s_mov_b32 s4, s0 +; VI-SDAG: s_movk_i32 s0, 0x4200 +; VI-SDAG: s_mov_b32 s5, s1 +; VI-SDAG: v_div_fixup_f16 v0, s0, v0, s0 +; VI-SDAG: s_endpgm +; +; VI-GISEL-LABEL: div_fixup_f16_imm_a_imm_c: +; VI-GISEL: ; %bb.0: ; %entry +; VI-GISEL: s_mov_b32 s6, -1 +; VI-GISEL: s_mov_b32 s7, 0xf000 +; VI-GISEL: v_mov_b32_e32 v1, 0x4200 +; VI-GISEL: s_mov_b64 s[4:5], s[2:3] +; VI-GISEL: v_readfirstlane_b32 s2, v0 +; VI-GISEL: v_div_fixup_f16 v0, v1, s2, v1 +; VI-GISEL: s_mov_b64 s[2:3], s[6:7] +; VI-GISEL: s_nop 2 +; VI-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %b) { entry: @@ -127,3 +284,17 @@ entry: store half %r.val, ptr addrspace(1) %r ret void } + +define half @div_fixup_f16_vgpr(half %a, half %b, half %c) { +; VI-SDAG-LABEL: div_fixup_f16_vgpr: +; VI-SDAG: ; %bb.0: +; VI-SDAG: v_div_fixup_f16 v0, v0, v1, v2 +; VI-SDAG: s_setpc_b64 s[30:31] +; +; VI-GISEL-LABEL: div_fixup_f16_vgpr: +; VI-GISEL: ; %bb.0: +; VI-GISEL: v_div_fixup_f16 v0, v0, v1, v2 +; VI-GISEL: s_setpc_b64 s[30:31] + %r = call half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c) + ret half %r +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll index 4a71fce583db..b34db3542363 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll @@ -1,5 +1,6 @@ -; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone @@ -31,3 +32,17 @@ define amdgpu_kernel void @test_div_fixup_f64(ptr addrspace(1) %out, double %a, store double %result, ptr addrspace(1) %out, align 8 ret void } + +; GCN-LABEL: {{^}}test_div_fixup_f32_vgpr: +; GCN: v_div_fixup_f32 +define float @test_div_fixup_f32_vgpr(float %a, float %b, float %c) { + %result = call float @llvm.amdgcn.div.fixup.f32(float %a, float %b, float %c) + ret float %result +} + +; GCN-LABEL: {{^}}test_div_fixup_f64_vgpr: +; GCN: v_div_fixup_f64 +define double @test_div_fixup_f64_vgpr(double %a, double %b, double %c) { + %result = call double @llvm.amdgcn.div.fixup.f64(double %a, double %b, double %c) + ret double %result +}