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[RISCV] Support Zb*/P Shared Instructions (#127160)

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This enables shared instructions between Zb* and Base-P extension.

Documentation:
https://jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-014.pdf
This commit is contained in:
realqhc 2025-02-15 22:26:02 +08:00 committed by GitHub
parent a6093d3034
commit 88284e4efc
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GPG Key ID: B5690EEEBB952194
8 changed files with 133 additions and 13 deletions
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1
clang/test/Driver/print-supported-extensions-riscv.c
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@ -182,6 +182,7 @@
// CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD))
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)

33
llvm/lib/Target/RISCV/RISCVFeatures.td
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@ -1016,6 +1016,39 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
"'Smctr' (Control Transfer Records Machine Level) or "
"'Ssctr' (Control Transfer Records Supervisor Level)">;
// Packed SIMD Extensions
def FeatureStdExtP
: RISCVExperimentalExtension<0, 14,
"'Base P' (Packed SIMD)">;
def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
AssemblerPredicate<(all_of FeatureStdExtP),
"'Base P' (Packed SIMD)">;
def HasStdExtZbaOrP
: Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">,
AssemblerPredicate<(any_of FeatureStdExtZba, FeatureStdExtP),
"'Zba' (Address Generation Instructions) or "
"'Base P' (Packed-SIMD)">;
def HasStdExtZbbOrP
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtP()">,
AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtP),
"'Zbb' (Basic Bit-Manipulation) or "
"'Base P' (Packed-SIMD)">;
def HasStdExtZbkbOrP
: Predicate<"Subtarget->hasStdExtZbkb() || Subtarget->hasStdExtP()">,
AssemblerPredicate<(any_of FeatureStdExtZbkb, FeatureStdExtP),
"'Zbkb' (Bitmanip instructions for Cryptography) or "
"'Base P' (Packed-SIMD)">;
def HasStdExtZbbOrZbkbOrP
: Predicate<"Subtarget->HasStdExtZbbOrZbkb()|| Subtarget->hasStdExtP()">,
AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP),
"'Zbb' (Basic Bit-Manipulation) or "
"'Zbkb' (Bitmanip instructions for Cryptography) or "
"'Base P' (Packed-SIMD)">;
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//

26
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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@ -263,9 +263,10 @@ def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbbOrZbkb]
let Predicates = [HasStdExtZba] in {
let Predicates = [HasStdExtZbaOrP] in
def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
let Predicates = [HasStdExtZba] in {
def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">,
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
@ -337,30 +338,32 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">,
Sched<[WriteXPERM, ReadXPERM, ReadXPERM]>;
} // Predicates = [HasStdExtZbkx]
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in
def CLZ : Unary_r<0b011000000000, 0b001, "clz">,
Sched<[WriteCLZ, ReadCLZ]>;
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
def CTZ : Unary_r<0b011000000001, 0b001, "ctz">,
Sched<[WriteCTZ, ReadCTZ]>;
def CPOP : Unary_r<0b011000000010, 0b001, "cpop">,
Sched<[WriteCPOP, ReadCPOP]>;
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
let Predicates = [HasStdExtZbbOrP, IsRV64], IsSignExtendingOpW = 1 in
def CLZW : UnaryW_r<0b011000000000, 0b001, "clzw">,
Sched<[WriteCLZ32, ReadCLZ32]>;
let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
def CTZW : UnaryW_r<0b011000000001, 0b001, "ctzw">,
Sched<[WriteCTZ32, ReadCTZ32]>;
def CPOPW : UnaryW_r<0b011000000010, 0b001, "cpopw">,
Sched<[WriteCPOP32, ReadCPOP32]>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in {
def SEXT_B : Unary_r<0b011000000100, 0b001, "sext.b">,
Sched<[WriteIALU, ReadIALU]>;
def SEXT_H : Unary_r<0b011000000101, 0b001, "sext.h">,
Sched<[WriteIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbb]
} // Predicates = [HasStdExtZbbOrP]
let Predicates = [HasStdExtZbc] in {
def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", Commutable=1>,
@ -374,7 +377,7 @@ def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", Commutable=1>,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
} // Predicates = [HasStdExtZbcOrZbkc]
let Predicates = [HasStdExtZbb] in {
let Predicates = [HasStdExtZbbOrP] in {
def MIN : ALU_rr<0b0000101, 0b100, "min", Commutable=1>,
Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
def MINU : ALU_rr<0b0000101, 0b101, "minu", Commutable=1>,
@ -385,9 +388,10 @@ def MAXU : ALU_rr<0b0000101, 0b111, "maxu", Commutable=1>,
Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbkb] in {
let Predicates = [HasStdExtZbkbOrP] in
def PACK : ALU_rr<0b0000100, 0b100, "pack">,
Sched<[WritePACK, ReadPACK, ReadPACK]>;
let Predicates = [HasStdExtZbkb] in {
let IsSignExtendingOpW = 1 in
def PACKH : ALU_rr<0b0000100, 0b111, "packh">,
Sched<[WritePACK, ReadPACK, ReadPACK]>;
@ -407,15 +411,15 @@ def ZEXT_H_RV64 : RVBUnaryR<0b0000100, 0b100, OPC_OP_32, "zext.h">,
Sched<[WriteIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in {
let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] in {
def REV8_RV32 : Unary_r<0b011010011000, 0b101, "rev8">,
Sched<[WriteREV8, ReadREV8]>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV32]
} // Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32]
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64] in {
def REV8_RV64 : Unary_r<0b011010111000, 0b101, "rev8">,
Sched<[WriteREV8, ReadREV8]>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
} // Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64]
let Predicates = [HasStdExtZbb] in {
def ORC_B : Unary_r<0b001010000111, 0b101, "orc.b">,

6
llvm/test/MC/RISCV/attribute-arch.s
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@ -473,3 +473,9 @@
.attribute arch, "rv32i_sdtrig1p0"
# CHECK: attribute 5, "rv32i2p1_sdtrig1p0"
.attribute arch, "rv32i_p0p14"
# CHECK: attribute 5, "rv32i2p1_p0p14"
.attribute arch, "rv64i_p0p14"
# CHECK: attribute 5, "rv64i2p1_p0p14"

4
llvm/test/MC/RISCV/rv32i-invalid.s
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@ -191,8 +191,8 @@ fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the followi
fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}}
fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}}
flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions){{$}}
clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}}
sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) or 'Base P' (Packed-SIMD){{$}}
clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) or 'Base P' (Packed-SIMD){{$}}
clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}}
bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}}
pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}}

36
llvm/test/MC/RISCV/rv32p-valid.s Normal file
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@ -0,0 +1,36 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
sh1add a0, a1, a2
# CHECK-ASM-AND-OBJ: clz a0, a1
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
clz a0, a1
# CHECK-ASM-AND-OBJ: sext.b a2, a3
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
sext.b a2, a3
# CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
minu t0, t1, t2
# CHECK-ASM-AND-OBJ: max t3, t4, t5
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
max t3, t4, t5
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
maxu a4, a5, a6
# CHECK-ASM-AND-OBJ: pack s0, s1, s2
# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
pack s0, s1, s2
# CHECK-ASM-AND-OBJ: rev8 s0, s1
# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69]
rev8 s0, s1

39
llvm/test/MC/RISCV/rv64p-valid.s Normal file
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@ -0,0 +1,39 @@
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-p < %s \
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
sh1add a0, a1, a2
# CHECK-ASM-AND-OBJ: clz a0, a1
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
clz a0, a1
# CHECK-ASM-AND-OBJ: clzw s0, s1
# CHECK-ASM: encoding: [0x1b,0x94,0x04,0x60]
clzw s0, s1
# CHECK-ASM-AND-OBJ: sext.b a2, a3
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
sext.b a2, a3
# CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
minu t0, t1, t2
# CHECK-ASM-AND-OBJ: max t3, t4, t5
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
max t3, t4, t5
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
maxu a4, a5, a6
# CHECK-ASM-AND-OBJ: pack s0, s1, s2
# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
pack s0, s1, s2
# CHECK-ASM-AND-OBJ: rev8 s0, s1
# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x6b]
rev8 s0, s1

1
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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@ -1108,6 +1108,7 @@ R"(All available -march extensions for RISC-V
xwchc 2.2
Experimental extensions
p 0.14
zicfilp 1.0 This is a long dummy description
zicfiss 1.0
zalasr 0.1