[HEXAGON] Fix corner cases for hwloops pass (#135439)
Add check to make sure Dist > 0 or Dist < 0 for appropriate cmp cases to hexagon hardware loops pass. The change modifies the HexagonHardwareLoops pass to add runtime checks to make sure that end_value > initial_value for less than comparisons and end_value < initial_value for greater than comparisons. Fix for https://github.com/llvm/llvm-project/issues/133241 @androm3da @iajbar PTAL --------- Co-authored-by: aankit-quic <aankit@quicinc.com> (cherry picked from commit da8ce56c53fe6e34809ba0b310fa90257e230a89)
This commit is contained in:
aankit-ca
Tom Stellard
parent
78f6719ca9
commit
89adc2d4f9
@ -731,6 +731,11 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
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Register IVReg,
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int64_t IVBump,
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Comparison::Kind Cmp) const {
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LLVM_DEBUG(llvm::dbgs() << "Loop: " << *Loop << "\n");
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LLVM_DEBUG(llvm::dbgs() << "Initial Value: " << *Start << "\n");
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LLVM_DEBUG(llvm::dbgs() << "End Value: " << *End << "\n");
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LLVM_DEBUG(llvm::dbgs() << "Inc/Dec Value: " << IVBump << "\n");
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LLVM_DEBUG(llvm::dbgs() << "Comparison: " << Cmp << "\n");
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// Cannot handle comparison EQ, i.e. while (A == B).
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if (Cmp == Comparison::EQ)
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return nullptr;
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@ -846,6 +851,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
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if (IVBump < 0) {
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std::swap(Start, End);
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IVBump = -IVBump;
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std::swap(CmpLess, CmpGreater);
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}
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// Cmp may now have a wrong direction, e.g. LEs may now be GEs.
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// Signedness, and "including equality" are preserved.
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@ -989,7 +995,45 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
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CountSR = 0;
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}
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return new CountValue(CountValue::CV_Register, CountR, CountSR);
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const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
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Register MuxR = CountR;
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unsigned MuxSR = CountSR;
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// For the loop count to be valid unsigned number, CmpLess should imply
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// Dist >= 0. Similarly, CmpGreater should imply Dist < 0. We can skip the
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// check if the initial distance is zero and the comparison is LTu || LTEu.
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if (!(Start->isImm() && StartV == 0 && Comparison::isUnsigned(Cmp) &&
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CmpLess) &&
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(CmpLess || CmpGreater)) {
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// Generate:
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// DistCheck = CMP_GT DistR, 0 --> CmpLess
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// DistCheck = CMP_GT DistR, -1 --> CmpGreater
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Register DistCheckR = MRI->createVirtualRegister(PredRC);
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const MCInstrDesc &DistCheckD = TII->get(Hexagon::C2_cmpgti);
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BuildMI(*PH, InsertPos, DL, DistCheckD, DistCheckR)
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.addReg(DistR, 0, DistSR)
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.addImm((CmpLess) ? 0 : -1);
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// Generate:
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// MUXR = MUX DistCheck, CountR, 1 --> CmpLess
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// MUXR = MUX DistCheck, 1, CountR --> CmpGreater
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MuxR = MRI->createVirtualRegister(IntRC);
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if (CmpLess) {
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const MCInstrDesc &MuxD = TII->get(Hexagon::C2_muxir);
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BuildMI(*PH, InsertPos, DL, MuxD, MuxR)
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.addReg(DistCheckR)
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.addReg(CountR, 0, CountSR)
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.addImm(1);
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} else {
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const MCInstrDesc &MuxD = TII->get(Hexagon::C2_muxri);
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BuildMI(*PH, InsertPos, DL, MuxD, MuxR)
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.addReg(DistCheckR)
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.addImm(1)
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.addReg(CountR, 0, CountSR);
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}
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MuxSR = 0;
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}
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return new CountValue(CountValue::CV_Register, MuxR, MuxSR);
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}
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/// Return true if the operation is invalid within hardware loop.
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277
llvm/test/CodeGen/Hexagon/hwloop-dist-check.mir
Normal file
277
llvm/test/CodeGen/Hexagon/hwloop-dist-check.mir
Normal file
@ -0,0 +1,277 @@
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# RUN: llc --mtriple=hexagon -run-pass=hwloops %s -o - | FileCheck %s
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# CHECK-LABEL: name: f
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# CHECK: [[R1:%[0-9]+]]:predregs = C2_cmpgti [[R0:%[0-9]+]], 0
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# CHECK: [[R3:%[0-9]+]]:intregs = C2_muxir [[R1:%[0-9]+]], [[R2:%[0-9]+]], 1
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# CHECK-LABEL: name: g
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# CHECK: [[R1:%[0-9]+]]:predregs = C2_cmpgti [[R0:%[0-9]+]], 0
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# CHECK: [[R3:%[0-9]+]]:intregs = C2_muxir [[R1:%[0-9]+]], [[R2:%[0-9]+]], 1
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--- |
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@a = dso_local global [255 x ptr] zeroinitializer, align 8
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; Function Attrs: minsize nofree norecurse nosync nounwind optsize memory(write, argmem: none, inaccessiblemem: none)
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define dso_local void @f(i32 noundef %m) local_unnamed_addr #0 {
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entry:
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%cond = tail call i32 @llvm.smax.i32(i32 %m, i32 2)
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%0 = add nsw i32 %cond, -4
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%1 = shl i32 %cond, 3
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%cgep = getelementptr i8, ptr @a, i32 %1
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%cgep36 = bitcast ptr @a to ptr
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%lsr.iv1 = phi ptr [ %cgep4, %do.body ], [ %cgep, %entry ]
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%lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %0, %entry ]
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%sh.0 = phi i32 [ 256, %entry ], [ %shr, %do.body ]
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%shr = lshr i32 %sh.0, 1
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%cgep5 = getelementptr inbounds [255 x ptr], ptr %cgep36, i32 0, i32 %shr
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store ptr %lsr.iv1, ptr %cgep5, align 4, !tbaa !5
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%lsr.iv.next = add nsw i32 %lsr.iv, 4
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%cmp1 = icmp samesign ult i32 %lsr.iv.next, 1073741836
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%cgep4 = getelementptr i8, ptr %lsr.iv1, i32 32
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br i1 %cmp1, label %do.body, label %do.end, !llvm.loop !9
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do.end: ; preds = %do.body
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ret void
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}
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; Function Attrs: minsize nofree norecurse nosync nounwind optsize memory(write, argmem: none, inaccessiblemem: none)
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define dso_local void @g(i32 noundef %m) local_unnamed_addr #0 {
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entry:
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%0 = add i32 %m, -4
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%1 = shl i32 %m, 3
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%cgep = getelementptr i8, ptr @a, i32 %1
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%cgep36 = bitcast ptr @a to ptr
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%lsr.iv1 = phi ptr [ %cgep4, %do.body ], [ %cgep, %entry ]
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%lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %0, %entry ]
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%sh.0 = phi i32 [ 256, %entry ], [ %shr, %do.body ]
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%shr = lshr i32 %sh.0, 1
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%cgep5 = getelementptr inbounds [255 x ptr], ptr %cgep36, i32 0, i32 %shr
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store ptr %lsr.iv1, ptr %cgep5, align 4, !tbaa !5
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%lsr.iv.next = add i32 %lsr.iv, 4
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%cmp = icmp slt i32 %lsr.iv.next, 1073741836
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%cgep4 = getelementptr i8, ptr %lsr.iv1, i32 32
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br i1 %cmp, label %do.body, label %do.end, !llvm.loop !11
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do.end: ; preds = %do.body
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.smax.i32(i32, i32) #1
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!llvm.module.flags = !{!0, !1, !2, !3}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 8, !"PIC Level", i32 2}
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!2 = !{i32 7, !"PIE Level", i32 2}
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!3 = !{i32 7, !"frame-pointer", i32 2}
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!5 = !{!6, !6, i64 0}
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!6 = !{!"any pointer", !7, i64 0}
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!7 = !{!"omnipotent char", !8, i64 0}
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!8 = !{!"Simple C/C++ TBAA"}
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!9 = distinct !{!9, !10}
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!10 = !{!"llvm.loop.mustprogress"}
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!11 = distinct !{!11, !10}
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...
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---
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name: f
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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noPhis: false
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isSSA: true
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noVRegs: false
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hasFakeUses: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 1, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 2, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 3, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 4, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 5, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 6, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 7, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 8, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 9, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 10, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 11, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 12, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 13, class: predregs, preferred-register: '', flags: [ ] }
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- { id: 14, class: predregs, preferred-register: '', flags: [ ] }
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- { id: 15, class: intregs, preferred-register: '', flags: [ ] }
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liveins:
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- { reg: '$r0', virtual-reg: '%9' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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isCalleeSavedInfoValid: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0
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%9:intregs = COPY $r0
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%11:intregs = A2_tfrsi 2
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%12:intregs = A2_max %9, %11
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%0:intregs = nsw A2_addi %12, -4
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%1:intregs = S4_addi_asl_ri @a, %12, 3
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%2:intregs = A2_tfrsi @a
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%10:intregs = A2_tfrsi 256
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bb.1.do.body:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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%3:intregs = PHI %1, %bb.0, %8, %bb.1
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%4:intregs = PHI %0, %bb.0, %7, %bb.1
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%5:intregs = PHI %10, %bb.0, %15, %bb.1
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%15:intregs = S2_extractu %5, 8, 1
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S4_storeri_rr %2, %15, 2, %3 :: (store (s32) into %ir.cgep5, !tbaa !5)
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%7:intregs = nsw A2_addi %4, 4
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%13:predregs = C2_cmpgtui %7, 1073741835
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%8:intregs = A2_addi %3, 32
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J2_jumpf %13, %bb.1, implicit-def dead $pc
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J2_jump %bb.2, implicit-def dead $pc
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bb.2.do.end:
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PS_jmpret $r31, implicit-def dead $pc
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...
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---
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name: g
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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noPhis: false
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isSSA: true
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noVRegs: false
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hasFakeUses: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 1, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 2, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 3, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 4, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 5, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 6, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 7, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 8, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 9, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 10, class: intregs, preferred-register: '', flags: [ ] }
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- { id: 11, class: predregs, preferred-register: '', flags: [ ] }
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- { id: 12, class: predregs, preferred-register: '', flags: [ ] }
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- { id: 13, class: intregs, preferred-register: '', flags: [ ] }
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liveins:
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- { reg: '$r0', virtual-reg: '%9' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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isCalleeSavedInfoValid: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0
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%9:intregs = COPY $r0
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%0:intregs = A2_addi %9, -4
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%1:intregs = S4_addi_asl_ri @a, %9, 3
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%2:intregs = A2_tfrsi @a
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%10:intregs = A2_tfrsi 256
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bb.1.do.body:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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%3:intregs = PHI %1, %bb.0, %8, %bb.1
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%4:intregs = PHI %0, %bb.0, %7, %bb.1
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%5:intregs = PHI %10, %bb.0, %13, %bb.1
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%13:intregs = S2_extractu %5, 8, 1
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S4_storeri_rr %2, %13, 2, %3 :: (store (s32) into %ir.cgep5, !tbaa !5)
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%7:intregs = A2_addi %4, 4
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%11:predregs = C2_cmpgti %7, 1073741835
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%8:intregs = A2_addi %3, 32
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J2_jumpf %11, %bb.1, implicit-def dead $pc
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J2_jump %bb.2, implicit-def dead $pc
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bb.2.do.end:
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PS_jmpret $r31, implicit-def dead $pc
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...
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@ -5,8 +5,9 @@
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; the same stage.
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; CHECK-DAG: [[REG3:(r[0-9]+)]] = add([[REG1:(r[0-9]+)]],#-1)
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; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG1]],#-1)
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; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG3]])
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; CHECK-DAG: [[REG2:(r[0-9]+)]] = add([[REG4:(r[0-9]+)]],#-1)
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; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],[[REG2]])
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; CHECK-NOT: = [[REG3]]
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; CHECK-NOT: = [[REG2]]
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: }{{[ \t]*}}:endloop
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