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Set the floating point status register as reserved

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Summary:
This patch sets the FPSW (X87 floating-point status register) as a reserved
physical register and fix the test failure caused by [[ https://reviews.llvm.org/D68854| D68854 ]].

Before this patch, some tests will fail because it implicit uses FPSW without
define it. Setting the FPSW as a reserved physical register will skip liveness
analysis because it is always live.

Reviewers: pengfei, craig.topper

Reviewed By: craig.topper

Subscribers: craig.topper, hiraditya, llvm-commits

Patch by LiuChen.

Differential Revision: https://reviews.llvm.org/D69784
This commit is contained in:
Pengfei Wang 2019-11-03 23:13:51 -08:00
parent 31e14f41a2
commit 8d7ccb3744
2 changed files with 4 additions and 1 deletions
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3
llvm/lib/Target/X86/X86RegisterInfo.cpp
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@ -523,6 +523,9 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// Set the floating point control register as reserved.
Reserved.set(X86::FPCW);
// Set the floating point status register as reserved.
Reserved.set(X86::FPSW);
// Set the SIMD floating point control register as reserved.
Reserved.set(X86::MXCSR);

2
llvm/test/CodeGen/X86/pr34080-2.ll
View File

@ -62,13 +62,13 @@ define void @computeJD(%struct.DateTime*) nounwind {
; CHECK-NEXT: imull $60000, 24(%ebx), %ecx # imm = 0xEA60
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: fldl 28(%ebx)
; CHECK-NEXT: fmuls {{\.LCPI.*}}
; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: fmuls {{\.LCPI.*}}
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
; CHECK-NEXT: fistpll {{[0-9]+}}(%esp)
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)