[OFFLOAD] Build DeviceRTL with SPIRV backend (#174675)
This PR adds configuration to build DeviceRTL with SPIRV backend. It is primarily used for level-zero plugin for Intel GPUs --------- Co-authored-by: Joseph Huber <huberjn@outlook.com>
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@ -158,8 +158,8 @@ else()
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endif()
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# Use the current compiler target to determine the appropriate runtime to build.
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if("${LLVM_DEFAULT_TARGET_TRIPLE}" MATCHES "^amdgcn|^nvptx" OR
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"${CMAKE_CXX_COMPILER_TARGET}" MATCHES "^amdgcn|^nvptx")
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if("${LLVM_DEFAULT_TARGET_TRIPLE}" MATCHES "^amdgcn|^nvptx|^spirv64" OR
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"${CMAKE_CXX_COMPILER_TARGET}" MATCHES "^amdgcn|^nvptx|^spirv64")
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add_subdirectory(device)
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else()
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add_subdirectory(module)
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@ -33,6 +33,7 @@ list(APPEND compile_options -fno-rtti)
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list(APPEND compile_options -fno-exceptions)
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list(APPEND compile_options -fconvergent-functions)
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list(APPEND compile_options -Wno-unknown-cuda-version)
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if(LLVM_DEFAULT_TARGET_TRIPLE)
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list(APPEND compile_options --target=${LLVM_DEFAULT_TARGET_TRIPLE})
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endif()
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@ -52,6 +53,9 @@ elseif("${LLVM_DEFAULT_TARGET_TRIPLE}" MATCHES "^nvptx" OR
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"${CMAKE_CXX_COMPILER_TARGET}" MATCHES "^nvptx")
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set(target_name "nvptx")
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list(APPEND compile_options --cuda-feature=+ptx63)
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elseif("${LLVM_DEFAULT_TARGET_TRIPLE}" MATCHES "^spirv64" OR
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"${CMAKE_CXX_COMPILER_TARGET}" MATCHES "^spirv64")
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set(target_name "spirv")
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endif()
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# Trick to combine these into a bitcode file via the linker's LTO pass.
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@ -74,8 +78,15 @@ target_include_directories(libompdevice PRIVATE
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${CMAKE_CURRENT_SOURCE_DIR}/../../libc
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${CMAKE_CURRENT_SOURCE_DIR}/../../offload/include)
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target_compile_options(libompdevice PRIVATE ${compile_options})
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target_link_options(libompdevice PRIVATE
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"-flto" "-r" "-nostdlib" "-Wl,--lto-emit-llvm")
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if(NOT "${LLVM_DEFAULT_TARGET_TRIPLE}" MATCHES "^spirv" AND
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NOT "${CMAKE_CXX_COMPILER_TARGET}" MATCHES "^spirv")
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target_link_options(libompdevice PRIVATE
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"-flto" "-r" "-nostdlib" "-Wl,--lto-emit-llvm")
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else()
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target_link_options(libompdevice PRIVATE
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"-nostdlib" "-emit-llvm")
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endif()
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if(LLVM_DEFAULT_TARGET_TRIPLE)
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target_link_options(libompdevice PRIVATE "--target=${LLVM_DEFAULT_TARGET_TRIPLE}")
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endif()
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@ -131,7 +131,17 @@ struct IdentTy {
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using __kmpc_impl_lanemask_t = LaneMaskTy;
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using ParallelRegionFnTy = void *;
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#ifdef __SPIRV__
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// Function pointers in SPIRV backend have a special address space 9.
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// Since function pointers are passed as regular void * pointers it is
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// necessary to annotate them with proper address space to avoid casting
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// errors during compilation.
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using FnPtrTy = void [[clang::address_space(9)]] *;
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#else
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using FnPtrTy = void *;
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#endif
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using ParallelRegionFnTy = FnPtrTy;
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using CriticalNameTy = int32_t[8];
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@ -219,7 +219,7 @@ lookup32(ValueKind Kind, bool IsReadonly, IdentTy *Ident, bool ForceTeamState) {
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__builtin_unreachable();
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}
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[[gnu::always_inline, gnu::flatten]] inline void *&
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[[gnu::always_inline, gnu::flatten]] inline FnPtrTy &
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lookupPtr(ValueKind Kind, bool IsReadonly, bool ForceTeamState) {
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switch (Kind) {
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case state::VK_ParallelRegionFn:
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@ -42,7 +42,20 @@ enum MemScopeTy {
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template <typename Ty, typename V = utils::remove_addrspace_t<Ty>>
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V inc(Ty *Address, V Val, atomic::OrderingTy Ordering,
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MemScopeTy MemScope = MemScopeTy::device) {
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#if defined(__SPIRV__)
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uint32_t Old;
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while (true) {
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Old = load(Address, Ordering, MemScope);
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if (Old >= Val) {
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if (cas(Address, Old, 0u, Ordering, Ordering, MemScope))
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break;
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} else if (cas(Address, Old, Old + 1, Ordering, Ordering, MemScope))
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break;
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}
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return Old;
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#else
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return __scoped_atomic_fetch_uinc(Address, Val, Ordering, MemScope);
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#endif
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}
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template <typename Ty, typename V = utils::remove_addrspace_t<Ty>>
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@ -23,7 +23,7 @@ using namespace allocator;
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// Provide a default implementation of malloc / free for AMDGPU platforms built
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// without 'libc' support.
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extern "C" {
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#if defined(__AMDGPU__) && !defined(OMPTARGET_HAS_LIBC)
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#if (defined(__AMDGPU__) || defined(__SPIRV__)) && !defined(OMPTARGET_HAS_LIBC)
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[[gnu::weak]] void *malloc(size_t Size) { return allocator::alloc(Size); }
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[[gnu::weak]] void free(void *Ptr) { allocator::free(Ptr); }
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#else
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@ -68,7 +68,7 @@ uint32_t determineNumberOfThreads(int32_t NumThreadsClause) {
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// Invoke an outlined parallel function unwrapping arguments (up to 32).
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[[clang::always_inline]] void invokeMicrotask(int32_t global_tid,
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int32_t bound_tid, void *fn,
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int32_t bound_tid, FnPtrTy fn,
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void **args, int64_t nargs) {
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switch (nargs) {
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#include "generated_microtask_cases.gen"
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@ -84,7 +84,7 @@ extern "C" {
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[[clang::always_inline]] void __kmpc_parallel_spmd(IdentTy *ident,
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int32_t num_threads,
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void *fn, void **args,
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FnPtrTy fn, void **args,
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const int64_t nargs) {
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uint32_t TId = mapping::getThreadIdInBlock();
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uint32_t NumThreads = determineNumberOfThreads(num_threads);
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@ -142,8 +142,8 @@ extern "C" {
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[[clang::always_inline]] void
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__kmpc_parallel_60(IdentTy *ident, int32_t, int32_t if_expr,
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int32_t num_threads, int proc_bind, void *fn,
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void *wrapper_fn, void **args, int64_t nargs,
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int32_t num_threads, int proc_bind, FnPtrTy fn,
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FnPtrTy wrapper_fn, void **args, int64_t nargs,
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int32_t nt_strict) {
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uint32_t TId = mapping::getThreadIdInBlock();
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@ -261,7 +261,7 @@ __kmpc_parallel_60(IdentTy *ident, int32_t, int32_t if_expr,
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1u, true, ident,
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/*ForceTeamState=*/true);
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state::ValueRAII ParallelRegionFnRAII(state::ParallelRegionFn, wrapper_fn,
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(void *)nullptr, true, ident,
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(FnPtrTy) nullptr, true, ident,
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/*ForceTeamState=*/true);
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state::ValueRAII ActiveLevelRAII(icv::ActiveLevel, 1u, 0u, true, ident,
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/*ForceTeamState=*/true);
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@ -186,6 +186,37 @@ void setCriticalLock(omp_lock_t *Lock) { setLock(Lock); }
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#endif
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///}
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#if defined(__SPIRV__)
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void namedBarrierInit() { __builtin_trap(); } // TODO
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void namedBarrier() { __builtin_trap(); } // TODO
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void unsetLock(omp_lock_t *Lock) {
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atomic::store((int32_t *)Lock, 0, atomic::seq_cst);
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}
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int testLock(omp_lock_t *Lock) {
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return atomic::add((int32_t *)Lock, 0, atomic::seq_cst);
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}
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void initLock(omp_lock_t *Lock) { unsetLock(Lock); }
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void destroyLock(omp_lock_t *Lock) { unsetLock(Lock); }
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void setLock(omp_lock_t *Lock) {
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int32_t *Lock_ptr = (int32_t *)Lock;
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bool Acquired = false;
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int32_t Expected;
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while (!Acquired) {
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Expected = 0;
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if (Expected == atomic::load(Lock_ptr, atomic::seq_cst))
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Acquired =
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atomic::cas(Lock_ptr, Expected, 1, atomic::seq_cst, atomic::seq_cst);
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}
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}
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void unsetCriticalLock(omp_lock_t *Lock) { unsetLock(Lock); }
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void setCriticalLock(omp_lock_t *Lock) { setLock(Lock); }
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void syncThreadsAligned(atomic::OrderingTy Ordering) {
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synchronize::threads(Ordering);
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}
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#endif
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} // namespace impl
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void synchronize::init(bool IsSPMD) {
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