shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

PreISelIntrinsicLowering: Lower llvm.log to a loop if scalable vec arg (#129744)

Browse Source 
Similar to ab976a1, but for llvm.log.

(cherry picked from commit 19ada02086c371dda75ec9704e50e1e28f1758bb)
This commit is contained in:
Stephen Long 2025-08-11 12:04:28 -04:00 committed by Tobias Hieta
parent 6096d35ea9
commit 8e0e800222
No known key found for this signature in database
GPG Key ID: 44F2485E45D59042
3 changed files with 44 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
View File

@ -587,12 +587,14 @@ bool PreISelIntrinsicLowering::lowerIntrinsics(Module &M) const {
break;
case Intrinsic::exp:
case Intrinsic::exp2:
case Intrinsic::log:
Changed |= forEachCall(F, [&](CallInst *CI) {
Type *Ty = CI->getArgOperand(0)->getType();
if (!isa<ScalableVectorType>(Ty))
return false;
const TargetLowering *TL = TM->getSubtargetImpl(F)->getTargetLowering();
unsigned Op = TL->IntrinsicIDToISD(F.getIntrinsicID());
assert(Op != ISD::DELETED_NODE && "unsupported intrinsic");
if (!TL->isOperationExpand(Op, EVT::getEVT(Ty)))
return false;
return lowerUnaryVectorIntrinsicAsLoop(M, CI);

2
llvm/lib/CodeGen/TargetLoweringBase.cpp
View File

@ -1922,6 +1922,8 @@ int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
return ISD::FEXP;
case Intrinsic::exp2:
return ISD::FEXP2;
case Intrinsic::log:
return ISD::FLOG;
default:
return ISD::DELETED_NODE;
}

40
llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll Normal file
View File

@ -0,0 +1,40 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s
target triple = "aarch64"
define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT: br label %[[BB3:.*]]
; CHECK: [[BB3]]:
; CHECK-NEXT: [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT: [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK: [[BB11]]:
; CHECK-NEXT: ret <vscale x 4 x float> [[TMP8]]
;
%output = call <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float> %input)
ret <vscale x 4 x float> %output
}
define <4 x float> @fixed_vec_log(<4 x float> %input) {
; CHECK-LABEL: define <4 x float> @fixed_vec_log(
; CHECK-SAME: <4 x float> [[INPUT:%.*]]) {
; CHECK-NEXT: [[OUTPUT:%.*]] = call <4 x float> @llvm.log.v4f32(<4 x float> [[INPUT]])
; CHECK-NEXT: ret <4 x float> [[OUTPUT]]
;
%output = call <4 x float> @llvm.log.v4f32(<4 x float> %input)
ret <4 x float> %output
}
declare <4 x float> @llvm.log.v4f32(<4 x float>) #0
declare <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float>) #0
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }