From 8f1accfb35f2da96e8521efcabdabec74a28bc4e Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 11 Dec 2023 22:46:42 -0800 Subject: [PATCH] Revert "[RISCV] Update the interface of sifive vqmaccqoq (#74284)" This reverts commit dc5570319676c14c48440b4ee87c8cfb35102ff6. Several bots seem to be failing: https://lab.llvm.org/buildbot/#/builders/10/builds/34651 https://lab.llvm.org/buildbot/#/builders/178/builds/6320 https://lab.llvm.org/buildbot/#/builders/77/builds/32918 --- .../clang/Basic/riscv_sifive_vector.td | 26 +++----- .../non-overloaded/sf_vqmacc_4x8x4.c | 24 ++++---- .../non-overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++---- .../non-overloaded/sf_vqmaccu_4x8x4.c | 24 ++++---- .../non-overloaded/sf_vqmaccus_4x8x4.c | 24 ++++---- .../non-policy/overloaded/sf_vqmacc_4x8x4.c | 24 ++++---- .../non-policy/overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++---- .../non-policy/overloaded/sf_vqmaccu_4x8x4.c | 24 ++++---- .../non-policy/overloaded/sf_vqmaccus_4x8x4.c | 24 ++++---- .../policy/non-overloaded/sf_vqmacc_4x8x4.c | 24 ++++---- .../policy/non-overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++---- .../policy/non-overloaded/sf_vqmaccu_4x8x4.c | 24 ++++---- .../policy/non-overloaded/sf_vqmaccus_4x8x4.c | 24 ++++---- .../policy/overloaded/sf_vqmacc_4x8x4.c | 24 ++++---- .../policy/overloaded/sf_vqmaccsu_4x8x4.c | 24 ++++---- .../policy/overloaded/sf_vqmaccu_4x8x4.c | 24 ++++---- .../policy/overloaded/sf_vqmaccus_4x8x4.c | 24 ++++---- clang/test/Sema/rvv-required-features.c | 18 +++++- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 61 +++++++------------ .../test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll | 58 +++++++++--------- .../CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll | 58 +++++++++--------- .../CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll | 58 +++++++++--------- .../CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll | 58 +++++++++--------- 23 files changed, 360 insertions(+), 361 deletions(-) diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td index 61c2ff52d9f7..bb54e2664186 100644 --- a/clang/include/clang/Basic/riscv_sifive_vector.td +++ b/clang/include/clang/Basic/riscv_sifive_vector.td @@ -112,7 +112,7 @@ multiclass RVVVFWMACCBuiltinSet> suffixes_prototypes> { defm NAME : RVVOutOp1Op2BuiltinSet; } -multiclass RVVVQMACCDODBuiltinSet> suffixes_prototypes> { +multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> { let OverloadedName = NAME, Name = NAME, HasMasked = false, @@ -120,14 +120,6 @@ multiclass RVVVQMACCDODBuiltinSet> suffixes_prototypes> { defm NAME : RVVOutOp1Op2BuiltinSet; } -multiclass RVVVQMACCQOQBuiltinSet> suffixes_prototypes> { - let OverloadedName = NAME, - Name = NAME, - HasMasked = false, - Log2LMUL = [-1, 0, 1, 2] in - defm NAME : RVVOutOp1Op2BuiltinSet; -} - multiclass RVVVFNRCLIPBuiltinSet { let Log2LMUL = [-3, -2, -1, 0, 1, 2], Name = NAME, @@ -138,18 +130,18 @@ multiclass RVVVFNRCLIPBuiltinSet; - defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>; - defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>; - defm sf_vqmaccsu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>; + defm sf_vqmaccu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>; + defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>; + defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>; + defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>; } let UnMaskedPolicyScheme = HasPolicyOperand in let RequiredFeatures = ["Xsfvqmaccqoq"] in { - defm sf_vqmaccu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)Uw"]]>; - defm sf_vqmacc_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)w"]]>; - defm sf_vqmaccus_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)w"]]>; - defm sf_vqmaccsu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)Uw"]]>; + defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>; + defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>; + defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>; + defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>; } let UnMaskedPolicyScheme = HasPolicyOperand in diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c index 80e1c443eb54..935cb2e007d3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m1(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m2(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m8(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c index 8c0a6218c1d2..f34517b24bcf 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m1(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m2(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m8(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c index b40891f417f2..ab7f6627ad1f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m1(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m2(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m8(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c index d106aab64c51..d0bcdcbf40cc 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m1(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m2(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m8(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c index 88fae7306944..839d09c4f9a9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c index 0aec4bfd9fe2..b18853043e92 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c index 81965e86f77c..4cb966b08f23 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c index f2544cf3ef2a..f558151f88a3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c index 8fdeac62a31f..05c10840cabf 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m1_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m2_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_i32m8_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c index e02c790dfbeb..bce1a4e9443f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m1_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m2_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_i32m8_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c index ddeb6de00716..36aaae9caebf 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m1_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m2_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_i32m8_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c index 397e406c2ee5..f5ac2bf0f1f3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m1_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m2_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_i32m8_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c index 7b3b25a20331..531bc2b2b942 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmacc_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmacc_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmacc_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmacc_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmacc_4x8x4_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c index 2f3cbeec26fc..23bba523aaa4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1_tu(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2_tu(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4_tu(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8_tu(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccsu_4x8x4_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c index 1f2b2a1c8645..950688c6c785 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccu_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccu_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccu_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccu_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccu_4x8x4_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c index 923234fe8e2b..7bdce95043ee 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c @@ -7,41 +7,41 @@ #include // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +vint32m1_t test_sf_vqmaccus_4x8x4_i32m1_tu(vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, size_t vl) { +vint32m2_t test_sf_vqmaccus_4x8x4_i32m2_tu(vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, size_t vl) { +vint32m4_t test_sf_vqmaccus_4x8x4_i32m4_tu(vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); } // CHECK-RV64-LABEL: define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64( [[VD]], [[VS1]], [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: ret [[TMP0]] // -vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, size_t vl) { +vint32m8_t test_sf_vqmaccus_4x8x4_i32m8_tu(vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, size_t vl) { return __riscv_sf_vqmaccus_4x8x4_tu(vd, vs1, vs2, vl); } diff --git a/clang/test/Sema/rvv-required-features.c b/clang/test/Sema/rvv-required-features.c index 5846f338aa80..2714ef04b9bf 100644 --- a/clang/test/Sema/rvv-required-features.c +++ b/clang/test/Sema/rvv-required-features.c @@ -1,6 +1,8 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp \ -// RUN: -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq %s -fsyntax-only -verify +// RUN: -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq \ +// RUN: -target-feature +experimental-zvfbfmin -target-feature +xsfvfwmaccqqq \ +// RUN: -target-feature +xsfvfnrclipxfqf %s -fsyntax-only -verify // expected-no-diagnostics @@ -23,6 +25,18 @@ void test_xsfvqmaccdod(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl); } -void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) { +void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) { __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl); } + +void test_xsfvfwmaccqqq(vfloat32m1_t vd, vbfloat16m1_t vs1, vbfloat16mf2_t vs2, size_t vl) { + __riscv_sf_vfwmacc_4x4x4(vd, vs1, vs2, vl); +} + +void test_xsfvfnrclipxufqf(vfloat32m1_t vs1, float rs2, size_t vl) { + __riscv_sf_vfnrclip_xu_f_qf(vs1, rs2, vl); +} + +void test_xsfvfnrclipxfqf(vfloat32m1_t vs1, float rs2, size_t vl) { + __riscv_sf_vfnrclip_x_f_qf(vs1, rs2, vl); +} diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 9812aa501e04..fa618b437ce7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -349,20 +349,14 @@ multiclass VPseudoSiFiveVMACC; } -multiclass VPseudoSiFiveVQMACCDOD { +multiclass VPseudoSiFiveVQMACC { foreach m = MxListVF8 in defm NAME : VPseudoSiFiveVMACC; } -multiclass VPseudoSiFiveVQMACCQOQ { - foreach m = MxListVF8 in - defm NAME : VPseudoSiFiveVMACC; -} - multiclass VPseudoSiFiveVFWMACC { - foreach i = [0, 1, 2, 3, 4] in - defm NAME : VPseudoSiFiveVMACC; + foreach m = MxListFW in + defm NAME : VPseudoSiFiveVMACC; } multiclass VPseudoSiFiveVFNRCLIP { @@ -404,17 +398,17 @@ let Predicates = [HasVendorXSfvcp] in { } let Predicates = [HasVendorXSfvqmaccdod] in { - defm VQMACCU_2x8x2 : VPseudoSiFiveVQMACCDOD; - defm VQMACC_2x8x2 : VPseudoSiFiveVQMACCDOD; - defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD; - defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD; + defm VQMACCU_2x8x2 : VPseudoSiFiveVQMACC; + defm VQMACC_2x8x2 : VPseudoSiFiveVQMACC; + defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACC; + defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACC; } let Predicates = [HasVendorXSfvqmaccqoq] in { - defm VQMACCU_4x8x4 : VPseudoSiFiveVQMACCQOQ; - defm VQMACC_4x8x4 : VPseudoSiFiveVQMACCQOQ; - defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ; - defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ; + defm VQMACCU_4x8x4 : VPseudoSiFiveVQMACC; + defm VQMACC_4x8x4 : VPseudoSiFiveVQMACC; + defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACC; + defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACC; } let Predicates = [HasVendorXSfvfwmaccqqq] in { @@ -565,30 +559,21 @@ multiclass VPatVMACC; } } -defset list VQMACCDODInfoPairs = { +defset list VQMACCInfoPairs = { def : VTypeInfoToWide; def : VTypeInfoToWide; def : VTypeInfoToWide; def : VTypeInfoToWide; } -defset list VQMACCQOQInfoPairs = { - def : VTypeInfoToWide; - def : VTypeInfoToWide; - def : VTypeInfoToWide; - def : VTypeInfoToWide; -} +multiclass VPatVQMACC + : VPatVMACC; -multiclass VPatVQMACCDOD - : VPatVMACC; - -multiclass VPatVQMACCQOQ - : VPatVMACC; multiclass VPatVFWMACC : VPatVMACC; - defm : VPatVQMACCDOD<"vqmacc_2x8x2", "VQMACC", "2x8x2">; - defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">; - defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">; + defm : VPatVQMACC<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">; + defm : VPatVQMACC<"vqmacc_2x8x2", "VQMACC", "2x8x2">; + defm : VPatVQMACC<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">; + defm : VPatVQMACC<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">; } let Predicates = [HasVendorXSfvqmaccqoq] in { - defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">; - defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "VQMACC", "4x8x4">; - defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">; - defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">; + defm : VPatVQMACC<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">; + defm : VPatVQMACC<"vqmacc_4x8x4", "VQMACC", "4x8x4">; + defm : VPatVQMACC<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">; + defm : VPatVQMACC<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">; } let Predicates = [HasVendorXSfvfwmaccqqq] in { diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll index 300fda43ada4..843e4bda4d12 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll @@ -7,10 +7,10 @@ declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmacc_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma @@ -20,13 +20,13 @@ entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmacc_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma @@ -36,7 +36,7 @@ entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -45,36 +45,36 @@ entry: declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmacc_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmacc_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -83,36 +83,36 @@ entry: declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmacc_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmacc_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -121,36 +121,38 @@ entry: declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmacc_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma +; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmacc_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmacc_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma +; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll index 1df81527850e..45a3b22d9618 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll @@ -7,10 +7,10 @@ declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccsu_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma @@ -20,13 +20,13 @@ entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccsu_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma @@ -36,7 +36,7 @@ entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -45,36 +45,36 @@ entry: declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccsu_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccsu_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -83,36 +83,36 @@ entry: declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccsu_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccsu_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -121,36 +121,38 @@ entry: declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccsu_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma +; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccsu_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccsu_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma +; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll index be2ce2fffe31..9d15ab68a091 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll @@ -7,10 +7,10 @@ declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccu_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma @@ -20,13 +20,13 @@ entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccu_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma @@ -36,7 +36,7 @@ entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -45,36 +45,36 @@ entry: declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccu_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccu_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -83,36 +83,36 @@ entry: declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccu_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccu_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -121,36 +121,38 @@ entry: declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccu_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma +; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccu_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccu_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma +; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll index caa1b226bd39..d9b62d8a5769 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll @@ -7,10 +7,10 @@ declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccus_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_tu_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma @@ -20,13 +20,13 @@ entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccus_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_ta_i32m1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma @@ -36,7 +36,7 @@ entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -45,36 +45,36 @@ entry: declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccus_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_tu_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccus_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_ta_i32m2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v10, v11 +; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -83,36 +83,36 @@ entry: declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccus_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_tu_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccus_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_ta_i32m4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v12, v14 +; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a @@ -121,36 +121,38 @@ entry: declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8( , , - , + , iXLen, iXLen); -define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma -; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma +; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 2) ret %a } -define @intrinsic_vqmaccus_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { +define @intrinsic_vqmaccus_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v16, v20 +; CHECK-NEXT: vl8r.v v24, (a0) +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma +; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8( %0, %1, - %2, + %2, iXLen %3, iXLen 3) ret %a