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[AArch64] Remove SIMDLongThreeVectorTiedBHSabal tablegen class.

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Similar to #152987 this removes SIMDLongThreeVectorTiedBHSabal as it is
equivalent to SIMDLongThreeVectorTiedBHS with a better TriOpFrag pattern.
This commit is contained in:
David Green 2025-08-18 09:11:13 +01:00
parent 8181c76bca
commit 8f98529209
2 changed files with 15 additions and 58 deletions
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44
llvm/lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -7405,50 +7405,6 @@ multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
(extract_high_v4i32 (v4i32 V128:$Rm))))]>;
}
multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
string asm,
SDPatternOperator OpNode> {
def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
V128, V64, V64,
asm, ".8h", ".8b", ".8b",
[(set (v8i16 V128:$dst),
(add (v8i16 V128:$Rd),
(zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
V128, V128, V128,
asm#"2", ".8h", ".16b", ".16b",
[(set (v8i16 V128:$dst),
(add (v8i16 V128:$Rd),
(zext (v8i8 (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
(extract_high_v16i8 (v16i8 V128:$Rm)))))))]>;
def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
V128, V64, V64,
asm, ".4s", ".4h", ".4h",
[(set (v4i32 V128:$dst),
(add (v4i32 V128:$Rd),
(zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
V128, V128, V128,
asm#"2", ".4s", ".8h", ".8h",
[(set (v4i32 V128:$dst),
(add (v4i32 V128:$Rd),
(zext (v4i16 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
(extract_high_v8i16 (v8i16 V128:$Rm)))))))]>;
def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
V128, V64, V64,
asm, ".2d", ".2s", ".2s",
[(set (v2i64 V128:$dst),
(add (v2i64 V128:$Rd),
(zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
V128, V128, V128,
asm#"2", ".2d", ".4s", ".4s",
[(set (v2i64 V128:$dst),
(add (v2i64 V128:$Rd),
(zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
(extract_high_v4i32 (v4i32 V128:$Rm)))))))]>;
}
let isCommutable = 1 in
multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
SDPatternOperator OpNode = null_frag> {

9
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -6788,7 +6788,8 @@ defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn
defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
let isCommutable = 1 in
defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;
defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", abds>;
defm SABAL : SIMDLongThreeVectorTiedBHS<0,0b0101,"sabal",
TriOpFrag<(add node:$LHS, (zext (abds node:$MHS, node:$RHS)))>>;
defm SABDL : SIMDLongThreeVectorBHS<0, 0b0111, "sabdl",
BinOpFrag<(zext (abds node:$LHS, node:$RHS))>>;
defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
@ -6802,14 +6803,14 @@ defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", AArch64smull>;
defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", saddsat>;
defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", ssubsat>;
defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
int_aarch64_neon_sqdmull>;
defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", int_aarch64_neon_sqdmull>;
let isCommutable = 0 in
defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", abdu>;
defm UABAL : SIMDLongThreeVectorTiedBHS<1, 0b0101, "uabal",
TriOpFrag<(add node:$LHS, (zext (abdu node:$MHS, node:$RHS)))>>;
defm UABDL : SIMDLongThreeVectorBHS<1, 0b0111, "uabdl",
BinOpFrag<(zext (abdu node:$LHS, node:$RHS))>>;
defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",