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[AMDGPU] Remove GDS and GWS for GFX12 (#76148)

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This commit is contained in:
Jay Foad 2023-12-21 15:27:08 +00:00 committed by GitHub
parent 35111695dd
commit 8fdfd34cd2
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9 changed files with 45 additions and 11 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPU.td
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@ -1100,8 +1100,8 @@ def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
FeatureVOP3Literal, FeatureDPP8,
FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
FeatureA16, FeatureFastDenormalF32, FeatureG16,
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureGDS,
FeatureGWS, FeatureTrue16BitInsts
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
FeatureTrue16BitInsts
]
>;

12
llvm/lib/Target/AMDGPU/DSInstructions.td
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@ -1147,7 +1147,8 @@ def : GCNPat <
>;
} // End SubtargetPredicate = HasAtomicDsPkAdd16Insts
def : Pat <
let OtherPredicates = [HasGDS] in
def : GCNPat <
(SIds_ordered_count i32:$value, i16:$offset),
(DS_ORDERED_COUNT $value, (as_i16imm $offset))
>;
@ -1189,7 +1190,8 @@ def : GCNPat <
//===----------------------------------------------------------------------===//
class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
string opName = ps.Mnemonic>
string opName = ps.Mnemonic,
bit hasGFX12Enc = 0>
: DS_Real<ps, opName>, SIMCInstr <ps.Mnemonic, ef> {
let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
@ -1201,6 +1203,8 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
let gds = !if(hasGFX12Enc, 0, ?);
}
//===----------------------------------------------------------------------===//
@ -1212,7 +1216,7 @@ let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in {
defvar ps = !cast<DS_Pseudo>(NAME);
def _gfx12 :
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
ps.Mnemonic>;
ps.Mnemonic, 1>;
}
multiclass DS_Real_Renamed_gfx12<bits<8> op, DS_Pseudo backing_pseudo,
@ -1220,7 +1224,7 @@ let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in {
def _gfx12 :
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, backing_pseudo,
SIEncodingFamily.GFX12,
real_name>,
real_name, 1>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>,
Requires<[isGFX12Plus]>;
}

5
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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@ -702,6 +702,11 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
AMDGPU::OpName::src2_modifiers);
}
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) &&
!AMDGPU::hasGDS(STI)) {
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds);
}
if (Res && (MCII->get(MI.getOpcode()).TSFlags &
(SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) {
int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),

8
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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@ -4983,6 +4983,14 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}
if (isDS(MI) && !ST.hasGDS()) {
const MachineOperand *GDSOp = getNamedOperand(MI, AMDGPU::OpName::gds);
if (GDSOp && GDSOp->getImm() != 0) {
ErrInfo = "GDS is not supported on this subtarget";
return false;
}
}
if (isImage(MI)) {
const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
if (DimOp) {

1
llvm/test/CodeGen/AMDGPU/gds-unsupported.ll
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@ -1,4 +1,5 @@
; RUN: not --crash llc -march=amdgcn -mcpu=gfx90a < %s 2>&1 | FileCheck %s
; RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 < %s 2>&1 | FileCheck %s
; GDS is not supported on GFX90A+
; CHECK: LLVM ERROR: Cannot select: {{.*}} AtomicLoadAdd

3
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
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@ -1,5 +1,8 @@
; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
; RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
; GFX12-ERR: LLVM ERROR: Cannot select: {{.*}} = DS_ORDERED_COUNT
; FUNC-LABEL: {{^}}ds_ordered_add:
; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31

10
llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir Normal file
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@ -0,0 +1,10 @@
# RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 -run-pass=none -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX12 %s
---
name: gds
body: |
bb.0:
; GFX12: *** Bad machine code: GDS is not supported on this subtarget ***
; GFX12: - instruction: DS_ADD_U32 %0:vgpr_32, %1:vgpr_32, 0, 1, implicit $m0, implicit $exec :: (load store acq_rel (s32), addrspace 2)
DS_ADD_U32 %0:vgpr_32, %2:vgpr_32, 0, 1, implicit $m0, implicit $exec :: (load store acq_rel (s32), addrspace 2)
...

8
llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
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@ -34,6 +34,14 @@
# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0
# this is ds_add_f32 with gds bit which is not valid on gfx12+
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00
# this is image_msaa_load where samp field for gfx12 VSAMPLE is not all zeros
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00
# This is ds_read_b32 with gds bit which is not valid on gfx90a.
# GFX90A: [[@LINE+1]]:1: warning: invalid instruction encoding
0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00

5
llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
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@ -773,8 +773,3 @@
# GFX90A: flat_atomic_min_f64 v[0:1], v[0:1], v[2:3] glc ; encoding: [0x00,0x00,0x41,0xdd,0x00,0x02,0x00,0x00]
0x00,0x00,0x41,0xdd,0x00,0x02,0x00,0x00
# Disassembler still decodes the gds modifier even though the assembler does
# not accept it.
# GFX90A: ds_read_b32 v0, v1 gds ; encoding: [0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00]
0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00