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AMDGPU/GlobalISel: RegBankLegalize for global atomic ordered add (#180829)

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vangthao95 2026-02-11 09:30:11 -08:00 committed by GitHub
parent 182eb9d21a
commit 90a56a18ee
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2 changed files with 18 additions and 2 deletions
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3
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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@ -1412,6 +1412,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivB64}, {{VgprB64}, {IntrId, SgprP1}}})
.Any({{DivB128}, {{VgprB128}, {IntrId, SgprP1}}});
addRulesForIOpcs({amdgcn_global_atomic_ordered_add_b64})
.Any({{DivS64}, {{Vgpr64}, {IntrId, VgprP1, Vgpr64}}});
addRulesForIOpcs({amdgcn_wwm, amdgcn_strict_wwm}, StandardB)
.Div(B32, {{VgprB32}, {IntrId, VgprB32}})
.Uni(B32, {{SgprB32}, {IntrId, SgprB32}})

17
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
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@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12-SDAG %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12-GISEL %s
declare i64 @llvm.amdgcn.global.atomic.ordered.add.b64(ptr addrspace(1), i64)
@ -59,3 +59,16 @@ entry:
store i64 %val, ptr addrspace(1) %use
ret void
}
define amdgpu_ps i64 @global_atomic_ordered_add_b64_v(ptr addrspace(1) inreg %addr, i64 %val) {
; GCN-LABEL: global_atomic_ordered_add_b64_v:
; GCN: ; %bb.0:
; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: global_atomic_ordered_add_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN
; GCN-NEXT: s_wait_loadcnt 0x0
; GCN-NEXT: v_readfirstlane_b32 s0, v0
; GCN-NEXT: v_readfirstlane_b32 s1, v1
; GCN-NEXT: ; return to shader part epilog
%result = call i64 @llvm.amdgcn.global.atomic.ordered.add.b64(ptr addrspace(1) %addr, i64 %val)
ret i64 %result
}