[ARC][CSKY][Lanai] TableGen-erate SDNode descriptions (#138874)

This consolidates node definitions into one place and enables automatic
node verification.

Part of #119709.

llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp

@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARC.h"
+#include "ARCSelectionDAGInfo.h"
 #include "ARCTargetMachine.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"

llvm/lib/Target/ARC/ARCISelLowering.cpp

@@ -13,6 +13,7 @@
 #include "ARCISelLowering.h"
 #include "ARC.h"
 #include "ARCMachineFunctionInfo.h"
+#include "ARCSelectionDAGInfo.h"
 #include "ARCSubtarget.h"
 #include "ARCTargetMachine.h"
 #include "MCTargetDesc/ARCInfo.h"
@@ -178,24 +179,6 @@ ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
   setMaxAtomicSizeInBitsSupported(0);
 }
 
-const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const {
-  switch (Opcode) {
-  case ARCISD::BL:
-    return "ARCISD::BL";
-  case ARCISD::CMOV:
-    return "ARCISD::CMOV";
-  case ARCISD::CMP:
-    return "ARCISD::CMP";
-  case ARCISD::BRcc:
-    return "ARCISD::BRcc";
-  case ARCISD::RET:
-    return "ARCISD::RET";
-  case ARCISD::GAWRAPPER:
-    return "ARCISD::GAWRAPPER";
-  }
-  return nullptr;
-}
-
 //===----------------------------------------------------------------------===//
 //  Misc Lower Operation implementation
 //===----------------------------------------------------------------------===//

llvm/lib/Target/ARC/ARCISelLowering.h

@@ -24,36 +24,6 @@ namespace llvm {
 class ARCSubtarget;
 class ARCTargetMachine;
 
-namespace ARCISD {
-
-enum NodeType : unsigned {
-  // Start the numbering where the builtin ops and target ops leave off.
-  FIRST_NUMBER = ISD::BUILTIN_OP_END,
-
-  // Branch and link (call)
-  BL,
-
-  // Jump and link (indirect call)
-  JL,
-
-  // CMP
-  CMP,
-
-  // CMOV
-  CMOV,
-
-  // BRcc
-  BRcc,
-
-  // Global Address Wrapper
-  GAWRAPPER,
-
-  // return, (j_s [blink])
-  RET
-};
-
-} // end namespace ARCISD
-
 //===--------------------------------------------------------------------===//
 // TargetLowering Implementation
 //===--------------------------------------------------------------------===//
@@ -65,9 +35,6 @@ public:
   /// Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-  /// This method returns the name of a target specific DAG node.
-  const char *getTargetNodeName(unsigned Opcode) const override;
-
   /// Return true if the addressing mode represented by AM is legal for this
   /// target, for a load/store of the specified type.
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,

llvm/lib/Target/ARC/ARCSelectionDAGInfo.cpp

@@ -0,0 +1,19 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARCSelectionDAGInfo.h"
+
+#define GET_SDNODE_DESC
+#include "ARCGenSDNodeInfo.inc"
+
+using namespace llvm;
+
+ARCSelectionDAGInfo::ARCSelectionDAGInfo()
+    : SelectionDAGGenTargetInfo(ARCGenSDNodeInfo) {}
+
+ARCSelectionDAGInfo::~ARCSelectionDAGInfo() = default;

llvm/lib/Target/ARC/ARCSelectionDAGInfo.h

@@ -0,0 +1,28 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARC_ARCSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_ARC_ARCSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+#define GET_SDNODE_ENUM
+#include "ARCGenSDNodeInfo.inc"
+
+namespace llvm {
+
+class ARCSelectionDAGInfo : public SelectionDAGGenTargetInfo {
+public:
+  ARCSelectionDAGInfo();
+
+  ~ARCSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_ARC_ARCSELECTIONDAGINFO_H

llvm/lib/Target/ARC/ARCSubtarget.cpp

@@ -12,6 +12,7 @@
 
 #include "ARCSubtarget.h"
 #include "ARC.h"
+#include "ARCSelectionDAGInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 
 using namespace llvm;
@@ -27,4 +28,12 @@ void ARCSubtarget::anchor() {}
 ARCSubtarget::ARCSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const TargetMachine &TM)
     : ARCGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), InstrInfo(*this),
-      FrameLowering(*this), TLInfo(TM, *this) {}
+      FrameLowering(*this), TLInfo(TM, *this) {
+  TSInfo = std::make_unique<ARCSelectionDAGInfo>();
+}
+
+ARCSubtarget::~ARCSubtarget() = default;
+
+const SelectionDAGTargetInfo *ARCSubtarget::getSelectionDAGInfo() const {
+  return TSInfo.get();
+}

llvm/lib/Target/ARC/ARCSubtarget.h

@@ -16,7 +16,6 @@
 #include "ARCFrameLowering.h"
 #include "ARCISelLowering.h"
 #include "ARCInstrInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include <string>
 
@@ -33,7 +32,7 @@ class ARCSubtarget : public ARCGenSubtargetInfo {
   ARCInstrInfo InstrInfo;
   ARCFrameLowering FrameLowering;
   ARCTargetLowering TLInfo;
-  SelectionDAGTargetInfo TSInfo;
+  std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
 
   // ARC processor extensions
   bool Xnorm = false;
@@ -44,6 +43,8 @@ public:
   ARCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
                const TargetMachine &TM);
 
+  ~ARCSubtarget() override;
+
   /// Parses features string setting specified subtarget options.
   /// Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
@@ -58,9 +59,8 @@ public:
   const ARCRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
-  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
-    return &TSInfo;
-  }
+
+  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
 
   bool hasNorm() const { return Xnorm; }
 };

llvm/lib/Target/ARC/CMakeLists.txt

@@ -8,6 +8,7 @@ tablegen(LLVM ARCGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM ARCGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM ARCGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM ARCGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM ARCGenSDNodeInfo.inc -gen-sd-node-info)
 tablegen(LLVM ARCGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(ARCCommonTableGen)
@@ -24,6 +25,7 @@ add_llvm_target(ARCCodeGen
   ARCMCInstLower.cpp
   ARCOptAddrMode.cpp
   ARCRegisterInfo.cpp
+  ARCSelectionDAGInfo.cpp
   ARCSubtarget.cpp
   ARCTargetMachine.cpp
 

llvm/lib/Target/CSKY/CMakeLists.txt

@@ -12,6 +12,7 @@ tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM CSKYGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM CSKYGenSDNodeInfo.inc -gen-sd-node-info)
 tablegen(LLVM CSKYGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(CSKYCommonTableGen)
@@ -26,6 +27,7 @@ add_llvm_target(CSKYCodeGen
   CSKYISelLowering.cpp
   CSKYMCInstLower.cpp
   CSKYRegisterInfo.cpp
+  CSKYSelectionDAGInfo.cpp
   CSKYSubtarget.cpp
   CSKYTargetMachine.cpp
   CSKYTargetObjectFile.cpp

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

@@ -1117,33 +1117,6 @@ SDValue CSKYTargetLowering::getTargetNode(ConstantPoolSDNode *N, SDLoc DL,
                                    N->getOffset(), Flags);
 }
 
-const char *CSKYTargetLowering::getTargetNodeName(unsigned Opcode) const {
-  switch (Opcode) {
-  default:
-    llvm_unreachable("unknown CSKYISD node");
-  case CSKYISD::NIE:
-    return "CSKYISD::NIE";
-  case CSKYISD::NIR:
-    return "CSKYISD::NIR";
-  case CSKYISD::RET:
-    return "CSKYISD::RET";
-  case CSKYISD::CALL:
-    return "CSKYISD::CALL";
-  case CSKYISD::CALLReg:
-    return "CSKYISD::CALLReg";
-  case CSKYISD::TAIL:
-    return "CSKYISD::TAIL";
-  case CSKYISD::TAILReg:
-    return "CSKYISD::TAILReg";
-  case CSKYISD::LOAD_ADDR:
-    return "CSKYISD::LOAD_ADDR";
-  case CSKYISD::BITCAST_TO_LOHI:
-    return "CSKYISD::BITCAST_TO_LOHI";
-  case CSKYISD::BITCAST_FROM_LOHI:
-    return "CSKYISD::BITCAST_FROM_LOHI";
-  }
-}
-
 SDValue CSKYTargetLowering::LowerGlobalAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   SDLoc DL(Op);

llvm/lib/Target/CSKY/CSKYISelLowering.h

@@ -14,6 +14,7 @@
 #ifndef LLVM_LIB_TARGET_CSKY_CSKYISELLOWERING_H
 #define LLVM_LIB_TARGET_CSKY_CSKYISELLOWERING_H
 
+#include "CSKYSelectionDAGInfo.h"
 #include "MCTargetDesc/CSKYBaseInfo.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/TargetLowering.h"
@@ -21,24 +22,6 @@
 namespace llvm {
 class CSKYSubtarget;
 
-namespace CSKYISD {
-enum NodeType : unsigned {
-  FIRST_NUMBER = ISD::BUILTIN_OP_END,
-  NIE,
-  NIR,
-  RET,
-  CALL,
-  CALLReg,
-  TAIL,
-  TAILReg,
-  LOAD_ADDR,
-  // i32, i32 <-- f64
-  BITCAST_TO_LOHI,
-  // f64 < -- i32, i32
-  BITCAST_FROM_LOHI,
-};
-}
-
 class CSKYTargetLowering : public TargetLowering {
   const CSKYSubtarget &Subtarget;
 
@@ -71,8 +54,6 @@ private:
   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;
 
-  const char *getTargetNodeName(unsigned Opcode) const override;
-
   /// If a physical register, this returns the register that receives the
   /// exception address on entry to an EH pad.
   Register

llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.cpp

@@ -0,0 +1,19 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "CSKYSelectionDAGInfo.h"
+
+#define GET_SDNODE_DESC
+#include "CSKYGenSDNodeInfo.inc"
+
+using namespace llvm;
+
+CSKYSelectionDAGInfo::CSKYSelectionDAGInfo()
+    : SelectionDAGGenTargetInfo(CSKYGenSDNodeInfo) {}
+
+CSKYSelectionDAGInfo::~CSKYSelectionDAGInfo() = default;

llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.h

@@ -0,0 +1,28 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CSKY_CSKYSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_CSKY_CSKYSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+#define GET_SDNODE_ENUM
+#include "CSKYGenSDNodeInfo.inc"
+
+namespace llvm {
+
+class CSKYSelectionDAGInfo : public SelectionDAGGenTargetInfo {
+public:
+  CSKYSelectionDAGInfo();
+
+  ~CSKYSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_CSKY_CSKYSELECTIONDAGINFO_H

llvm/lib/Target/CSKY/CSKYSubtarget.cpp

@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "CSKYSubtarget.h"
+#include "CSKYSelectionDAGInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 
 using namespace llvm;
@@ -91,7 +92,15 @@ CSKYSubtarget::CSKYSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
                              StringRef FS, const TargetMachine &TM)
     : CSKYGenSubtargetInfo(TT, CPU, TuneCPU, FS),
       FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS)),
-      InstrInfo(*this), RegInfo(), TLInfo(TM, *this) {}
+      InstrInfo(*this), RegInfo(), TLInfo(TM, *this) {
+  TSInfo = std::make_unique<CSKYSelectionDAGInfo>();
+}
+
+CSKYSubtarget::~CSKYSubtarget() = default;
+
+const SelectionDAGTargetInfo *CSKYSubtarget::getSelectionDAGInfo() const {
+  return TSInfo.get();
+}
 
 bool CSKYSubtarget::useHardFloatABI() const {
   auto FloatABI = getTargetLowering()->getTargetMachine().Options.FloatABIType;

llvm/lib/Target/CSKY/CSKYSubtarget.h

@@ -17,7 +17,6 @@
 #include "CSKYISelLowering.h"
 #include "CSKYInstrInfo.h"
 #include "CSKYRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
@@ -34,7 +33,7 @@ class CSKYSubtarget : public CSKYGenSubtargetInfo {
   CSKYInstrInfo InstrInfo;
   CSKYRegisterInfo RegInfo;
   CSKYTargetLowering TLInfo;
-  SelectionDAGTargetInfo TSInfo;
+  std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
 
   enum CSKYProcFamilyEnum {
     Others,
@@ -112,6 +111,8 @@ public:
   CSKYSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
                 StringRef FS, const TargetMachine &TM);
 
+  ~CSKYSubtarget() override;
+
   const CSKYFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
@@ -120,9 +121,8 @@ public:
   const CSKYTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
-  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
-    return &TSInfo;
-  }
+
+  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.

llvm/lib/Target/Lanai/CMakeLists.txt

@@ -10,6 +10,7 @@ tablegen(LLVM LanaiGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM LanaiGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM LanaiGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM LanaiGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM LanaiGenSDNodeInfo.inc -gen-sd-node-info)
 tablegen(LLVM LanaiGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(LanaiCommonTableGen)

llvm/lib/Target/Lanai/LanaiISelLowering.cpp

@@ -1087,37 +1087,6 @@ SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
   return FrameAddr;
 }
 
-const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
-  switch (Opcode) {
-  case LanaiISD::ADJDYNALLOC:
-    return "LanaiISD::ADJDYNALLOC";
-  case LanaiISD::RET_GLUE:
-    return "LanaiISD::RET_GLUE";
-  case LanaiISD::CALL:
-    return "LanaiISD::CALL";
-  case LanaiISD::SELECT_CC:
-    return "LanaiISD::SELECT_CC";
-  case LanaiISD::SETCC:
-    return "LanaiISD::SETCC";
-  case LanaiISD::SUBBF:
-    return "LanaiISD::SUBBF";
-  case LanaiISD::SET_FLAG:
-    return "LanaiISD::SET_FLAG";
-  case LanaiISD::BR_CC:
-    return "LanaiISD::BR_CC";
-  case LanaiISD::Wrapper:
-    return "LanaiISD::Wrapper";
-  case LanaiISD::HI:
-    return "LanaiISD::HI";
-  case LanaiISD::LO:
-    return "LanaiISD::LO";
-  case LanaiISD::SMALL:
-    return "LanaiISD::SMALL";
-  default:
-    return nullptr;
-  }
-}
-
 SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
                                                SelectionDAG &DAG) const {
   SDLoc DL(Op);

llvm/lib/Target/Lanai/LanaiISelLowering.h

@@ -20,47 +20,6 @@
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
-namespace LanaiISD {
-enum {
-  FIRST_NUMBER = ISD::BUILTIN_OP_END,
-
-  ADJDYNALLOC,
-
-  // Return with a glue operand. Operand 0 is the chain operand.
-  RET_GLUE,
-
-  // CALL - These operations represent an abstract call instruction, which
-  // includes a bunch of information.
-  CALL,
-
-  // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
-  // is condition code and operand 4 is flag operand.
-  SELECT_CC,
-
-  // SETCC - Store the conditional code to a register.
-  SETCC,
-
-  // SET_FLAG - Set flag compare.
-  SET_FLAG,
-
-  // SUBBF - Subtract with borrow that sets flags.
-  SUBBF,
-
-  // BR_CC - Used to glue together a conditional branch and comparison
-  BR_CC,
-
-  // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
-  // and TargetGlobalAddress.
-  Wrapper,
-
-  // Get the Higher/Lower 16 bits from a 32-bit immediate.
-  HI,
-  LO,
-
-  // Small 21-bit immediate in global memory.
-  SMALL
-};
-} // namespace LanaiISD
 
 class LanaiSubtarget;
 
@@ -71,10 +30,6 @@ public:
   // LowerOperation - Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-  // getTargetNodeName - This method returns the name of a target specific
-  // DAG node.
-  const char *getTargetNodeName(unsigned Opcode) const override;
-
   SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp

@@ -12,9 +12,15 @@
 
 #include "LanaiSelectionDAGInfo.h"
 
+#define GET_SDNODE_DESC
+#include "LanaiGenSDNodeInfo.inc"
+
 #define DEBUG_TYPE "lanai-selectiondag-info"
 
-namespace llvm {
+using namespace llvm;
+
+LanaiSelectionDAGInfo::LanaiSelectionDAGInfo()
+    : SelectionDAGGenTargetInfo(LanaiGenSDNodeInfo) {}
 
 SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy(
     SelectionDAG & /*DAG*/, const SDLoc & /*dl*/, SDValue /*Chain*/,
@@ -28,5 +34,3 @@ SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy(
 
   return SDValue();
 }
-
-} // namespace llvm

llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h

@@ -16,11 +16,14 @@
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
+#define GET_SDNODE_ENUM
+#include "LanaiGenSDNodeInfo.inc"
+
 namespace llvm {
 
-class LanaiSelectionDAGInfo : public SelectionDAGTargetInfo {
+class LanaiSelectionDAGInfo : public SelectionDAGGenTargetInfo {
 public:
-  LanaiSelectionDAGInfo() = default;
+  LanaiSelectionDAGInfo();
 
   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
                                   SDValue Chain, SDValue Dst, SDValue Src,