From 93311617bf7eccc389643cf93ed00a8ad2e30ed2 Mon Sep 17 00:00:00 2001 From: vangthao95 Date: Wed, 25 Mar 2026 14:35:21 -0700 Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for s_memrealtime (#188311) --- llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 3 +++ .../GlobalISel/regbankselect-amdgcn.s.memrealtime.mir | 3 +-- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll | 9 ++++++--- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index 483007069744..81d462a2ffd9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1463,6 +1463,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Any({{S32}, {{Sgpr32}, {}}}) .Any({{S64}, {{Sgpr64}, {}}}); + addRulesForIOpcs({amdgcn_s_memrealtime}, Standard) + .Uni(S64, {{Sgpr64}, {IntrId}}); + addRulesForIOpcs({amdgcn_groupstaticsize, amdgcn_pops_exiting_wave_id, amdgcn_reloc_constant}, Standard) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir index a2ec76a4950d..d7c82f50cd2e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: memrealtime diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll index 819e50746eb8..8473754b1c80 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll @@ -1,7 +1,10 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s -; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s +; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR-SDAG %s +; RUN: not llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR-GISEL %s -; ERR: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.s.memrealtime +; ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.s.memrealtime +; ERR-GISEL: LLVM ERROR: cannot select: %{{[0-9]+}}:sreg_64(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memrealtime) declare i64 @llvm.amdgcn.s.memrealtime() #0