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This commit is contained in:
Aaditya 2025-08-13 11:28:13 +05:30
parent 4277c1370b
commit 9362371fdc
1 changed files with 11 additions and 9 deletions
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20
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -5236,18 +5236,22 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
if (isSGPR) {
switch (Opc) {
case AMDGPU::S_MIN_U32:
case AMDGPU::V_CMP_LT_U64_e64: /*umin*/
case AMDGPU::S_MIN_I32:
case AMDGPU::V_CMP_LT_I64_e64: /*min*/
case AMDGPU::S_MAX_U32:
case AMDGPU::V_CMP_GT_U64_e64: /*umax*/
case AMDGPU::S_MAX_I32:
case AMDGPU::V_CMP_GT_I64_e64: /*max*/
case AMDGPU::S_AND_B32:
case AMDGPU::S_OR_B32: {
// Idempotent operations.
unsigned movOpc = is32BitOpc ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
BuildMI(BB, MI, DL, TII->get(movOpc), DstReg).addReg(SrcReg);
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
RetBB = &BB;
break;
}
case AMDGPU::V_CMP_LT_U64_e64: // umin
case AMDGPU::V_CMP_LT_I64_e64: // min
case AMDGPU::V_CMP_GT_U64_e64: // umax
case AMDGPU::V_CMP_GT_I64_e64: { // max
// Idempotent operations.
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B64), DstReg).addReg(SrcReg);
RetBB = &BB;
break;
}
@ -5441,9 +5445,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
Register LaneMaskReg = MRI.createVirtualRegister(WaveMaskRegClass);
Register ComparisonResultReg =
MRI.createVirtualRegister(WaveMaskRegClass);
const TargetRegisterClass *VregClass =
ST.needsAlignedVGPRs() ? &AMDGPU::VReg_64_Align2RegClass
: &AMDGPU::VReg_64RegClass;
const TargetRegisterClass *VregClass = TRI->getVGPR64Class();
const TargetRegisterClass *VSubRegClass =
TRI->getSubRegisterClass(VregClass, AMDGPU::sub0);
Register AccumulatorVReg = MRI.createVirtualRegister(VregClass);