From 93d7583f4f2d267c66785c2543509d190d56d2ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mirko=20Brku=C5=A1anin?= Date: Fri, 20 Mar 2026 17:04:17 +0100 Subject: [PATCH] [AMDGPU] Update features for gfx1170 (#186107) - Enable `NoF16PseudoScalarTransInlineConstants` for 11.7. - Add test for `RequiredExportPriority`, one of the differences between 11.5 and 11.7. --- llvm/lib/Target/AMDGPU/AMDGPU.td | 12 +- llvm/lib/Target/AMDGPU/GCNSubtarget.h | 6 - .../AMDGPU/pseudo-scalar-transcendental.mir | 3 +- .../AMDGPU/required-export-priority.ll | 509 +++++++++++------- .../AMDGPU/required-export-priority.mir | 95 ++++ 5 files changed, 431 insertions(+), 194 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 6be61d1d0829..20e811503256 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1065,6 +1065,11 @@ defm PseudoScalarTrans : AMDGPUSubtargetFeature<"pseudo-scalar-trans", "Has Pseudo Scalar Transcendental instructions" >; +defm NoF16PseudoScalarTransInlineConstants : AMDGPUSubtargetFeature<"no-f16-pseudo-scalar-trans-inline-constants", + "Inline constants are not supported for F16 pseudo scalar transcendentals", + /*GenPredicate=*/0 +>; + defm RestrictedSOffset : AMDGPUSubtargetFeature<"restricted-soffset", "Has restricted SOffset (immediate not supported)." >; @@ -1966,7 +1971,8 @@ def FeatureISAVersion11_7_0 : FeatureSet< FeatureSWMMACGfx1200Insts, FeatureIEEEMinimumMaximumInsts, FeatureMinimum3Maximum3F32, - FeatureMinimum3Maximum3F16])>; + FeatureMinimum3Maximum3F16, + FeatureNoF16PseudoScalarTransInlineConstants])>; def FeatureISAVersion12 : FeatureSet< [FeatureGFX12, @@ -2018,7 +2024,8 @@ def FeatureISAVersion12 : FeatureSet< FeatureQsadInsts, FeatureCvtNormInsts, FeatureCvtPkNormVOP2Insts, - FeatureCvtPkNormVOP3Insts + FeatureCvtPkNormVOP3Insts, + FeatureNoF16PseudoScalarTransInlineConstants, ]>; def FeatureISAVersion12_50_Common : FeatureSet< @@ -2097,6 +2104,7 @@ def FeatureISAVersion12_50_Common : FeatureSet< FeatureClusters, FeatureD16Writes32BitVgpr, FeatureMcastLoadInsts, + FeatureNoF16PseudoScalarTransInlineConstants, ]>; def FeatureISAVersion12_50 : FeatureSet< diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index ea5c308a38f9..fe5fbbe04fb6 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -622,12 +622,6 @@ public: /// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively. bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; } - /// \returns true if inline constants are not supported for F16 pseudo - /// scalar transcendentals. - bool hasNoF16PseudoScalarTransInlineConstants() const { - return getGeneration() == GFX12; - } - /// \returns true if the target has packed f32 instructions that only read 32 /// bits from a scalar operand (SGPR or literal) and replicates the bits to /// both channels. diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir index 17bed38bd046..19681a4346a1 100644 --- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir +++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1170 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s +# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s # Do not use inline constants for f16 pseudo scalar transcendentals. # But allow literal constants. diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll index 962cd28693b9..007950478f86 100644 --- a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll +++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll @@ -1,88 +1,134 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX11 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX1150 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX11 %s define amdgpu_ps void @test_export_zeroes_f32() #0 { -; GCN-LABEL: test_export_zeroes_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: exp mrt0, off, off, off, off -; GCN-NEXT: exp mrt0, off, off, off, off done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_zeroes_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: exp mrt0, off, off, off, off +; GFX11-NEXT: exp mrt0, off, off, off, off done +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_zeroes_f32: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: v_mov_b32_e32 v0, 0 +; GFX1150-NEXT: exp mrt0, off, off, off, off +; GFX1150-NEXT: exp mrt0, off, off, off, off done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 true, i1 false) ret void } define amdgpu_ps void @test_export_en_src0_f32() #0 { -; GCN-LABEL: test_export_en_src0_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: v_mov_b32_e32 v0, 4.0 -; GCN-NEXT: v_mov_b32_e32 v1, 0.5 -; GCN-NEXT: v_mov_b32_e32 v2, 2.0 -; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0, v3, off, off, off done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_en_src0_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, 4.0 +; GFX11-NEXT: v_mov_b32_e32 v1, 0.5 +; GFX11-NEXT: v_mov_b32_e32 v2, 2.0 +; GFX11-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX11-NEXT: exp mrt0, v3, off, off, off done +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_en_src0_f32: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: v_mov_b32_e32 v0, 4.0 +; GFX1150-NEXT: v_mov_b32_e32 v1, 0.5 +; GFX1150-NEXT: v_mov_b32_e32 v2, 2.0 +; GFX1150-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1150-NEXT: exp mrt0, v3, off, off, off done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void } define amdgpu_gs void @test_export_gs() #0 { -; GCN-LABEL: test_export_gs: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: v_mov_b32_e32 v0, 4.0 -; GCN-NEXT: v_mov_b32_e32 v1, 0.5 -; GCN-NEXT: v_mov_b32_e32 v2, 2.0 -; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0, off, v2, off, off done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_gs: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, 4.0 +; GFX11-NEXT: v_mov_b32_e32 v1, 0.5 +; GFX11-NEXT: v_mov_b32_e32 v2, 2.0 +; GFX11-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX11-NEXT: exp mrt0, off, v2, off, off done +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_gs: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: v_mov_b32_e32 v0, 4.0 +; GFX1150-NEXT: v_mov_b32_e32 v1, 0.5 +; GFX1150-NEXT: v_mov_b32_e32 v2, 2.0 +; GFX1150-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1150-NEXT: exp mrt0, off, v2, off, off done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void } define amdgpu_hs void @test_export_hs() #0 { -; GCN-LABEL: test_export_hs: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: v_mov_b32_e32 v0, 4.0 -; GCN-NEXT: v_mov_b32_e32 v1, 0.5 -; GCN-NEXT: v_mov_b32_e32 v2, 2.0 -; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0, off, v2, off, off done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_hs: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, 4.0 +; GFX11-NEXT: v_mov_b32_e32 v1, 0.5 +; GFX11-NEXT: v_mov_b32_e32 v2, 2.0 +; GFX11-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX11-NEXT: exp mrt0, off, v2, off, off done +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_hs: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: v_mov_b32_e32 v0, 4.0 +; GFX1150-NEXT: v_mov_b32_e32 v1, 0.5 +; GFX1150-NEXT: v_mov_b32_e32 v2, 2.0 +; GFX1150-NEXT: v_mov_b32_e32 v3, 1.0 +; GFX1150-NEXT: exp mrt0, off, v2, off, off done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void } define amdgpu_gfx void @test_export_gfx(float %v) #0 { -; GCN-LABEL: test_export_gfx: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v1, 4.0 -; GCN-NEXT: v_mov_b32_e32 v2, 0.5 -; GCN-NEXT: v_mov_b32_e32 v3, 2.0 -; GCN-NEXT: exp mrt0, off, v3, off, off done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_waitcnt_expcnt null, 0x0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_waitcnt expcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] +; GFX11-LABEL: test_export_gfx: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v1, 4.0 +; GFX11-NEXT: v_mov_b32_e32 v2, 0.5 +; GFX11-NEXT: v_mov_b32_e32 v3, 2.0 +; GFX11-NEXT: exp mrt0, off, v3, off, off done +; GFX11-NEXT: s_waitcnt expcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1150-LABEL: test_export_gfx: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1150-NEXT: v_mov_b32_e32 v1, 4.0 +; GFX1150-NEXT: v_mov_b32_e32 v2, 0.5 +; GFX1150-NEXT: v_mov_b32_e32 v3, 2.0 +; GFX1150-NEXT: exp mrt0, off, v3, off, off done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_waitcnt_expcnt null, 0x0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_waitcnt expcnt(0) +; GFX1150-NEXT: s_setpc_b64 s[30:31] call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float %v, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void } @@ -129,21 +175,31 @@ define amdgpu_ps void @test_no_export_ps(float %v) #0 { } define amdgpu_ps void @test_if_export_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { -; GCN-LABEL: test_if_export_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_mov_b32 s0, exec_lo -; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 -; GCN-NEXT: s_cbranch_execz .LBB9_2 -; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0, v1, v2, v3, v4 -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_waitcnt_expcnt null, 0x0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: .LBB9_2: ; %end -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_if_export_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB9_2 +; GFX11-NEXT: ; %bb.1: ; %exp +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 +; GFX11-NEXT: .LBB9_2: ; %end +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_if_export_f32: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_mov_b32 s0, exec_lo +; GFX1150-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX1150-NEXT: s_cbranch_execz .LBB9_2 +; GFX1150-NEXT: ; %bb.1: ; %exp +; GFX1150-NEXT: exp mrt0, v1, v2, v3, v4 +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_waitcnt_expcnt null, 0x0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: .LBB9_2: ; %end +; GFX1150-NEXT: s_endpgm %cc = icmp eq i32 %flag, 0 br i1 %cc, label %end, label %exp @@ -156,21 +212,31 @@ end: } define amdgpu_ps void @test_if_export_vm_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { -; GCN-LABEL: test_if_export_vm_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_mov_b32 s0, exec_lo -; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 -; GCN-NEXT: s_cbranch_execz .LBB10_2 -; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0, v1, v2, v3, v4 -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_waitcnt_expcnt null, 0x0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: .LBB10_2: ; %end -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_if_export_vm_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB10_2 +; GFX11-NEXT: ; %bb.1: ; %exp +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 +; GFX11-NEXT: .LBB10_2: ; %end +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_if_export_vm_f32: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_mov_b32 s0, exec_lo +; GFX1150-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX1150-NEXT: s_cbranch_execz .LBB10_2 +; GFX1150-NEXT: ; %bb.1: ; %exp +; GFX1150-NEXT: exp mrt0, v1, v2, v3, v4 +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_waitcnt_expcnt null, 0x0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: .LBB10_2: ; %end +; GFX1150-NEXT: s_endpgm %cc = icmp eq i32 %flag, 0 br i1 %cc, label %end, label %exp @@ -183,21 +249,31 @@ end: } define amdgpu_ps void @test_if_export_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { -; GCN-LABEL: test_if_export_done_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_mov_b32 s0, exec_lo -; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 -; GCN-NEXT: s_cbranch_execz .LBB11_2 -; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0, v1, v2, v3, v4 done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_waitcnt_expcnt null, 0x0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: .LBB11_2: ; %end -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_if_export_done_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB11_2 +; GFX11-NEXT: ; %bb.1: ; %exp +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 done +; GFX11-NEXT: .LBB11_2: ; %end +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_if_export_done_f32: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_mov_b32 s0, exec_lo +; GFX1150-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX1150-NEXT: s_cbranch_execz .LBB11_2 +; GFX1150-NEXT: ; %bb.1: ; %exp +; GFX1150-NEXT: exp mrt0, v1, v2, v3, v4 done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_waitcnt_expcnt null, 0x0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: .LBB11_2: ; %end +; GFX1150-NEXT: s_endpgm %cc = icmp eq i32 %flag, 0 br i1 %cc, label %end, label %exp @@ -210,21 +286,31 @@ end: } define amdgpu_ps void @test_if_export_vm_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { -; GCN-LABEL: test_if_export_vm_done_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_mov_b32 s0, exec_lo -; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 -; GCN-NEXT: s_cbranch_execz .LBB12_2 -; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0, v1, v2, v3, v4 done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_waitcnt_expcnt null, 0x0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: .LBB12_2: ; %end -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_if_export_vm_done_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB12_2 +; GFX11-NEXT: ; %bb.1: ; %exp +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 done +; GFX11-NEXT: .LBB12_2: ; %end +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_if_export_vm_done_f32: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_mov_b32 s0, exec_lo +; GFX1150-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX1150-NEXT: s_cbranch_execz .LBB12_2 +; GFX1150-NEXT: ; %bb.1: ; %exp +; GFX1150-NEXT: exp mrt0, v1, v2, v3, v4 done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_waitcnt_expcnt null, 0x0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: .LBB12_2: ; %end +; GFX1150-NEXT: s_endpgm %cc = icmp eq i32 %flag, 0 br i1 %cc, label %end, label %exp @@ -237,21 +323,33 @@ end: } define amdgpu_ps void @test_export_pos_before_param_across_load(i32 %idx) #0 { -; GCN-LABEL: test_export_pos_before_param_across_load: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_mov_b32_e32 v2, 1.0 -; GCN-NEXT: v_mov_b32_e32 v3, 0.5 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: exp pos0, v1, v1, v1, v0 done -; GCN-NEXT: exp invalid_target_32, v2, v2, v2, v2 -; GCN-NEXT: exp invalid_target_33, v2, v2, v2, v3 -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_pos_before_param_across_load: +; GFX11: ; %bb.0: +; GFX11-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: v_mov_b32_e32 v2, 1.0 +; GFX11-NEXT: v_mov_b32_e32 v3, 0.5 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: exp pos0, v1, v1, v1, v0 done +; GFX11-NEXT: exp invalid_target_32, v2, v2, v2, v2 +; GFX11-NEXT: exp invalid_target_33, v2, v2, v2, v3 +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_pos_before_param_across_load: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen +; GFX1150-NEXT: v_mov_b32_e32 v1, 0 +; GFX1150-NEXT: v_mov_b32_e32 v2, 1.0 +; GFX1150-NEXT: v_mov_b32_e32 v3, 0.5 +; GFX1150-NEXT: s_waitcnt vmcnt(0) +; GFX1150-NEXT: exp pos0, v1, v1, v1, v0 done +; GFX1150-NEXT: exp invalid_target_32, v2, v2, v2, v2 +; GFX1150-NEXT: exp invalid_target_33, v2, v2, v2, v3 +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float 1.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float 1.0, float 1.0, float 1.0, float 0.5, i1 false, i1 false) %load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx, i32 0, i32 0) @@ -260,30 +358,46 @@ define amdgpu_ps void @test_export_pos_before_param_across_load(i32 %idx) #0 { } define amdgpu_ps void @test_export_across_store_load(i32 %idx, float %v) #0 { -; GCN-LABEL: test_export_across_store_load: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: v_mov_b32_e32 v2, 0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GCN-NEXT: v_cndmask_b32_e32 v0, 16, v2, vcc_lo -; GCN-NEXT: v_mov_b32_e32 v2, 0 -; GCN-NEXT: scratch_store_b32 v0, v1, off -; GCN-NEXT: scratch_load_b32 v0, off, off -; GCN-NEXT: v_mov_b32_e32 v1, 1.0 -; GCN-NEXT: exp pos0, v2, v2, v2, v1 done -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_waitcnt_expcnt null, 0x0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: exp invalid_target_32, v0, v2, v1, v2 -; GCN-NEXT: exp invalid_target_33, v0, v2, v1, v2 -; GCN-NEXT: s_setprio 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_nop 0 -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_across_store_load: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e32 v0, 16, v2, vcc_lo +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: scratch_store_b32 v0, v1, off +; GFX11-NEXT: scratch_load_b32 v0, off, off +; GFX11-NEXT: v_mov_b32_e32 v1, 1.0 +; GFX11-NEXT: exp pos0, v2, v2, v2, v1 done +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: exp invalid_target_32, v0, v2, v1, v2 +; GFX11-NEXT: exp invalid_target_33, v0, v2, v1, v2 +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_across_store_load: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: v_mov_b32_e32 v2, 0 +; GFX1150-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1150-NEXT: v_cndmask_b32_e32 v0, 16, v2, vcc_lo +; GFX1150-NEXT: v_mov_b32_e32 v2, 0 +; GFX1150-NEXT: scratch_store_b32 v0, v1, off +; GFX1150-NEXT: scratch_load_b32 v0, off, off +; GFX1150-NEXT: v_mov_b32_e32 v1, 1.0 +; GFX1150-NEXT: exp pos0, v2, v2, v2, v1 done +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_waitcnt_expcnt null, 0x0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_waitcnt vmcnt(0) +; GFX1150-NEXT: exp invalid_target_32, v0, v2, v1, v2 +; GFX1150-NEXT: exp invalid_target_33, v0, v2, v1, v2 +; GFX1150-NEXT: s_setprio 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_nop 0 +; GFX1150-NEXT: s_endpgm %data0 = alloca <4 x float>, align 8, addrspace(5) %data1 = alloca <4 x float>, align 8, addrspace(5) %cmp = icmp eq i32 %idx, 1 @@ -297,37 +411,62 @@ define amdgpu_ps void @test_export_across_store_load(i32 %idx, float %v) #0 { } define amdgpu_ps void @test_export_in_callee(float %v) #0 { -; GCN-LABEL: test_export_in_callee: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_getpc_b64 s[0:1] -; GCN-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12 -; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 -; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_in_callee: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_getpc_b64 s[0:1] +; GFX11-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4 +; GFX11-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12 +; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_mov_b32 s32, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_in_callee: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_getpc_b64 s[0:1] +; GFX1150-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4 +; GFX1150-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12 +; GFX1150-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX1150-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX1150-NEXT: s_mov_b32 s32, 0 +; GFX1150-NEXT: s_waitcnt lgkmcnt(0) +; GFX1150-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX1150-NEXT: s_endpgm %x = fadd float %v, 1.0 call amdgpu_gfx void @test_export_gfx(float %x) ret void } define amdgpu_ps void @test_export_in_callee_prio(float %v) #0 { -; GCN-LABEL: test_export_in_callee_prio: -; GCN: ; %bb.0: -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 -; GCN-NEXT: s_setprio 2 -; GCN-NEXT: s_getpc_b64 s[0:1] -; GCN-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12 -; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GCN-NEXT: s_endpgm +; GFX11-LABEL: test_export_in_callee_prio: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s32, 0 +; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX11-NEXT: s_setprio 0 +; GFX11-NEXT: s_getpc_b64 s[0:1] +; GFX11-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4 +; GFX11-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: s_endpgm +; +; GFX1150-LABEL: test_export_in_callee_prio: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_mov_b32 s32, 0 +; GFX1150-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX1150-NEXT: s_setprio 2 +; GFX1150-NEXT: s_getpc_b64 s[0:1] +; GFX1150-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4 +; GFX1150-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12 +; GFX1150-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX1150-NEXT: s_waitcnt lgkmcnt(0) +; GFX1150-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX1150-NEXT: s_endpgm %x = fadd float %v, 1.0 call void @llvm.amdgcn.s.setprio(i16 0) call amdgpu_gfx void @test_export_gfx(float %x) diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.mir b/llvm/test/CodeGen/AMDGPU/required-export-priority.mir index 392519171cd7..70241033f35a 100644 --- a/llvm/test/CodeGen/AMDGPU/required-export-priority.mir +++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GFX11 %s # RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GFX1150 %s # RUN: llc -mtriple=amdgcn -mcpu=gfx11-generic -run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GFX1150 %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GFX11 %s --- | define amdgpu_ps void @end_of_shader() { @@ -37,6 +39,12 @@ liveins: body: | bb.0: liveins: $vgpr0 + ; GFX11-LABEL: name: end_of_shader + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: end_of_shader ; GFX1150: liveins: $vgpr0 ; GFX1150-NEXT: {{ $}} @@ -58,6 +66,12 @@ liveins: body: | bb.0: liveins: $vgpr0 + ; GFX11-LABEL: name: end_of_shader_return_to_epilogue + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: SI_RETURN_TO_EPILOG $vgpr0 + ; ; GFX1150-LABEL: name: end_of_shader_return_to_epilogue ; GFX1150: liveins: $vgpr0 ; GFX1150-NEXT: {{ $}} @@ -79,6 +93,16 @@ tracksRegLiveness: true liveins: - { reg: '$vgpr0' } body: | + ; GFX11-LABEL: name: end_of_block + ; GFX11: bb.0: + ; GFX11-NEXT: successors: %bb.1(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.1: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: end_of_block ; GFX1150: bb.0: ; GFX1150-NEXT: successors: %bb.1(0x80000000) @@ -108,6 +132,20 @@ tracksRegLiveness: true liveins: - { reg: '$vgpr0' } body: | + ; GFX11-LABEL: name: start_of_block + ; GFX11: bb.0: + ; GFX11-NEXT: successors: %bb.1(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.1: + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: start_of_block ; GFX1150: bb.0: ; GFX1150-NEXT: successors: %bb.1(0x80000000) @@ -147,6 +185,14 @@ liveins: body: | bb.0: liveins: $vgpr0 + ; GFX11-LABEL: name: block_of_exports + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP 2, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: block_of_exports ; GFX1150: liveins: $vgpr0 ; GFX1150-NEXT: {{ $}} @@ -172,6 +218,16 @@ liveins: body: | bb.0: liveins: $vgpr0 + ; GFX11-LABEL: name: sparse_exports + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP 2, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: $vgpr0 = V_AND_B32_e32 1, $vgpr0, implicit $exec + ; GFX11-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: $vgpr0 = V_OR_B32_e32 2, $vgpr0, implicit $exec + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: sparse_exports ; GFX1150: liveins: $vgpr0 ; GFX1150-NEXT: {{ $}} @@ -209,6 +265,36 @@ tracksRegLiveness: true liveins: - { reg: '$vgpr0' } body: | + ; GFX11-LABEL: name: existing_setprio_1 + ; GFX11: bb.0: + ; GFX11-NEXT: successors: %bb.1(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $vgpr0 = V_AND_B32_e32 1, $vgpr0, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.1: + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: S_SETPRIO 3 + ; GFX11-NEXT: $vgpr0 = V_OR_B32_e32 2, $vgpr0, implicit $exec + ; GFX11-NEXT: S_SETPRIO 0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: S_SETPRIO 1 + ; GFX11-NEXT: $vgpr0 = V_OR_B32_e32 3, $vgpr0, implicit $exec + ; GFX11-NEXT: S_SETPRIO 0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: existing_setprio_1 ; GFX1150: bb.0: ; GFX1150-NEXT: successors: %bb.1(0x80000000) @@ -273,6 +359,15 @@ liveins: body: | bb.0: liveins: $vgpr0 + ; GFX11-LABEL: name: existing_setprio_2 + ; GFX11: liveins: $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: S_SETPRIO 3 + ; GFX11-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec + ; GFX11-NEXT: S_SETPRIO 3 + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX1150-LABEL: name: existing_setprio_2 ; GFX1150: liveins: $vgpr0 ; GFX1150-NEXT: {{ $}}