[AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16/permlanex16 (#187906)
Add RegBankLegalize rules for the amdgcn_permlane16 and amdgcn_permlanex16 intrinsics. Both intrinsics are sources of divergence, so only the divergent case is needed: result, old, and src0 map to VGPR, while src1 and src2 are SGPR with ReadFirstLane if divergent. Update the GISEL RUN lines in llvm.amdgcn.permlane.ll and permlane16_opsel.ll to use -new-reg-bank-select, and regenerate check lines. The v8i16 test cases now produce identical SDAG/GISEL output so their checks are unified.
This commit is contained in:
Anshil Gandhi
GitHub
parent
b32b31e6a7
commit
94239b3450
@ -1550,6 +1550,11 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
|
||||
{{VgprB32},
|
||||
{IntrId, SgprB32_ReadFirstLane, SgprB32_ReadFirstLane, VgprB32}});
|
||||
|
||||
addRulesForIOpcs({amdgcn_permlane16, amdgcn_permlanex16}, Standard)
|
||||
.Div(S32, {{Vgpr32},
|
||||
{IntrId, Vgpr32, Vgpr32, SgprB32_ReadFirstLane,
|
||||
SgprB32_ReadFirstLane, Imm, Imm}});
|
||||
|
||||
addRulesForIOpcs({amdgcn_wave_reduce_umax, amdgcn_wave_reduce_umin}, Standard)
|
||||
.Uni(S32, {{Sgpr32}, {IntrId, Sgpr32}})
|
||||
.Div(S32, {{Sgpr32ToVgprDst}, {IntrId, VgprB32}})
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
|
||||
; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
|
||||
; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
|
||||
; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
|
||||
; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
|
||||
; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
|
||||
|
||||
declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1)
|
||||
declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1)
|
||||
@ -9250,182 +9250,96 @@ define void @v_permlanex16_v7i32(ptr addrspace(1) %out, <7 x i32> %src0, i32 %sr
|
||||
}
|
||||
|
||||
define void @v_permlane16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %src1, i32 %src2) {
|
||||
; GFX10-SDAG-LABEL: v_permlane16_v8i16:
|
||||
; GFX10-SDAG: ; %bb.0:
|
||||
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-SDAG-NEXT: v_readfirstlane_b32 s4, v6
|
||||
; GFX10-SDAG-NEXT: v_readfirstlane_b32 s5, v7
|
||||
; GFX10-SDAG-NEXT: v_permlane16_b32 v5, v5, s4, s5
|
||||
; GFX10-SDAG-NEXT: v_permlane16_b32 v4, v4, s4, s5
|
||||
; GFX10-SDAG-NEXT: v_permlane16_b32 v3, v3, s4, s5
|
||||
; GFX10-SDAG-NEXT: v_permlane16_b32 v2, v2, s4, s5
|
||||
; GFX10-SDAG-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
|
||||
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX10-LABEL: v_permlane16_v8i16:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: v_readfirstlane_b32 s4, v6
|
||||
; GFX10-NEXT: v_readfirstlane_b32 s5, v7
|
||||
; GFX10-NEXT: v_permlane16_b32 v5, v5, s4, s5
|
||||
; GFX10-NEXT: v_permlane16_b32 v4, v4, s4, s5
|
||||
; GFX10-NEXT: v_permlane16_b32 v3, v3, s4, s5
|
||||
; GFX10-NEXT: v_permlane16_b32 v2, v2, s4, s5
|
||||
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-GISEL-LABEL: v_permlane16_v8i16:
|
||||
; GFX10-GISEL: ; %bb.0:
|
||||
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v6
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v7
|
||||
; GFX10-GISEL-NEXT: v_permlane16_b32 v2, v2, s4, s5
|
||||
; GFX10-GISEL-NEXT: v_permlane16_b32 v3, v3, s4, s5
|
||||
; GFX10-GISEL-NEXT: v_permlane16_b32 v4, v4, s4, s5
|
||||
; GFX10-GISEL-NEXT: v_permlane16_b32 v5, v5, s4, s5
|
||||
; GFX10-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
|
||||
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-LABEL: v_permlane16_v8i16:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX11-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-NEXT: v_permlane16_b32 v5, v5, s0, s1
|
||||
; GFX11-NEXT: v_permlane16_b32 v4, v4, s0, s1
|
||||
; GFX11-NEXT: v_permlane16_b32 v3, v3, s0, s1
|
||||
; GFX11-NEXT: v_permlane16_b32 v2, v2, s0, s1
|
||||
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-LABEL: v_permlane16_v8i16:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-SDAG-NEXT: v_permlane16_b32 v5, v5, s0, s1
|
||||
; GFX11-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
|
||||
; GFX11-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
|
||||
; GFX11-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
|
||||
; GFX11-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-LABEL: v_permlane16_v8i16:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
|
||||
; GFX11-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
|
||||
; GFX11-GISEL-NEXT: v_permlane16_b32 v4, v4, s0, s1
|
||||
; GFX11-GISEL-NEXT: v_permlane16_b32 v5, v5, s0, s1
|
||||
; GFX11-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-SDAG-LABEL: v_permlane16_v8i16:
|
||||
; GFX12-SDAG: ; %bb.0:
|
||||
; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
|
||||
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX12-SDAG-NEXT: v_permlane16_b32 v5, v5, s0, s1
|
||||
; GFX12-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
|
||||
; GFX12-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
|
||||
; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
|
||||
; GFX12-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-GISEL-LABEL: v_permlane16_v8i16:
|
||||
; GFX12-GISEL: ; %bb.0:
|
||||
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
|
||||
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
|
||||
; GFX12-GISEL-NEXT: v_permlane16_b32 v4, v4, s0, s1
|
||||
; GFX12-GISEL-NEXT: v_permlane16_b32 v5, v5, s0, s1
|
||||
; GFX12-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX12-LABEL: v_permlane16_v8i16:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX12-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
|
||||
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX12-NEXT: v_permlane16_b32 v5, v5, s0, s1
|
||||
; GFX12-NEXT: v_permlane16_b32 v4, v4, s0, s1
|
||||
; GFX12-NEXT: v_permlane16_b32 v3, v3, s0, s1
|
||||
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
|
||||
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
%v = call <8 x i16> @llvm.amdgcn.permlane16.v8i16(<8 x i16> %src0, <8 x i16> %src0, i32 %src1, i32 %src2, i1 false, i1 false)
|
||||
store <8 x i16> %v, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @v_permlanex16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %src1, i32 %src2) {
|
||||
; GFX10-SDAG-LABEL: v_permlanex16_v8i16:
|
||||
; GFX10-SDAG: ; %bb.0:
|
||||
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-SDAG-NEXT: v_readfirstlane_b32 s4, v6
|
||||
; GFX10-SDAG-NEXT: v_readfirstlane_b32 s5, v7
|
||||
; GFX10-SDAG-NEXT: v_permlanex16_b32 v5, v5, s4, s5
|
||||
; GFX10-SDAG-NEXT: v_permlanex16_b32 v4, v4, s4, s5
|
||||
; GFX10-SDAG-NEXT: v_permlanex16_b32 v3, v3, s4, s5
|
||||
; GFX10-SDAG-NEXT: v_permlanex16_b32 v2, v2, s4, s5
|
||||
; GFX10-SDAG-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
|
||||
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX10-LABEL: v_permlanex16_v8i16:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: v_readfirstlane_b32 s4, v6
|
||||
; GFX10-NEXT: v_readfirstlane_b32 s5, v7
|
||||
; GFX10-NEXT: v_permlanex16_b32 v5, v5, s4, s5
|
||||
; GFX10-NEXT: v_permlanex16_b32 v4, v4, s4, s5
|
||||
; GFX10-NEXT: v_permlanex16_b32 v3, v3, s4, s5
|
||||
; GFX10-NEXT: v_permlanex16_b32 v2, v2, s4, s5
|
||||
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX10-GISEL-LABEL: v_permlanex16_v8i16:
|
||||
; GFX10-GISEL: ; %bb.0:
|
||||
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v6
|
||||
; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v7
|
||||
; GFX10-GISEL-NEXT: v_permlanex16_b32 v2, v2, s4, s5
|
||||
; GFX10-GISEL-NEXT: v_permlanex16_b32 v3, v3, s4, s5
|
||||
; GFX10-GISEL-NEXT: v_permlanex16_b32 v4, v4, s4, s5
|
||||
; GFX10-GISEL-NEXT: v_permlanex16_b32 v5, v5, s4, s5
|
||||
; GFX10-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
|
||||
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX11-LABEL: v_permlanex16_v8i16:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX11-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-NEXT: v_permlanex16_b32 v5, v5, s0, s1
|
||||
; GFX11-NEXT: v_permlanex16_b32 v4, v4, s0, s1
|
||||
; GFX11-NEXT: v_permlanex16_b32 v3, v3, s0, s1
|
||||
; GFX11-NEXT: v_permlanex16_b32 v2, v2, s0, s1
|
||||
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-SDAG-LABEL: v_permlanex16_v8i16:
|
||||
; GFX11-SDAG: ; %bb.0:
|
||||
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-SDAG-NEXT: v_permlanex16_b32 v5, v5, s0, s1
|
||||
; GFX11-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
|
||||
; GFX11-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
|
||||
; GFX11-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
|
||||
; GFX11-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-GISEL-LABEL: v_permlanex16_v8i16:
|
||||
; GFX11-GISEL: ; %bb.0:
|
||||
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX11-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
|
||||
; GFX11-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
|
||||
; GFX11-GISEL-NEXT: v_permlanex16_b32 v4, v4, s0, s1
|
||||
; GFX11-GISEL-NEXT: v_permlanex16_b32 v5, v5, s0, s1
|
||||
; GFX11-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-SDAG-LABEL: v_permlanex16_v8i16:
|
||||
; GFX12-SDAG: ; %bb.0:
|
||||
; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
|
||||
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX12-SDAG-NEXT: v_permlanex16_b32 v5, v5, s0, s1
|
||||
; GFX12-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
|
||||
; GFX12-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
|
||||
; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
|
||||
; GFX12-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-GISEL-LABEL: v_permlanex16_v8i16:
|
||||
; GFX12-GISEL: ; %bb.0:
|
||||
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
|
||||
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
|
||||
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
|
||||
; GFX12-GISEL-NEXT: v_permlanex16_b32 v4, v4, s0, s1
|
||||
; GFX12-GISEL-NEXT: v_permlanex16_b32 v5, v5, s0, s1
|
||||
; GFX12-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX12-LABEL: v_permlanex16_v8i16:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: v_readfirstlane_b32 s0, v6
|
||||
; GFX12-NEXT: v_readfirstlane_b32 s1, v7
|
||||
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
|
||||
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; GFX12-NEXT: v_permlanex16_b32 v5, v5, s0, s1
|
||||
; GFX12-NEXT: v_permlanex16_b32 v4, v4, s0, s1
|
||||
; GFX12-NEXT: v_permlanex16_b32 v3, v3, s0, s1
|
||||
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
|
||||
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
%v = call <8 x i16> @llvm.amdgcn.permlanex16.v8i16(<8 x i16> %src0, <8 x i16> %src0, i32 %src1, i32 %src2, i1 false, i1 false)
|
||||
store <8 x i16> %v, ptr addrspace(1) %out
|
||||
ret void
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 --stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=SDAG,SDAG-GFX10 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 --stop-after=instruction-select < %s | FileCheck -check-prefixes=GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 --stop-after=instruction-select < %s | FileCheck -check-prefixes=GISEL %s
|
||||
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 --stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=SDAG,SDAG-GFX11 %s
|
||||
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 --stop-after=instruction-select < %s | FileCheck -check-prefixes=GISEL %s
|
||||
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 --stop-after=instruction-select < %s | FileCheck -check-prefixes=GISEL %s
|
||||
|
||||
declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1)
|
||||
declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user