AMDGPU: Select VGPR MFMAs by default (#159493)
AGPRs are undesirable since they are only usable by a handful instructions like loads, stores and mfmas and everything else requires copies to/from VGPRs. Using the AGPR form should be a measure of last resort if we must use more than 256 VGPRs.
This commit is contained in:
Matt Arsenault
GitHub
parent
9357c5906c
commit
9568772187
@ -37,7 +37,7 @@ static cl::opt<bool, true> MFMAVGPRFormOpt(
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"amdgpu-mfma-vgpr-form",
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cl::desc("Whether to force use VGPR for Opc and Dest of MFMA. If "
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"unspecified, default to compiler heuristics"),
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cl::location(SIMachineFunctionInfo::MFMAVGPRForm), cl::init(false),
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cl::location(SIMachineFunctionInfo::MFMAVGPRForm), cl::init(true),
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cl::Hidden);
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const GCNTargetMachine &getTM(const GCNSubtarget *STI) {
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@ -15,59 +15,42 @@ define amdgpu_kernel void @test_mfma_f32_32x32x4bf16_1k(ptr addrspace(1) %arg) #
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
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; GCN-NEXT: s_mov_b64 s[36:37], 1
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[36:37], s[36:37] op_sel:[0,1]
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; GCN-NEXT: s_mov_b32 s38, 2
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; GCN-NEXT: s_mov_b32 s39, s37
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; GCN-NEXT: v_pk_mov_b32 v[32:33], s[36:37], s[36:37] op_sel:[0,1]
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; GCN-NEXT: s_mov_b32 s36, 2
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; GCN-NEXT: v_pk_mov_b32 v[34:35], s[36:37], s[36:37] op_sel:[0,1]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx16 s[0:15], s[34:35], 0x0
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; GCN-NEXT: s_load_dwordx16 s[16:31], s[34:35], 0x40
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[38:39], s[38:39] op_sel:[0,1]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_accvgpr_write_b32 a0, s0
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; GCN-NEXT: v_accvgpr_write_b32 a16, s16
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; GCN-NEXT: v_accvgpr_write_b32 a1, s1
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; GCN-NEXT: v_accvgpr_write_b32 a2, s2
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; GCN-NEXT: v_accvgpr_write_b32 a3, s3
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; GCN-NEXT: v_accvgpr_write_b32 a4, s4
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; GCN-NEXT: v_accvgpr_write_b32 a5, s5
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; GCN-NEXT: v_accvgpr_write_b32 a6, s6
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; GCN-NEXT: v_accvgpr_write_b32 a7, s7
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; GCN-NEXT: v_accvgpr_write_b32 a8, s8
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; GCN-NEXT: v_accvgpr_write_b32 a9, s9
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; GCN-NEXT: v_accvgpr_write_b32 a10, s10
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; GCN-NEXT: v_accvgpr_write_b32 a11, s11
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; GCN-NEXT: v_accvgpr_write_b32 a12, s12
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; GCN-NEXT: v_accvgpr_write_b32 a13, s13
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; GCN-NEXT: v_accvgpr_write_b32 a14, s14
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; GCN-NEXT: v_accvgpr_write_b32 a15, s15
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; GCN-NEXT: v_accvgpr_write_b32 a17, s17
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; GCN-NEXT: v_accvgpr_write_b32 a18, s18
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; GCN-NEXT: v_accvgpr_write_b32 a19, s19
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; GCN-NEXT: v_accvgpr_write_b32 a20, s20
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; GCN-NEXT: v_accvgpr_write_b32 a21, s21
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; GCN-NEXT: v_accvgpr_write_b32 a22, s22
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; GCN-NEXT: v_accvgpr_write_b32 a23, s23
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; GCN-NEXT: v_accvgpr_write_b32 a24, s24
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; GCN-NEXT: v_accvgpr_write_b32 a25, s25
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; GCN-NEXT: v_accvgpr_write_b32 a26, s26
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; GCN-NEXT: v_accvgpr_write_b32 a27, s27
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; GCN-NEXT: v_accvgpr_write_b32 a28, s28
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; GCN-NEXT: v_accvgpr_write_b32 a29, s29
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; GCN-NEXT: v_accvgpr_write_b32 a30, s30
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; GCN-NEXT: v_accvgpr_write_b32 a31, s31
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[16:17], s[16:17], s[16:17] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[18:19], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[20:21], s[20:21], s[20:21] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[22:23], s[22:23], s[22:23] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[24:25], s[24:25], s[24:25] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[26:27], s[26:27], s[26:27] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[28:29], s[28:29], s[28:29] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[30:31], s[30:31], s[30:31] op_sel:[0,1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_mfma_f32_32x32x4bf16_1k a[0:31], v[0:1], v[2:3], a[0:31] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mfma_f32_32x32x4bf16_1k v[0:31], v[32:33], v[34:35], v[0:31] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v32, 0
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; GCN-NEXT: s_nop 15
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[34:35]
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; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[34:35] offset:16
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; GCN-NEXT: global_store_dwordx4 v0, a[8:11], s[34:35] offset:32
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; GCN-NEXT: global_store_dwordx4 v0, a[12:15], s[34:35] offset:48
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; GCN-NEXT: global_store_dwordx4 v0, a[16:19], s[34:35] offset:64
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; GCN-NEXT: global_store_dwordx4 v0, a[20:23], s[34:35] offset:80
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; GCN-NEXT: global_store_dwordx4 v0, a[24:27], s[34:35] offset:96
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; GCN-NEXT: global_store_dwordx4 v0, a[28:31], s[34:35] offset:112
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; GCN-NEXT: global_store_dwordx4 v32, v[0:3], s[34:35]
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; GCN-NEXT: global_store_dwordx4 v32, v[4:7], s[34:35] offset:16
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; GCN-NEXT: global_store_dwordx4 v32, v[8:11], s[34:35] offset:32
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; GCN-NEXT: global_store_dwordx4 v32, v[12:15], s[34:35] offset:48
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; GCN-NEXT: global_store_dwordx4 v32, v[16:19], s[34:35] offset:64
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; GCN-NEXT: global_store_dwordx4 v32, v[20:23], s[34:35] offset:80
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; GCN-NEXT: global_store_dwordx4 v32, v[24:27], s[34:35] offset:96
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; GCN-NEXT: global_store_dwordx4 v32, v[28:31], s[34:35] offset:112
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; GCN-NEXT: s_endpgm
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bb:
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%in.1 = load <32 x float>, ptr addrspace(1) %arg
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@ -83,36 +66,28 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4bf16_1k(ptr addrspace(1) %arg) #
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
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; GCN-NEXT: s_mov_b64 s[18:19], 1
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[16:17], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: s_mov_b32 s18, 2
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[18:19], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_accvgpr_write_b32 a0, s0
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; GCN-NEXT: v_accvgpr_write_b32 a1, s1
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; GCN-NEXT: v_accvgpr_write_b32 a2, s2
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; GCN-NEXT: v_accvgpr_write_b32 a3, s3
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; GCN-NEXT: v_accvgpr_write_b32 a4, s4
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; GCN-NEXT: v_accvgpr_write_b32 a5, s5
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; GCN-NEXT: v_accvgpr_write_b32 a6, s6
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; GCN-NEXT: v_accvgpr_write_b32 a7, s7
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; GCN-NEXT: v_accvgpr_write_b32 a8, s8
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; GCN-NEXT: v_accvgpr_write_b32 a9, s9
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; GCN-NEXT: v_accvgpr_write_b32 a10, s10
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; GCN-NEXT: v_accvgpr_write_b32 a11, s11
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; GCN-NEXT: v_accvgpr_write_b32 a12, s12
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; GCN-NEXT: v_accvgpr_write_b32 a13, s13
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; GCN-NEXT: v_accvgpr_write_b32 a14, s14
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; GCN-NEXT: v_accvgpr_write_b32 a15, s15
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_mfma_f32_16x16x4bf16_1k a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mfma_f32_16x16x4bf16_1k v[0:15], v[16:17], v[18:19], v[0:15] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v16, 0
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; GCN-NEXT: s_nop 9
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; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
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; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
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; GCN-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
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; GCN-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
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; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
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; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
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; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
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; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
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; GCN-NEXT: s_endpgm
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bb:
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%in.1 = load <16 x float>, ptr addrspace(1) %arg
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@ -128,21 +103,19 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4bf16_1k(ptr addrspace(1) %arg) #0
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
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; GCN-NEXT: s_mov_b64 s[4:5], 1
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: s_mov_b32 s4, 2
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[6:7], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_accvgpr_write_b32 a0, s0
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; GCN-NEXT: v_accvgpr_write_b32 a1, s1
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; GCN-NEXT: v_accvgpr_write_b32 a2, s2
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; GCN-NEXT: v_accvgpr_write_b32 a3, s3
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_mfma_f32_4x4x4bf16_1k a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mfma_f32_4x4x4bf16_1k v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v4, 0
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; GCN-NEXT: s_nop 3
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; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7]
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; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
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; GCN-NEXT: s_endpgm
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bb:
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%in.1 = load <4 x float>, ptr addrspace(1) %arg
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@ -158,37 +131,29 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8bf16_1k(ptr addrspace(1) %arg) #
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
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; GCN-NEXT: s_mov_b64 s[18:19], 1
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[16:17], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: s_mov_b32 s18, 2
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[18:19], s[18:19], s[18:19] op_sel:[0,1]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_accvgpr_write_b32 a0, s0
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; GCN-NEXT: v_accvgpr_write_b32 a1, s1
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; GCN-NEXT: v_accvgpr_write_b32 a2, s2
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; GCN-NEXT: v_accvgpr_write_b32 a3, s3
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; GCN-NEXT: v_accvgpr_write_b32 a4, s4
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; GCN-NEXT: v_accvgpr_write_b32 a5, s5
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; GCN-NEXT: v_accvgpr_write_b32 a6, s6
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; GCN-NEXT: v_accvgpr_write_b32 a7, s7
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; GCN-NEXT: v_accvgpr_write_b32 a8, s8
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; GCN-NEXT: v_accvgpr_write_b32 a9, s9
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; GCN-NEXT: v_accvgpr_write_b32 a10, s10
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; GCN-NEXT: v_accvgpr_write_b32 a11, s11
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; GCN-NEXT: v_accvgpr_write_b32 a12, s12
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; GCN-NEXT: v_accvgpr_write_b32 a13, s13
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; GCN-NEXT: v_accvgpr_write_b32 a14, s14
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; GCN-NEXT: v_accvgpr_write_b32 a15, s15
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; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
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; GCN-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_mfma_f32_32x32x8bf16_1k a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mfma_f32_32x32x8bf16_1k v[0:15], v[16:17], v[18:19], v[0:15] cbsz:1 abid:2 blgp:3
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; GCN-NEXT: v_mov_b32_e32 v16, 0
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; GCN-NEXT: s_nop 15
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; GCN-NEXT: s_nop 1
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||||
; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <16 x float>, ptr addrspace(1) %arg
|
||||
@ -204,21 +169,19 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16bf16_1k(ptr addrspace(1) %arg)
|
||||
; GCN: ; %bb.0: ; %bb
|
||||
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
|
||||
; GCN-NEXT: s_mov_b64 s[4:5], 1
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: s_mov_b32 s4, 2
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[6:7], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_mfma_f32_16x16x16bf16_1k a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: v_mfma_f32_16x16x16bf16_1k v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, 0
|
||||
; GCN-NEXT: s_nop 9
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7]
|
||||
; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <4 x float>, ptr addrspace(1) %arg
|
||||
@ -238,12 +201,12 @@ define amdgpu_kernel void @test_mfma_f64_4x4x4f64(ptr addrspace(1) %arg, double
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_mfma_f64_4x4x4f64 a[0:1], v[0:1], v[2:3], 0
|
||||
; GCN-NEXT: v_mfma_f64_4x4x4f64 v[4:5], v[0:1], v[2:3], 0
|
||||
; GCN-NEXT: s_nop 3
|
||||
; GCN-NEXT: v_mfma_f64_4x4x4f64 a[0:1], v[0:1], v[2:3], a[0:1] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: v_mfma_f64_4x4x4f64 v[0:1], v[0:1], v[2:3], v[4:5] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GCN-NEXT: s_nop 7
|
||||
; GCN-NEXT: global_store_dwordx2 v0, a[0:1], s[0:1]
|
||||
; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%mai.1 = tail call double @llvm.amdgcn.mfma.f64.4x4x4f64(double %a, double %b, double 0.0, i32 0, i32 0, i32 0)
|
||||
@ -258,25 +221,21 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64(ptr addrspace(1) %arg, doubl
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
|
||||
; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x34
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[8:9], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GCN-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[10:11], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a4, s4
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a5, s5
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a6, s6
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a7, s7
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 a[0:7], v[0:1], v[2:3], a[0:7] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 v[0:7], v[8:9], v[10:11], v[0:7] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
||||
; GCN-NEXT: s_nop 15
|
||||
; GCN-NEXT: s_nop 0
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[8:9]
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[8:9] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <4 x double>, ptr addrspace(1) %arg
|
||||
@ -291,16 +250,16 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_imm(ptr addrspace(1) %
|
||||
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
||||
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[8:9], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[10:11], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 a[0:7], v[0:1], v[2:3], 0
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 a[0:7], v[0:1], v[2:3], a[0:7] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 v[0:7], v[8:9], v[10:11], 0
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 v[0:7], v[8:9], v[10:11], v[0:7] cbsz:1 abid:2 blgp:3
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
||||
; GCN-NEXT: s_nop 15
|
||||
; GCN-NEXT: s_nop 0
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[0:1]
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%mai.1 = tail call <4 x double> @llvm.amdgcn.mfma.f64.16x16x4f64(double %a, double %b, <4 x double> <double 0.0, double 0.0, double 0.0, double 0.0>, i32 0, i32 0, i32 0)
|
||||
@ -312,28 +271,26 @@ bb:
|
||||
define amdgpu_kernel void @test_mfma_f64_16x16x4f64_imm(ptr addrspace(1) %arg, double %a, double %b) #0 {
|
||||
; GCN-LABEL: test_mfma_f64_16x16x4f64_imm:
|
||||
; GCN: ; %bb.0: ; %bb
|
||||
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
||||
; GCN-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x34
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
|
||||
; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x34
|
||||
; GCN-NEXT: s_mov_b64 s[0:1], 0
|
||||
; GCN-NEXT: s_mov_b64 s[6:7], 1.0
|
||||
; GCN-NEXT: s_mov_b64 s[8:9], 0
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a0, s8
|
||||
; GCN-NEXT: s_mov_b64 s[2:3], s[0:1]
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a2, s8
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a4, s8
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a6, s6
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a1, s9
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a3, s9
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a5, s9
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a7, s7
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[8:9], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[10:11], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 a[0:7], v[0:1], v[2:3], a[0:7]
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 v[0:7], v[8:9], v[10:11], v[0:7]
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
||||
; GCN-NEXT: s_nop 15
|
||||
; GCN-NEXT: s_nop 0
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[0:1]
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%mai.1 = tail call <4 x double> @llvm.amdgcn.mfma.f64.16x16x4f64(double %a, double %b, <4 x double> <double 0.0, double 0.0, double 0.0, double 1.0>, i32 0, i32 0, i32 0)
|
||||
@ -344,28 +301,27 @@ bb:
|
||||
define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_lit(ptr addrspace(1) %arg, double %a, double %b) #0 {
|
||||
; GCN-LABEL: test_mfma_f64_16x16x4f64_splat_lit:
|
||||
; GCN: ; %bb.0: ; %bb
|
||||
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
|
||||
; GCN-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
|
||||
; GCN-NEXT: s_mov_b32 s6, 0
|
||||
; GCN-NEXT: s_mov_b32 s7, 0x405ec000
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a0, s6
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
|
||||
; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x34
|
||||
; GCN-NEXT: s_mov_b32 s0, 0
|
||||
; GCN-NEXT: s_mov_b32 s1, 0x405ec000
|
||||
; GCN-NEXT: s_mov_b64 s[2:3], s[0:1]
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a2, s6
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a4, s6
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a6, s6
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a1, s7
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a3, s7
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a5, s7
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a7, s7
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[8:9], s[8:9] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[8:9], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]
|
||||
; GCN-NEXT: s_mov_b64 s[6:7], s[0:1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GCN-NEXT: v_pk_mov_b32 v[10:11], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 a[0:7], v[0:1], v[2:3], a[0:7]
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: v_mfma_f64_16x16x4f64 v[0:7], v[8:9], v[10:11], v[0:7]
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
||||
; GCN-NEXT: s_nop 15
|
||||
; GCN-NEXT: s_nop 0
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[0:3], s[0:1]
|
||||
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
|
||||
; GCN-NEXT: s_endpgm
|
||||
bb:
|
||||
%mai.1 = tail call <4 x double> @llvm.amdgcn.mfma.f64.16x16x4f64(double %a, double %b, <4 x double> <double 123.0, double 123.0, double 123.0, double 123.0>, i32 0, i32 0, i32 0)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regbankselect -regbankselect-fast -amdgpu-mfma-vgpr-form=0 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regbankselect -regbankselect-greedy -amdgpu-mfma-vgpr-form=0 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY
|
||||
|
||||
---
|
||||
name: mfma_f32_32x32x4bf16_1k_vva
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=regbankselect -regbankselect-fast -amdgpu-mfma-vgpr-form=0 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=regbankselect -regbankselect-greedy -amdgpu-mfma-vgpr-form=0 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY
|
||||
|
||||
---
|
||||
name: mfma_i32_16x16x32_i8_vva
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -early-live-intervals < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 -early-live-intervals < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
|
||||
|
||||
declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32, i32, i32)
|
||||
declare <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32, i32, <4 x i32>, i32, i32, i32)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-mfma-vgpr-form=0 -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s
|
||||
|
||||
; This testcase would fail on GFX908 due to not having a free VGPR available to
|
||||
; copy between AGPRs.
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,GFX908 %s
|
||||
|
||||
; Make sure flag is ignored
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -amdgpu-mfma-vgpr-form=1 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,GFX90A %s
|
||||
; Make sure flag is ignored for gfx908
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -amdgpu-mfma-vgpr-form=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9,GFX90A %s
|
||||
|
||||
; GFX9-DAG: buffer_load_format_xyzw v[{{[0-9:]+}}], v{{[0-9]+}}, s[{{[0-9:]+}}], 0 idxen ; encoding:
|
||||
; GFX9-DAG: buffer_load_format_d16_xyzw v[{{[0-9:]+}}], v{{[0-9]+}}, s[{{[0-9:]+}}], 0 idxen ; encoding:
|
||||
|
||||
@ -6,146 +6,144 @@ define amdgpu_kernel void @MFMAExpInterleave(ptr addrspace(1) %out0, ptr addrspa
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_load_dword s6, s[4:5], 0x10
|
||||
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x20
|
||||
; GCN-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 1.0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, 0x3fb8aa3b
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, 1.0
|
||||
; GCN-NEXT: s_mov_b32 s7, 0x42b17218
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_mul_f32_e32 v2, s6, v1
|
||||
; GCN-NEXT: v_rndne_f32_e32 v3, v2
|
||||
; GCN-NEXT: v_sub_f32_e32 v4, v2, v3
|
||||
; GCN-NEXT: v_fma_f32 v1, s6, v1, -v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, 0x32a5705f
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GCN-NEXT: v_fmac_f32_e32 v1, s6, v2
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GCN-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GCN-NEXT: v_add_f32_e32 v1, v4, v1
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v3
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_exp_f32_e32 v1, v1
|
||||
; GCN-NEXT: v_mul_f32_e32 v6, s6, v5
|
||||
; GCN-NEXT: v_rndne_f32_e32 v7, v6
|
||||
; GCN-NEXT: v_sub_f32_e32 v8, v6, v7
|
||||
; GCN-NEXT: v_fma_f32 v5, s6, v5, -v6
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, 0x32a5705f
|
||||
; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GCN-NEXT: v_fmac_f32_e32 v5, s6, v6
|
||||
; GCN-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GCN-NEXT: v_add_f32_e32 v5, v8, v5
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v6, v7
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_exp_f32_e32 v5, v5
|
||||
; GCN-NEXT: s_mov_b32 s0, 0x3fb8aa3b
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: ; iglp_opt mask(0x00000003)
|
||||
; GCN-NEXT: v_ldexp_f32 v1, v1, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s6, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, 0x42b17218
|
||||
; GCN-NEXT: v_ldexp_f32 v5, v5, v6
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, 0xc2ce8ed0
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s6, v6
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, 0x42b17218
|
||||
; GCN-NEXT: s_nop 0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v2
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, 0x7f800000
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v6
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, 0x7f800000
|
||||
; GCN-NEXT: s_mov_b32 s6, 0xc2ce8ed0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v1
|
||||
; GCN-NEXT: v_fma_f32 v4, v1, s0, -v3
|
||||
; GCN-NEXT: v_rndne_f32_e32 v5, v3
|
||||
; GCN-NEXT: v_fmac_f32_e32 v4, 0x32a5705f, v1
|
||||
; GCN-NEXT: v_sub_f32_e32 v3, v3, v5
|
||||
; GCN-NEXT: v_add_f32_e32 v3, v3, v4
|
||||
; GCN-NEXT: v_exp_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v5
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v3, v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
|
||||
; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
|
||||
; GCN-NEXT: v_rndne_f32_e32 v9, v7
|
||||
; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
|
||||
; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
|
||||
; GCN-NEXT: v_add_f32_e32 v7, v7, v8
|
||||
; GCN-NEXT: v_exp_f32_e32 v7, v7
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v7, v7, v8
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v1
|
||||
; GCN-NEXT: v_fma_f32 v4, v1, s0, -v3
|
||||
; GCN-NEXT: v_rndne_f32_e32 v5, v3
|
||||
; GCN-NEXT: v_fmac_f32_e32 v4, 0x32a5705f, v1
|
||||
; GCN-NEXT: v_sub_f32_e32 v3, v3, v5
|
||||
; GCN-NEXT: v_add_f32_e32 v3, v3, v4
|
||||
; GCN-NEXT: v_exp_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v5
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v3, v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
|
||||
; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
|
||||
; GCN-NEXT: v_rndne_f32_e32 v9, v7
|
||||
; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
|
||||
; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
|
||||
; GCN-NEXT: v_add_f32_e32 v7, v7, v8
|
||||
; GCN-NEXT: v_exp_f32_e32 v7, v7
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v7, v7, v8
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v1
|
||||
; GCN-NEXT: v_fma_f32 v4, v1, s0, -v3
|
||||
; GCN-NEXT: v_rndne_f32_e32 v5, v3
|
||||
; GCN-NEXT: v_fmac_f32_e32 v4, 0x32a5705f, v1
|
||||
; GCN-NEXT: v_sub_f32_e32 v3, v3, v5
|
||||
; GCN-NEXT: v_add_f32_e32 v3, v3, v4
|
||||
; GCN-NEXT: v_exp_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v5
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v3, v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
|
||||
; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
|
||||
; GCN-NEXT: v_rndne_f32_e32 v9, v7
|
||||
; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
|
||||
; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
|
||||
; GCN-NEXT: v_add_f32_e32 v7, v7, v8
|
||||
; GCN-NEXT: v_exp_f32_e32 v7, v7
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v7, v7, v8
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v1
|
||||
; GCN-NEXT: v_fma_f32 v4, v1, s0, -v3
|
||||
; GCN-NEXT: v_rndne_f32_e32 v5, v3
|
||||
; GCN-NEXT: v_fmac_f32_e32 v4, 0x32a5705f, v1
|
||||
; GCN-NEXT: v_sub_f32_e32 v3, v3, v5
|
||||
; GCN-NEXT: v_add_f32_e32 v3, v3, v4
|
||||
; GCN-NEXT: v_exp_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v5
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v3, v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
|
||||
; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
|
||||
; GCN-NEXT: v_rndne_f32_e32 v9, v7
|
||||
; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
|
||||
; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
|
||||
; GCN-NEXT: v_add_f32_e32 v7, v7, v8
|
||||
; GCN-NEXT: v_exp_f32_e32 v7, v7
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v7, v7, v8
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v1
|
||||
; GCN-NEXT: v_fma_f32 v4, v1, s0, -v3
|
||||
; GCN-NEXT: v_rndne_f32_e32 v5, v3
|
||||
; GCN-NEXT: v_fmac_f32_e32 v4, 0x32a5705f, v1
|
||||
; GCN-NEXT: v_sub_f32_e32 v3, v3, v5
|
||||
; GCN-NEXT: v_add_f32_e32 v3, v3, v4
|
||||
; GCN-NEXT: v_exp_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v5
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v3, v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
|
||||
; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
|
||||
; GCN-NEXT: v_rndne_f32_e32 v9, v7
|
||||
; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
|
||||
; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
|
||||
; GCN-NEXT: v_add_f32_e32 v7, v7, v8
|
||||
; GCN-NEXT: v_exp_f32_e32 v7, v7
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_ldexp_f32 v7, v7, v8
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v3, 0x3fb8aa3b, v1
|
||||
; GCN-NEXT: v_fma_f32 v4, v1, s0, -v3
|
||||
; GCN-NEXT: v_rndne_f32_e32 v5, v3
|
||||
; GCN-NEXT: v_fmac_f32_e32 v4, 0x32a5705f, v1
|
||||
; GCN-NEXT: v_sub_f32_e32 v3, v3, v5
|
||||
; GCN-NEXT: v_add_f32_e32 v3, v3, v4
|
||||
; GCN-NEXT: v_exp_f32_e32 v3, v3
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v4, v5
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v0, a[0:3]
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1
|
||||
; GCN-NEXT: v_ldexp_f32 v0, v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v7, 0x3fb8aa3b, v5
|
||||
; GCN-NEXT: v_fma_f32 v8, v5, s0, -v7
|
||||
; GCN-NEXT: v_rndne_f32_e32 v9, v7
|
||||
; GCN-NEXT: v_fmac_f32_e32 v8, 0x32a5705f, v5
|
||||
; GCN-NEXT: v_sub_f32_e32 v7, v7, v9
|
||||
; GCN-NEXT: v_add_f32_e32 v7, v7, v8
|
||||
; GCN-NEXT: v_exp_f32_e32 v7, v7
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v8, v9
|
||||
; GCN-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v4, v[0:3]
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v5
|
||||
; GCN-NEXT: v_ldexp_f32 v4, v7, v8
|
||||
; GCN-NEXT: s_nop 0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v5
|
||||
; GCN-NEXT: s_nop 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
|
||||
; GCN-NEXT: v_fma_f32 v3, v0, s0, -v1
|
||||
; GCN-NEXT: v_rndne_f32_e32 v4, v1
|
||||
; GCN-NEXT: v_fmac_f32_e32 v3, 0x32a5705f, v0
|
||||
; GCN-NEXT: v_sub_f32_e32 v1, v1, v4
|
||||
; GCN-NEXT: v_add_f32_e32 v1, v1, v3
|
||||
; GCN-NEXT: v_exp_f32_e32 v1, v1
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v3, v4
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
|
||||
; GCN-NEXT: v_mul_f32_e32 v5, 0x3fb8aa3b, v4
|
||||
; GCN-NEXT: v_fma_f32 v7, v4, s0, -v5
|
||||
; GCN-NEXT: v_rndne_f32_e32 v8, v5
|
||||
; GCN-NEXT: v_fmac_f32_e32 v7, 0x32a5705f, v4
|
||||
; GCN-NEXT: v_sub_f32_e32 v5, v5, v8
|
||||
; GCN-NEXT: v_add_f32_e32 v5, v5, v7
|
||||
; GCN-NEXT: v_exp_f32_e32 v5, v5
|
||||
; GCN-NEXT: v_cvt_i32_f32_e32 v7, v8
|
||||
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v4, 0
|
||||
; GCN-NEXT: v_ldexp_f32 v1, v1, v3
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v0
|
||||
; GCN-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v4
|
||||
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
||||
; GCN-NEXT: v_ldexp_f32 v5, v5, v7
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
|
||||
; GCN-NEXT: v_cmp_nlt_f32_e32 vcc, s7, v4
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: global_store_dwordx4 v4, a[0:3], s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
|
||||
; GCN-NEXT: global_store_dword v4, v0, s[2:3]
|
||||
; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
|
||||
; GCN-NEXT: global_store_dword v8, v4, s[2:3]
|
||||
; GCN-NEXT: s_endpgm
|
||||
%mai0 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %in1, i32 0, i32 0, i32 0)
|
||||
%mai1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai0, i32 0, i32 0, i32 0)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
define amdgpu_kernel void @test_iglp_opt() #0 {
|
||||
; GCN-LABEL: test_iglp_opt:
|
||||
|
||||
@ -1,7 +1,8 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GCN,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug < %s | FileCheck --check-prefixes=GCN,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefixes=GCN,GFX90A %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefix=GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug < %s | FileCheck --check-prefix=GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck --check-prefix=GFX90A %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefixes=GFX90A-VGPR %s
|
||||
|
||||
declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x2bf16(<2 x i16>, <2 x i16>, <32 x float>, i32, i32, i32)
|
||||
declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x2bf16(<2 x i16>, <2 x i16>, <16 x float>, i32, i32, i32)
|
||||
@ -201,6 +202,62 @@ define amdgpu_kernel void @test_mfma_f32_32x32x2bf16(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[0:3], s[34:35]
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[4:7], s[34:35] offset:16
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_f32_32x32x2bf16:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v33, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v34, 2
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v32, 0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx16 s[16:31], s[34:35], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx16 s[0:15], s[34:35], 0x40
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v0, s16
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v1, s17
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v2, s18
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v3, s19
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v4, s20
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, s21
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, s22
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v7, s23
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v8, s24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v9, s25
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v10, s26
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v11, s27
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v12, s28
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v13, s29
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v14, s30
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v15, s31
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, s0
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v17, s1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v18, s2
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v19, s3
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v20, s4
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v21, s5
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v22, s6
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v23, s7
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v24, s8
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v25, s9
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v26, s10
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v27, s11
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v28, s12
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v29, s13
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v30, s14
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v31, s15
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_f32_32x32x2bf16 v[0:31], v33, v34, v[0:31] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: s_nop 15
|
||||
; GFX90A-VGPR-NEXT: s_nop 2
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[24:27], s[34:35] offset:96
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[28:31], s[34:35] offset:112
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[16:19], s[34:35] offset:64
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[20:23], s[34:35] offset:80
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[8:11], s[34:35] offset:32
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[12:15], s[34:35] offset:48
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[0:3], s[34:35]
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v32, v[4:7], s[34:35] offset:16
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <32 x float>, ptr addrspace(1) %arg
|
||||
%a = bitcast i32 1 to <2 x i16>
|
||||
@ -311,6 +368,32 @@ define amdgpu_kernel void @test_mfma_f32_16x16x2bf16(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_f32_16x16x2bf16:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v17, 2
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_f32_16x16x2bf16 v[0:15], v16, v17, v[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; GFX90A-VGPR-NEXT: s_nop 9
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <16 x float>, ptr addrspace(1) %arg
|
||||
%a = bitcast i32 1 to <2 x i16>
|
||||
@ -367,6 +450,23 @@ define amdgpu_kernel void @test_mfma_f32_4x4x2bf16(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: s_nop 4
|
||||
; GFX90A-NEXT: global_store_dwordx4 v1, a[0:3], s[6:7]
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_f32_4x4x2bf16:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v4, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, 2
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, 0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_f32_4x4x2bf16 v[0:3], v4, v6, v[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: s_nop 4
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v5, v[0:3], s[6:7]
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <4 x float>, ptr addrspace(1) %arg
|
||||
%a = bitcast i32 1 to <2 x i16>
|
||||
@ -478,6 +578,33 @@ define amdgpu_kernel void @test_mfma_f32_32x32x4bf16(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_f32_32x32x4bf16:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v17, 2
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_f32_32x32x4bf16 v[0:15], v16, v17, v[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; GFX90A-VGPR-NEXT: s_nop 15
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <16 x float>, ptr addrspace(1) %arg
|
||||
%a = bitcast i32 1 to <2 x i16>
|
||||
@ -534,6 +661,23 @@ define amdgpu_kernel void @test_mfma_f32_16x16x8bf16(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: s_nop 10
|
||||
; GFX90A-NEXT: global_store_dwordx4 v1, a[0:3], s[6:7]
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_f32_16x16x8bf16:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v4, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, 2
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, 0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_f32_16x16x8bf16 v[0:3], v4, v6, v[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: s_nop 10
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v5, v[0:3], s[6:7]
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <4 x float>, ptr addrspace(1) %arg
|
||||
%a = bitcast i32 1 to <2 x i16>
|
||||
@ -544,5 +688,3 @@ bb:
|
||||
}
|
||||
|
||||
attributes #0 = { "amdgpu-flat-work-group-size"="1,256" }
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; GCN: {{.*}}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,6 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -enable-var-scope --check-prefix=AGPR %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope --check-prefix=VGPR %s
|
||||
|
||||
; FIXME: bfloat vector arguments are broken in globalisel.
|
||||
; https://github.com/llvm/llvm-project/issues/77055
|
||||
@ -76,6 +77,131 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
|
||||
; GCN-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: s_endpgm
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[0:1], 48
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[2:3], 32
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[4:5], 16
|
||||
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a1, s9
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a2, s10
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a3, s11
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a4, s12
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a5, s13
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a6, s14
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a7, s15
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a8, s16
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a9, s17
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a10, s18
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a11, s19
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a12, s20
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a13, s21
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a14, s22
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a15, s23
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15]
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
||||
; AGPR-NEXT: v_mov_b32_e32 v8, s20
|
||||
; AGPR-NEXT: v_mov_b32_e32 v9, s21
|
||||
; AGPR-NEXT: v_mov_b32_e32 v10, s22
|
||||
; AGPR-NEXT: v_mov_b32_e32 v11, s23
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
|
||||
; AGPR-NEXT: s_nop 4
|
||||
; AGPR-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[2:3], a[24:27], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[4:5], a[20:23], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[6:7], a[16:19], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[2:3], v[16:19], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[0:1], v[8:11], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b32_e32 v0, s8
|
||||
; AGPR-NEXT: v_mov_b32_e32 v1, s9
|
||||
; AGPR-NEXT: v_mov_b32_e32 v2, s10
|
||||
; AGPR-NEXT: v_mov_b32_e32 v3, s11
|
||||
; AGPR-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 0
|
||||
; AGPR-NEXT: v_mov_b32_e32 v0, s12
|
||||
; AGPR-NEXT: v_mov_b32_e32 v1, s13
|
||||
; AGPR-NEXT: v_mov_b32_e32 v2, s14
|
||||
; AGPR-NEXT: v_mov_b32_e32 v3, s15
|
||||
; AGPR-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_endpgm
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[32:33], 48
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[34:35], 32
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[36:37], 16
|
||||
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v48, s16
|
||||
; VGPR-NEXT: v_mov_b32_e32 v49, s17
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[16:31], v[40:43], v[44:47], v[0:15]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v50, s18
|
||||
; VGPR-NEXT: v_mov_b32_e32 v51, s19
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
|
||||
; VGPR-NEXT: s_nop 8
|
||||
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[34:35], v[24:27], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[36:37], v[20:23], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, s20
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, s21
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, s22
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, s23
|
||||
; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, s8
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, s9
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, s10
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, s11
|
||||
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[0:3], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, s12
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, s13
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, s14
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, s15
|
||||
; VGPR-NEXT: global_store_dwordx4 v[36:37], v[0:3], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_endpgm
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
||||
store volatile <16 x float> %result, ptr addrspace(1) null
|
||||
store volatile <16 x float> %arg2, ptr addrspace(1) null
|
||||
@ -148,6 +274,131 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
|
||||
; GCN-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: s_endpgm
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__flags:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[0:1], 48
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[2:3], 32
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[4:5], 16
|
||||
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a1, s9
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a2, s10
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a3, s11
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a4, s12
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a5, s13
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a6, s14
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a7, s15
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a8, s16
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a9, s17
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a10, s18
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a11, s19
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a12, s20
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a13, s21
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a14, s22
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a15, s23
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[16:31], v[8:11], v[12:15], a[0:15] cbsz:2 abid:3 blgp:1
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
||||
; AGPR-NEXT: v_mov_b32_e32 v8, s20
|
||||
; AGPR-NEXT: v_mov_b32_e32 v9, s21
|
||||
; AGPR-NEXT: v_mov_b32_e32 v10, s22
|
||||
; AGPR-NEXT: v_mov_b32_e32 v11, s23
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[6:7], 0
|
||||
; AGPR-NEXT: s_nop 4
|
||||
; AGPR-NEXT: global_store_dwordx4 v[0:1], a[28:31], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[2:3], a[24:27], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[4:5], a[20:23], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[6:7], a[16:19], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[2:3], v[16:19], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v[0:1], v[8:11], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b32_e32 v0, s8
|
||||
; AGPR-NEXT: v_mov_b32_e32 v1, s9
|
||||
; AGPR-NEXT: v_mov_b32_e32 v2, s10
|
||||
; AGPR-NEXT: v_mov_b32_e32 v3, s11
|
||||
; AGPR-NEXT: global_store_dwordx4 v[6:7], v[0:3], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 0
|
||||
; AGPR-NEXT: v_mov_b32_e32 v0, s12
|
||||
; AGPR-NEXT: v_mov_b32_e32 v1, s13
|
||||
; AGPR-NEXT: v_mov_b32_e32 v2, s14
|
||||
; AGPR-NEXT: v_mov_b32_e32 v3, s15
|
||||
; AGPR-NEXT: global_store_dwordx4 v[4:5], v[0:3], off sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_endpgm
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__flags:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[32:33], 48
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[34:35], 32
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[36:37], 16
|
||||
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v48, s16
|
||||
; VGPR-NEXT: v_mov_b32_e32 v49, s17
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[16:31], v[40:43], v[44:47], v[0:15] cbsz:2 abid:3 blgp:1
|
||||
; VGPR-NEXT: v_mov_b32_e32 v50, s18
|
||||
; VGPR-NEXT: v_mov_b32_e32 v51, s19
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[38:39], 0
|
||||
; VGPR-NEXT: s_nop 8
|
||||
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[28:31], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[34:35], v[24:27], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[36:37], v[20:23], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[16:19], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, s20
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, s21
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, s22
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, s23
|
||||
; VGPR-NEXT: global_store_dwordx4 v[34:35], v[48:51], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v[32:33], v[0:3], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, s8
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, s9
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, s10
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, s11
|
||||
; VGPR-NEXT: global_store_dwordx4 v[38:39], v[0:3], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, s12
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, s13
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, s14
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, s15
|
||||
; VGPR-NEXT: global_store_dwordx4 v[36:37], v[0:3], off sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_endpgm
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 2, i32 3, i32 1)
|
||||
store volatile <16 x float> %result, ptr addrspace(1) null
|
||||
store volatile <16 x float> %arg2, ptr addrspace(1) null
|
||||
@ -194,6 +445,69 @@ define <16 x float> @test_mfma_f32_32x32x16_bf16__mac(<8 x bfloat> %arg0, <8 x b
|
||||
; GCN-NEXT: v_accvgpr_read_b32 v14, a14
|
||||
; GCN-NEXT: v_accvgpr_read_b32 v15, a15
|
||||
; GCN-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a0, v8
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a1, v9
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a2, v10
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a3, v11
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a4, v12
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a5, v13
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a6, v14
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a7, v15
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a8, v16
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a9, v17
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a10, v18
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a11, v19
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a12, v20
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a13, v21
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a14, v22
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a15, v23
|
||||
; AGPR-NEXT: s_nop 1
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15]
|
||||
; AGPR-NEXT: s_nop 11
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v0, a0
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v1, a1
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v2, a2
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v3, a3
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v4, a4
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v5, a5
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v6, a6
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v7, a7
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v8, a8
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v9, a9
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v10, a10
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v11, a11
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v12, a12
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v13, a13
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v14, a14
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v15, a15
|
||||
; AGPR-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[8:23], v[0:3], v[4:7], v[8:23]
|
||||
; VGPR-NEXT: s_nop 11
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, v8
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, v9
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, v10
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, v11
|
||||
; VGPR-NEXT: v_mov_b32_e32 v4, v12
|
||||
; VGPR-NEXT: v_mov_b32_e32 v5, v13
|
||||
; VGPR-NEXT: v_mov_b32_e32 v6, v14
|
||||
; VGPR-NEXT: v_mov_b32_e32 v7, v15
|
||||
; VGPR-NEXT: v_mov_b32_e32 v8, v16
|
||||
; VGPR-NEXT: v_mov_b32_e32 v9, v17
|
||||
; VGPR-NEXT: v_mov_b32_e32 v10, v18
|
||||
; VGPR-NEXT: v_mov_b32_e32 v11, v19
|
||||
; VGPR-NEXT: v_mov_b32_e32 v12, v20
|
||||
; VGPR-NEXT: v_mov_b32_e32 v13, v21
|
||||
; VGPR-NEXT: v_mov_b32_e32 v14, v22
|
||||
; VGPR-NEXT: v_mov_b32_e32 v15, v23
|
||||
; VGPR-NEXT: s_setpc_b64 s[30:31]
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
||||
ret <16 x float> %result
|
||||
}
|
||||
@ -238,6 +552,69 @@ define <16 x float> @test_mfma_f32_32x32x16_bf16__mac__flags(<8 x bfloat> %arg0,
|
||||
; GCN-NEXT: v_accvgpr_read_b32 v14, a14
|
||||
; GCN-NEXT: v_accvgpr_read_b32 v15, a15
|
||||
; GCN-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac__flags:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a0, v8
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a1, v9
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a2, v10
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a3, v11
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a4, v12
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a5, v13
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a6, v14
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a7, v15
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a8, v16
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a9, v17
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a10, v18
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a11, v19
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a12, v20
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a13, v21
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a14, v22
|
||||
; AGPR-NEXT: v_accvgpr_write_b32 a15, v23
|
||||
; AGPR-NEXT: s_nop 1
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15] cbsz:1 abid:1 blgp:1
|
||||
; AGPR-NEXT: s_nop 11
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v0, a0
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v1, a1
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v2, a2
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v3, a3
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v4, a4
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v5, a5
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v6, a6
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v7, a7
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v8, a8
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v9, a9
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v10, a10
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v11, a11
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v12, a12
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v13, a13
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v14, a14
|
||||
; AGPR-NEXT: v_accvgpr_read_b32 v15, a15
|
||||
; AGPR-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__mac__flags:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[8:23], v[0:3], v[4:7], v[8:23] cbsz:1 abid:1 blgp:1
|
||||
; VGPR-NEXT: s_nop 11
|
||||
; VGPR-NEXT: v_mov_b32_e32 v0, v8
|
||||
; VGPR-NEXT: v_mov_b32_e32 v1, v9
|
||||
; VGPR-NEXT: v_mov_b32_e32 v2, v10
|
||||
; VGPR-NEXT: v_mov_b32_e32 v3, v11
|
||||
; VGPR-NEXT: v_mov_b32_e32 v4, v12
|
||||
; VGPR-NEXT: v_mov_b32_e32 v5, v13
|
||||
; VGPR-NEXT: v_mov_b32_e32 v6, v14
|
||||
; VGPR-NEXT: v_mov_b32_e32 v7, v15
|
||||
; VGPR-NEXT: v_mov_b32_e32 v8, v16
|
||||
; VGPR-NEXT: v_mov_b32_e32 v9, v17
|
||||
; VGPR-NEXT: v_mov_b32_e32 v10, v18
|
||||
; VGPR-NEXT: v_mov_b32_e32 v11, v19
|
||||
; VGPR-NEXT: v_mov_b32_e32 v12, v20
|
||||
; VGPR-NEXT: v_mov_b32_e32 v13, v21
|
||||
; VGPR-NEXT: v_mov_b32_e32 v14, v22
|
||||
; VGPR-NEXT: v_mov_b32_e32 v15, v23
|
||||
; VGPR-NEXT: s_setpc_b64 s[30:31]
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 1, i32 1, i32 1)
|
||||
ret <16 x float> %result
|
||||
}
|
||||
@ -299,6 +676,120 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd(<8 x bfloat> %arg
|
||||
; GCN-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: s_endpgm
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; AGPR-NEXT: v_mov_b32_e32 v36, 0
|
||||
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
||||
; AGPR-NEXT: v_mov_b32_e32 v32, s20
|
||||
; AGPR-NEXT: v_mov_b32_e32 v33, s21
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31]
|
||||
; AGPR-NEXT: v_mov_b32_e32 v34, s22
|
||||
; AGPR-NEXT: v_mov_b32_e32 v35, s23
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 2
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 0
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s12
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s13
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s14
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s15
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 0
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s8
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s9
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s10
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s11
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_endpgm
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; VGPR-NEXT: v_mov_b32_e32 v36, 0
|
||||
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v32, s20
|
||||
; VGPR-NEXT: v_mov_b32_e32 v33, s21
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v34, s22
|
||||
; VGPR-NEXT: v_mov_b32_e32 v35, s23
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 2
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, s16
|
||||
; VGPR-NEXT: v_mov_b32_e32 v17, s17
|
||||
; VGPR-NEXT: v_mov_b32_e32 v18, s18
|
||||
; VGPR-NEXT: v_mov_b32_e32 v19, s19
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, s12
|
||||
; VGPR-NEXT: v_mov_b32_e32 v17, s13
|
||||
; VGPR-NEXT: v_mov_b32_e32 v18, s14
|
||||
; VGPR-NEXT: v_mov_b32_e32 v19, s15
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, s8
|
||||
; VGPR-NEXT: v_mov_b32_e32 v17, s9
|
||||
; VGPR-NEXT: v_mov_b32_e32 v18, s10
|
||||
; VGPR-NEXT: v_mov_b32_e32 v19, s11
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_endpgm
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
||||
store volatile <16 x float> %arg2, ptr addrspace(1) %out
|
||||
store volatile <16 x float> %result, ptr addrspace(1) %out
|
||||
@ -362,6 +853,120 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd__flags(<8 x bfloa
|
||||
; GCN-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: s_endpgm
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd__flags:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; AGPR-NEXT: v_mov_b32_e32 v36, 0
|
||||
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
||||
; AGPR-NEXT: v_mov_b32_e32 v32, s20
|
||||
; AGPR-NEXT: v_mov_b32_e32 v33, s21
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31] cbsz:1 abid:2 blgp:3
|
||||
; AGPR-NEXT: v_mov_b32_e32 v34, s22
|
||||
; AGPR-NEXT: v_mov_b32_e32 v35, s23
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 2
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s16
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s17
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s18
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s19
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 0
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s12
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s13
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s14
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s15
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_nop 0
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, s8
|
||||
; AGPR-NEXT: v_mov_b32_e32 v17, s9
|
||||
; AGPR-NEXT: v_mov_b32_e32 v18, s10
|
||||
; AGPR-NEXT: v_mov_b32_e32 v19, s11
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
||||
; AGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; AGPR-NEXT: s_endpgm
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd__flags:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; VGPR-NEXT: v_mov_b32_e32 v36, 0
|
||||
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v32, s20
|
||||
; VGPR-NEXT: v_mov_b32_e32 v33, s21
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[38:41], v[42:45], v[16:31] cbsz:1 abid:2 blgp:3
|
||||
; VGPR-NEXT: v_mov_b32_e32 v34, s22
|
||||
; VGPR-NEXT: v_mov_b32_e32 v35, s23
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[32:35], s[0:1] offset:48 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 2
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, s16
|
||||
; VGPR-NEXT: v_mov_b32_e32 v17, s17
|
||||
; VGPR-NEXT: v_mov_b32_e32 v18, s18
|
||||
; VGPR-NEXT: v_mov_b32_e32 v19, s19
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:32 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, s12
|
||||
; VGPR-NEXT: v_mov_b32_e32 v17, s13
|
||||
; VGPR-NEXT: v_mov_b32_e32 v18, s14
|
||||
; VGPR-NEXT: v_mov_b32_e32 v19, s15
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] offset:16 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_nop 0
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, s8
|
||||
; VGPR-NEXT: v_mov_b32_e32 v17, s9
|
||||
; VGPR-NEXT: v_mov_b32_e32 v18, s10
|
||||
; VGPR-NEXT: v_mov_b32_e32 v19, s11
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[16:19], s[0:1] sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[8:11], s[0:1] offset:32 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[12:15], s[0:1] offset:48 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[0:3], s[0:1] sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: global_store_dwordx4 v36, v[4:7], s[0:1] offset:16 sc0 sc1
|
||||
; VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; VGPR-NEXT: s_endpgm
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 1, i32 2, i32 3)
|
||||
store volatile <16 x float> %arg2, ptr addrspace(1) %out
|
||||
store volatile <16 x float> %result, ptr addrspace(1) %out
|
||||
@ -396,6 +1001,62 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac(<8 x bfloat>
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
||||
; GCN-NEXT: s_endpgm
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
||||
; AGPR-NEXT: s_nop 1
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15]
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; AGPR-NEXT: s_nop 10
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
||||
; AGPR-NEXT: s_endpgm
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
||||
; VGPR-NEXT: s_nop 1
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15]
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; VGPR-NEXT: s_nop 10
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
||||
; VGPR-NEXT: s_endpgm
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 0, i32 0, i32 0)
|
||||
store <16 x float> %result, ptr addrspace(1) %out
|
||||
ret void
|
||||
@ -429,6 +1090,62 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags(<8 x bf
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
||||
; GCN-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
||||
; GCN-NEXT: s_endpgm
|
||||
;
|
||||
; AGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags:
|
||||
; AGPR: ; %bb.0:
|
||||
; AGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; AGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; AGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; AGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
||||
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
||||
; AGPR-NEXT: s_nop 1
|
||||
; AGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1
|
||||
; AGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; AGPR-NEXT: s_nop 10
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
||||
; AGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
||||
; AGPR-NEXT: s_endpgm
|
||||
;
|
||||
; VGPR-LABEL: test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags:
|
||||
; VGPR: ; %bb.0:
|
||||
; VGPR-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0x24
|
||||
; VGPR-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x64
|
||||
; VGPR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa4
|
||||
; VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
|
||||
; VGPR-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
|
||||
; VGPR-NEXT: s_nop 1
|
||||
; VGPR-NEXT: v_mfma_f32_32x32x16_bf16 v[0:15], v[16:19], v[20:23], v[0:15] cbsz:3 abid:2 blgp:1
|
||||
; VGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; VGPR-NEXT: s_nop 10
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1] offset:48
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:32
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:16
|
||||
; VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1]
|
||||
; VGPR-NEXT: s_endpgm
|
||||
%result = call <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.bf16(<8 x bfloat> %arg0, <8 x bfloat> %arg1, <16 x float> %arg2, i32 3, i32 2, i32 1)
|
||||
store <16 x float> %result, ptr addrspace(1) %out
|
||||
ret void
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,8 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GCN,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug < %s | FileCheck --check-prefixes=GCN,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefixes=GCN,GFX90A %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck --check-prefixes=GCN,GFX90A %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefixes=GCN,GFX90A-VGPR %s
|
||||
|
||||
declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32, i32, <16 x i32>, i32, i32, i32)
|
||||
declare <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32, i32, <4 x i32>, i32, i32, i32)
|
||||
@ -109,6 +110,33 @@ define amdgpu_kernel void @test_mfma_i32_32x32x8i8(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
|
||||
; GFX90A-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_i32_32x32x8i8:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v17, 2
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_i32_32x32x8i8 v[0:15], v16, v17, v[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 0
|
||||
; GFX90A-VGPR-NEXT: s_nop 15
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <16 x i32>, ptr addrspace(1) %arg
|
||||
%mai.1 = tail call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32 1, i32 2, <16 x i32> %in.1, i32 1, i32 2, i32 3)
|
||||
@ -163,6 +191,23 @@ define amdgpu_kernel void @test_mfma_i32_16x16x16i8(ptr addrspace(1) %arg) #0 {
|
||||
; GFX90A-NEXT: s_nop 10
|
||||
; GFX90A-NEXT: global_store_dwordx4 v1, a[0:3], s[6:7]
|
||||
; GFX90A-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90A-VGPR-LABEL: test_mfma_i32_16x16x16i8:
|
||||
; GFX90A-VGPR: ; %bb.0: ; %bb
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v4, 1
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, 2
|
||||
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, 0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
||||
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
||||
; GFX90A-VGPR-NEXT: s_nop 1
|
||||
; GFX90A-VGPR-NEXT: v_mfma_i32_16x16x16i8 v[0:3], v4, v6, v[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A-VGPR-NEXT: s_nop 10
|
||||
; GFX90A-VGPR-NEXT: global_store_dwordx4 v5, v[0:3], s[6:7]
|
||||
; GFX90A-VGPR-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <4 x i32>, ptr addrspace(1) %arg
|
||||
%mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32 1, i32 2, <4 x i32> %in.1, i32 1, i32 2, i32 3)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -9,22 +9,20 @@ define amdgpu_kernel void @test_mfma_f32_16x16x8xf32(ptr addrspace(1) %arg) #0 {
|
||||
; GFX942-SDAG-LABEL: test_mfma_f32_16x16x8xf32:
|
||||
; GFX942-SDAG: ; %bb.0: ; %bb
|
||||
; GFX942-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 1.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, 2.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0x40400000
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, 1.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, 2.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 0x40400000
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, 4.0
|
||||
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-SDAG-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, 0
|
||||
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX942-SDAG-NEXT: s_nop 1
|
||||
; GFX942-SDAG-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[4:5], v[0:1], a[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-SDAG-NEXT: v_mfma_f32_16x16x8_xf32 v[0:3], v[8:9], v[4:5], v[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-SDAG-NEXT: s_nop 6
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v2, a[0:3], s[6:7]
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v6, v[0:3], s[6:7]
|
||||
; GFX942-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX942-GISEL-LABEL: test_mfma_f32_16x16x8xf32:
|
||||
@ -32,22 +30,20 @@ define amdgpu_kernel void @test_mfma_f32_16x16x8xf32(ptr addrspace(1) %arg) #0 {
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s4, 1.0
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s5, 2.0
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s4, 0x40400000
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s5, 4.0
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX942-GISEL-NEXT: s_nop 1
|
||||
; GFX942-GISEL-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX942-GISEL-NEXT: v_mfma_f32_16x16x8_xf32 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 0
|
||||
; GFX942-GISEL-NEXT: s_nop 5
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7]
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
|
||||
; GFX942-GISEL-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <4 x float>, ptr addrspace(1) %arg
|
||||
@ -107,37 +103,29 @@ define amdgpu_kernel void @test_mfma_f32_32x32x4xf32(ptr addrspace(1) %arg) #0 {
|
||||
; GFX942-SDAG-LABEL: test_mfma_f32_32x32x4xf32:
|
||||
; GFX942-SDAG: ; %bb.0: ; %bb
|
||||
; GFX942-SDAG-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 1.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 2.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0x40400000
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, 1.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, 2.0
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, 0x40400000
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, 4.0
|
||||
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-SDAG-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
|
||||
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a4, s4
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a5, s5
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a6, s6
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a7, s7
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a8, s8
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a9, s9
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a10, s10
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a11, s11
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a12, s12
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a13, s13
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a14, s14
|
||||
; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a15, s15
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
|
||||
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
|
||||
; GFX942-SDAG-NEXT: s_nop 1
|
||||
; GFX942-SDAG-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[2:3], v[0:1], a[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX942-SDAG-NEXT: v_mfma_f32_32x32x4_xf32 v[0:15], v[18:19], v[16:17], v[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, 0
|
||||
; GFX942-SDAG-NEXT: s_nop 9
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
|
||||
; GFX942-SDAG-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
|
||||
; GFX942-SDAG-NEXT: s_endpgm
|
||||
;
|
||||
; GFX942-GISEL-LABEL: test_mfma_f32_32x32x4xf32:
|
||||
@ -145,37 +133,29 @@ define amdgpu_kernel void @test_mfma_f32_32x32x4xf32(ptr addrspace(1) %arg) #0 {
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s18, 1.0
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s19, 2.0
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[18:19]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[18:19]
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s18, 0x40400000
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
|
||||
; GFX942-GISEL-NEXT: s_mov_b32 s19, 4.0
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[18:19]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
|
||||
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a4, s4
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a5, s5
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a6, s6
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a7, s7
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a8, s8
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a9, s9
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a10, s10
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a11, s11
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a12, s12
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a13, s13
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a14, s14
|
||||
; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a15, s15
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[8:9]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[10:11]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[12:13]
|
||||
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[14:15]
|
||||
; GFX942-GISEL-NEXT: s_nop 1
|
||||
; GFX942-GISEL-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX942-GISEL-NEXT: v_mfma_f32_32x32x4_xf32 v[0:15], v[16:17], v[18:19], v[0:15] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-GISEL-NEXT: v_mov_b32_e32 v16, 0
|
||||
; GFX942-GISEL-NEXT: s_nop 9
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
|
||||
; GFX942-GISEL-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
|
||||
; GFX942-GISEL-NEXT: s_endpgm
|
||||
bb:
|
||||
%in.1 = load <16 x float>, ptr addrspace(1) %arg
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -misched-cluster=0 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -misched-cluster=0 -amdgpu-igrouplp-exact-solver-max-branches=250000 < %s | FileCheck -check-prefix=EXACTCUTOFF %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -misched-cluster=0 -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -check-prefix=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -misched-cluster=0 -amdgpu-mfma-vgpr-form=0 -amdgpu-igrouplp-exact-solver-max-branches=250000 < %s | FileCheck -check-prefix=EXACTCUTOFF %s
|
||||
|
||||
define amdgpu_kernel void @test_sched_group_barrier() #0 {
|
||||
; GCN-LABEL: test_sched_group_barrier:
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -6,38 +6,36 @@ define amdgpu_kernel void @matmul_kernel(i32 %a0, i32 %a1) {
|
||||
; GFX942-LABEL: matmul_kernel:
|
||||
; GFX942: ; %bb.0: ; %entry
|
||||
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
||||
; GFX942-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX942-NEXT: s_mov_b32 s2, 0
|
||||
; GFX942-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a1, 0
|
||||
; GFX942-NEXT: s_mov_b32 s3, 0
|
||||
; GFX942-NEXT: s_mov_b32 s6, 0
|
||||
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; GFX942-NEXT: s_cselect_b64 s[0:1], -1, 0
|
||||
; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
|
||||
; GFX942-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
|
||||
; GFX942-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
|
||||
; GFX942-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v2
|
||||
; GFX942-NEXT: s_branch .LBB0_2
|
||||
; GFX942-NEXT: .LBB0_1: ; %bb2
|
||||
; GFX942-NEXT: ; in Loop: Header=BB0_2 Depth=1
|
||||
; GFX942-NEXT: s_or_b32 s4, s3, 1
|
||||
; GFX942-NEXT: s_ashr_i32 s5, s3, 31
|
||||
; GFX942-NEXT: s_mov_b32 s3, s2
|
||||
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a0, v0
|
||||
; GFX942-NEXT: v_accvgpr_mov_b32 a2, a1
|
||||
; GFX942-NEXT: v_accvgpr_mov_b32 a3, a1
|
||||
; GFX942-NEXT: s_and_b32 s3, s5, s4
|
||||
; GFX942-NEXT: s_nop 0
|
||||
; GFX942-NEXT: v_mfma_f32_16x16x16_f16 a[2:5], v[2:3], v[2:3], a[0:3]
|
||||
; GFX942-NEXT: s_nop 6
|
||||
; GFX942-NEXT: v_accvgpr_read_b32 v0, a2
|
||||
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
|
||||
; GFX942-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX942-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX942-NEXT: s_or_b32 s4, s6, 1
|
||||
; GFX942-NEXT: s_ashr_i32 s3, s6, 31
|
||||
; GFX942-NEXT: v_mfma_f32_16x16x16_f16 v[2:5], v[4:5], v[4:5], v[0:3]
|
||||
; GFX942-NEXT: s_and_b32 s6, s3, s4
|
||||
; GFX942-NEXT: s_nop 5
|
||||
; GFX942-NEXT: v_mov_b32_e32 v0, v2
|
||||
; GFX942-NEXT: s_cbranch_execz .LBB0_4
|
||||
; GFX942-NEXT: .LBB0_2: ; %bb
|
||||
; GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
; GFX942-NEXT: s_and_b64 vcc, exec, s[0:1]
|
||||
; GFX942-NEXT: s_cbranch_vccz .LBB0_1
|
||||
; GFX942-NEXT: ; %bb.3:
|
||||
; GFX942-NEXT: ; implicit-def: $sgpr3
|
||||
; GFX942-NEXT: ; implicit-def: $vgpr0
|
||||
; GFX942-NEXT: ; implicit-def: $sgpr6
|
||||
; GFX942-NEXT: .LBB0_4: ; %common.ret
|
||||
; GFX942-NEXT: s_endpgm
|
||||
;
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --stop-after=greedy,2 < %s | FileCheck -check-prefix=REGALLOC-GFX908 %s
|
||||
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --stop-after=prologepilog < %s | FileCheck -check-prefix=PEI-GFX908 %s
|
||||
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a --stop-after=greedy,2 < %s | FileCheck -check-prefix=REGALLOC-GFX90A %s
|
||||
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a --stop-after=prologepilog < %s | FileCheck -check-prefix=PEI-GFX90A %s
|
||||
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 --stop-after=greedy,2 < %s | FileCheck -check-prefix=REGALLOC-GFX90A %s
|
||||
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 --stop-after=prologepilog < %s | FileCheck -check-prefix=PEI-GFX90A %s
|
||||
|
||||
; Partial reg copy and spill missed during regalloc handled later at frame lowering.
|
||||
define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck -check-prefixes=GCN,GFX908 %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefixes=GCN,GFX90A %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck -check-prefixes=GCN,GFX90A %s
|
||||
|
||||
define amdgpu_kernel void @max_12regs_13a_used(i32 %cond, ptr addrspace(1) %arg, ptr addrspace(1) %out) #2 {
|
||||
; GFX908-LABEL: max_12regs_13a_used:
|
||||
|
||||
@ -884,15 +884,13 @@ define amdgpu_kernel void @v8i8_mfma_i8(ptr addrspace(1) %src1, ptr addrspace(1)
|
||||
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
|
||||
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[14:15], 0x0
|
||||
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a0, s0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a1, s1
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a2, s2
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a3, s3
|
||||
; GFX942-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
|
||||
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
|
||||
; GFX942-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX942-NEXT: s_nop 0
|
||||
; GFX942-NEXT: v_mfma_i32_16x16x32_i8 a[0:3], v[2:3], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-NEXT: v_mfma_i32_16x16x32_i8 v[2:5], v[2:3], v[2:3], v[4:7] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-NEXT: s_nop 6
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[0:3], s[12:13]
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[12:13]
|
||||
; GFX942-NEXT: s_endpgm
|
||||
entry:
|
||||
%idx = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
@ -922,65 +920,65 @@ define amdgpu_kernel void @v8i8_mfma_half(ptr addrspace(1) %src1, ptr addrspace(
|
||||
; GFX942-NEXT: s_load_dwordx8 s[36:43], s[4:5], 0x24
|
||||
; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
||||
; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
|
||||
; GFX942-NEXT: v_mov_b32_e32 v32, 0
|
||||
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
|
||||
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[36:37]
|
||||
; GFX942-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX942-NEXT: global_load_dwordx2 v[34:35], v1, s[36:37]
|
||||
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
|
||||
; GFX942-NEXT: s_cbranch_execz .LBB15_2
|
||||
; GFX942-NEXT: ; %bb.1: ; %bb.1
|
||||
; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[38:39]
|
||||
; GFX942-NEXT: global_load_dwordx2 v[34:35], v0, s[38:39]
|
||||
; GFX942-NEXT: .LBB15_2: ; %bb.2
|
||||
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
|
||||
; GFX942-NEXT: s_load_dwordx16 s[16:31], s[42:43], 0x0
|
||||
; GFX942-NEXT: s_load_dwordx16 s[0:15], s[42:43], 0x40
|
||||
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a0, s16
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a1, s17
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a2, s18
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a3, s19
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a4, s20
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a5, s21
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a6, s22
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a7, s23
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a8, s24
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a9, s25
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a10, s26
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a11, s27
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a12, s28
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a13, s29
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a14, s30
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a15, s31
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a16, s0
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a17, s1
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a18, s2
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a19, s3
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a20, s4
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a21, s5
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a22, s6
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a23, s7
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a24, s8
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a25, s9
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a26, s10
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a27, s11
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a28, s12
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a29, s13
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a30, s14
|
||||
; GFX942-NEXT: v_accvgpr_write_b32 a31, s15
|
||||
; GFX942-NEXT: v_mov_b32_e32 v0, s16
|
||||
; GFX942-NEXT: v_mov_b32_e32 v1, s17
|
||||
; GFX942-NEXT: v_mov_b32_e32 v2, s18
|
||||
; GFX942-NEXT: v_mov_b32_e32 v3, s19
|
||||
; GFX942-NEXT: v_mov_b32_e32 v4, s20
|
||||
; GFX942-NEXT: v_mov_b32_e32 v5, s21
|
||||
; GFX942-NEXT: v_mov_b32_e32 v6, s22
|
||||
; GFX942-NEXT: v_mov_b32_e32 v7, s23
|
||||
; GFX942-NEXT: v_mov_b32_e32 v8, s24
|
||||
; GFX942-NEXT: v_mov_b32_e32 v9, s25
|
||||
; GFX942-NEXT: v_mov_b32_e32 v10, s26
|
||||
; GFX942-NEXT: v_mov_b32_e32 v11, s27
|
||||
; GFX942-NEXT: v_mov_b32_e32 v12, s28
|
||||
; GFX942-NEXT: v_mov_b32_e32 v13, s29
|
||||
; GFX942-NEXT: v_mov_b32_e32 v14, s30
|
||||
; GFX942-NEXT: v_mov_b32_e32 v15, s31
|
||||
; GFX942-NEXT: v_mov_b32_e32 v16, s0
|
||||
; GFX942-NEXT: v_mov_b32_e32 v17, s1
|
||||
; GFX942-NEXT: v_mov_b32_e32 v18, s2
|
||||
; GFX942-NEXT: v_mov_b32_e32 v19, s3
|
||||
; GFX942-NEXT: v_mov_b32_e32 v20, s4
|
||||
; GFX942-NEXT: v_mov_b32_e32 v21, s5
|
||||
; GFX942-NEXT: v_mov_b32_e32 v22, s6
|
||||
; GFX942-NEXT: v_mov_b32_e32 v23, s7
|
||||
; GFX942-NEXT: v_mov_b32_e32 v24, s8
|
||||
; GFX942-NEXT: v_mov_b32_e32 v25, s9
|
||||
; GFX942-NEXT: v_mov_b32_e32 v26, s10
|
||||
; GFX942-NEXT: v_mov_b32_e32 v27, s11
|
||||
; GFX942-NEXT: v_mov_b32_e32 v28, s12
|
||||
; GFX942-NEXT: v_mov_b32_e32 v29, s13
|
||||
; GFX942-NEXT: v_mov_b32_e32 v30, s14
|
||||
; GFX942-NEXT: v_mov_b32_e32 v31, s15
|
||||
; GFX942-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX942-NEXT: s_nop 0
|
||||
; GFX942-NEXT: v_mfma_f32_32x32x4_2b_f16 a[0:31], v[2:3], v[2:3], a[0:31] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-NEXT: v_mfma_f32_32x32x4_2b_f16 v[0:31], v[34:35], v[34:35], v[0:31] cbsz:1 abid:2 blgp:3
|
||||
; GFX942-NEXT: s_nop 15
|
||||
; GFX942-NEXT: s_nop 2
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[28:31], s[40:41] offset:112
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[24:27], s[40:41] offset:96
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[20:23], s[40:41] offset:80
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[16:19], s[40:41] offset:64
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[12:15], s[40:41] offset:48
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[8:11], s[40:41] offset:32
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[4:7], s[40:41] offset:16
|
||||
; GFX942-NEXT: global_store_dwordx4 v1, a[0:3], s[40:41]
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[28:31], s[40:41] offset:112
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[24:27], s[40:41] offset:96
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[20:23], s[40:41] offset:80
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[16:19], s[40:41] offset:64
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[12:15], s[40:41] offset:48
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[8:11], s[40:41] offset:32
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[4:7], s[40:41] offset:16
|
||||
; GFX942-NEXT: global_store_dwordx4 v32, v[0:3], s[40:41]
|
||||
; GFX942-NEXT: s_endpgm
|
||||
entry:
|
||||
%idx = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user