[SimplifyCFG] Set branch weights when merging conditional store to address
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@ -15,6 +15,7 @@
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#ifndef LLVM_IR_PROFDATAUTILS_H
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#define LLVM_IR_PROFDATAUTILS_H
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/IR/Metadata.h"
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@ -186,5 +187,31 @@ LLVM_ABI bool hasExplicitlyUnknownBranchWeights(const Instruction &I);
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/// Scaling the profile data attached to 'I' using the ratio of S/T.
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LLVM_ABI void scaleProfData(Instruction &I, uint64_t S, uint64_t T);
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/// get the branch weights of a branch conditioned on b1 || b2, where b1 and b2
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/// are 2 booleans that are the condition of 2 branches for which we have the
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/// branch weights B1 and B2, respectivelly.
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inline SmallVector<uint64_t, 2>
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getDisjunctionWeights(const SmallVector<uint32_t, 2> &B1,
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const SmallVector<uint32_t, 2> &B2) {
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// for the first conditional branch, the probability the "true" case is taken
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// is p(b1) = B1[0] / (B1[0] + B2[0]). The "false" case's probability is
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// p(not b1) = B1[1] / (B1[0] + B1[1]).
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// Similarly for the second conditional branch and B2.
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//
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// the probability of the new branch NOT being taken is:
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// not P = p((not b1) and (not b2)) =
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// = B1[1] / (B1[0]+B1[1]) * B2[1] / (B2[0]+B2[1]) =
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// = B1[1] * B2[1] / (B1[0] + B1[1]) * (B2[0] + B2[1])
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// then the probability of it being taken is: P = 1 - (not P).
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// The denominator will be the same as above, and the numerator of P will be
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// (B1[0] + B1[1]) * (B2[0] + B2[1]) - B1[1]*B2[1]
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// Which then reduces to what's shown below (out of the 4 terms coming out of
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// the product of sums, the subtracted one cancels out)
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assert(B1.size() == 2);
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assert(B2.size() == 2);
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auto FalseWeight = B1[1] * B2[1];
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auto TrueWeight = B1[0] * B2[0] + B1[0] * B2[1] + B1[1] * B2[0];
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return {TrueWeight, FalseWeight};
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}
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} // namespace llvm
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#endif
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@ -1182,7 +1182,7 @@ static void cloneInstructionsIntoPredecessorBlockAndUpdateSSAUses(
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// only given the branch precondition.
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// Similarly strip attributes on call parameters that may cause UB in
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// location the call is moved to.
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NewBonusInst->dropUBImplyingAttrsAndMetadata();
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NewBonusInst->dropUBImplyingAttrsAndMetadata({LLVMContext::MD_prof});
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NewBonusInst->insertInto(PredBlock, PTI->getIterator());
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auto Range = NewBonusInst->cloneDebugInfoFrom(&BonusInst);
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@ -1808,7 +1808,8 @@ static void hoistConditionalLoadsStores(
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// !annotation: Not impact semantics. Keep it.
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if (const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range))
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MaskedLoadStore->addRangeRetAttr(getConstantRangeFromMetadata(*Ranges));
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I->dropUBImplyingAttrsAndUnknownMetadata({LLVMContext::MD_annotation});
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I->dropUBImplyingAttrsAndUnknownMetadata(
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{LLVMContext::MD_annotation, LLVMContext::MD_prof});
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// FIXME: DIAssignID is not supported for masked store yet.
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// (Verifier::visitDIAssignIDMetadata)
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at::deleteAssignmentMarkers(I);
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@ -3366,7 +3367,7 @@ bool SimplifyCFGOpt::speculativelyExecuteBB(BranchInst *BI,
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if (!SpeculatedStoreValue || &I != SpeculatedStore) {
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I.setDebugLoc(DebugLoc::getDropped());
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}
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I.dropUBImplyingAttrsAndMetadata();
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I.dropUBImplyingAttrsAndMetadata({LLVMContext::MD_prof});
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// Drop ephemeral values.
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if (EphTracker.contains(&I)) {
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@ -4404,10 +4405,12 @@ static bool mergeConditionalStoreToAddress(
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// OK, we're going to sink the stores to PostBB. The store has to be
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// conditional though, so first create the predicate.
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Value *PCond = cast<BranchInst>(PFB->getSinglePredecessor()->getTerminator())
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->getCondition();
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Value *QCond = cast<BranchInst>(QFB->getSinglePredecessor()->getTerminator())
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->getCondition();
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BranchInst *const PBranch =
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cast<BranchInst>(PFB->getSinglePredecessor()->getTerminator());
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BranchInst *const QBranch =
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cast<BranchInst>(QFB->getSinglePredecessor()->getTerminator());
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Value *const PCond = PBranch->getCondition();
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Value *const QCond = QBranch->getCondition();
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Value *PPHI = ensureValueAvailableInSuccessor(PStore->getValueOperand(),
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PStore->getParent());
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@ -4418,19 +4421,30 @@ static bool mergeConditionalStoreToAddress(
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IRBuilder<> QB(PostBB, PostBBFirst);
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QB.SetCurrentDebugLocation(PostBBFirst->getStableDebugLoc());
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Value *PPred = PStore->getParent() == PTB ? PCond : QB.CreateNot(PCond);
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Value *QPred = QStore->getParent() == QTB ? QCond : QB.CreateNot(QCond);
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InvertPCond = (PStore->getParent() == PTB) ^ InvertPCond;
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InvertQCond = (QStore->getParent() == QTB) ^ InvertQCond;
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Value *const PPred = InvertPCond ? PCond : QB.CreateNot(PCond);
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Value *const QPred = InvertQCond ? QCond : QB.CreateNot(QCond);
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if (InvertPCond)
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PPred = QB.CreateNot(PPred);
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if (InvertQCond)
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QPred = QB.CreateNot(QPred);
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Value *CombinedPred = QB.CreateOr(PPred, QPred);
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BasicBlock::iterator InsertPt = QB.GetInsertPoint();
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auto *T = SplitBlockAndInsertIfThen(CombinedPred, InsertPt,
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/*Unreachable=*/false,
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/*BranchWeights=*/nullptr, DTU);
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if (hasBranchWeightMD(*PBranch) && hasBranchWeightMD(*QBranch)) {
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SmallVector<uint32_t, 2> PWeights, QWeights;
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extractBranchWeights(*PBranch, PWeights);
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extractBranchWeights(*QBranch, QWeights);
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if (InvertPCond)
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std::swap(PWeights[0], PWeights[1]);
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if (InvertQCond)
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std::swap(QWeights[0], QWeights[1]);
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auto CombinedWeights = getDisjunctionWeights(PWeights, QWeights);
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setBranchWeights(PostBB->getTerminator(), CombinedWeights[0],
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CombinedWeights[1],
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/*IsExpected=*/false);
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}
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QB.SetInsertPoint(T);
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StoreInst *SI = cast<StoreInst>(QB.CreateStore(QPHI, Address));
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