[AArch64][SME]: Add precursory tests for D138290
Add testing files: - fp-arith.ll - fp-fma.ll
This commit is contained in:
Hassnaa Hamdi
parent
abfe65a12b
commit
97bbc8df84
@ -0,0 +1,905 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; FADD
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;
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define <2 x half> @fadd_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
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; CHECK-LABEL: fadd_v2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%res = fadd <2 x half> %op1, %op2
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ret <2 x half> %res
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}
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define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
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; CHECK-LABEL: fadd_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%res = fadd <4 x half> %op1, %op2
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ret <4 x half> %res
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}
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define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
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; CHECK-LABEL: fadd_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%res = fadd <8 x half> %op1, %op2
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ret <8 x half> %res
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}
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define void @fadd_v16f16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fadd_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: fadd v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: fadd v1.8h, v1.8h, v3.8h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, ptr %a
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%op2 = load <16 x half>, ptr %b
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%res = fadd <16 x half> %op1, %op2
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store <16 x half> %res, ptr %a
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ret void
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}
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define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
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; CHECK-LABEL: fadd_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%res = fadd <2 x float> %op1, %op2
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ret <2 x float> %res
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}
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define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
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; CHECK-LABEL: fadd_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%res = fadd <4 x float> %op1, %op2
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ret <4 x float> %res
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}
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define void @fadd_v8f32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fadd_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: fadd v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: fadd v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x float>, ptr %a
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%op2 = load <8 x float>, ptr %b
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%res = fadd <8 x float> %op1, %op2
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store <8 x float> %res, ptr %a
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ret void
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}
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define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
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; CHECK-LABEL: fadd_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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%res = fadd <2 x double> %op1, %op2
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ret <2 x double> %res
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}
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define void @fadd_v4f64(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fadd_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: fadd v0.2d, v0.2d, v2.2d
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; CHECK-NEXT: fadd v1.2d, v1.2d, v3.2d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <4 x double>, ptr %a
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%op2 = load <4 x double>, ptr %b
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%res = fadd <4 x double> %op1, %op2
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store <4 x double> %res, ptr %a
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ret void
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}
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;
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; FDIV
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;
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define <2 x half> @fdiv_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
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; CHECK-LABEL: fdiv_v2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fdiv v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%res = fdiv <2 x half> %op1, %op2
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ret <2 x half> %res
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}
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define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
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; CHECK-LABEL: fdiv_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fdiv v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%res = fdiv <4 x half> %op1, %op2
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ret <4 x half> %res
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}
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define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
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; CHECK-LABEL: fdiv_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fdiv v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%res = fdiv <8 x half> %op1, %op2
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ret <8 x half> %res
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}
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define void @fdiv_v16f16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fdiv_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q3, [x1]
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: fdiv v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: fdiv v1.8h, v2.8h, v3.8h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, ptr %a
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%op2 = load <16 x half>, ptr %b
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%res = fdiv <16 x half> %op1, %op2
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store <16 x half> %res, ptr %a
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ret void
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}
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define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
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; CHECK-LABEL: fdiv_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fdiv v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%res = fdiv <2 x float> %op1, %op2
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ret <2 x float> %res
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}
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define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
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; CHECK-LABEL: fdiv_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fdiv v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%res = fdiv <4 x float> %op1, %op2
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ret <4 x float> %res
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}
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define void @fdiv_v8f32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fdiv_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q3, [x1]
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: fdiv v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: fdiv v1.4s, v2.4s, v3.4s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x float>, ptr %a
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%op2 = load <8 x float>, ptr %b
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%res = fdiv <8 x float> %op1, %op2
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store <8 x float> %res, ptr %a
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ret void
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}
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define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
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; CHECK-LABEL: fdiv_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fdiv v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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%res = fdiv <2 x double> %op1, %op2
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ret <2 x double> %res
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}
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define void @fdiv_v4f64(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fdiv_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q3, [x1]
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: fdiv v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: fdiv v1.2d, v2.2d, v3.2d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <4 x double>, ptr %a
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%op2 = load <4 x double>, ptr %b
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%res = fdiv <4 x double> %op1, %op2
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store <4 x double> %res, ptr %a
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ret void
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}
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;
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; FMA
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;
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define <2 x half> @fma_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3) #0 {
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; CHECK-LABEL: fma_v2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmla v2.4h, v1.4h, v0.4h
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; CHECK-NEXT: fmov d0, d2
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; CHECK-NEXT: ret
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%res = call <2 x half> @llvm.fma.v2f16(<2 x half> %op1, <2 x half> %op2, <2 x half> %op3)
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ret <2 x half> %res
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}
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define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) #0 {
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; CHECK-LABEL: fma_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmla v2.4h, v1.4h, v0.4h
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; CHECK-NEXT: fmov d0, d2
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; CHECK-NEXT: ret
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%res = call <4 x half> @llvm.fma.v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3)
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ret <4 x half> %res
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}
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define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) #0 {
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; CHECK-LABEL: fma_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmla v2.8h, v1.8h, v0.8h
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%res = call <8 x half> @llvm.fma.v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3)
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ret <8 x half> %res
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}
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define void @fma_v16f16(ptr %a, ptr %b, ptr %c) #0 {
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; CHECK-LABEL: fma_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q3, [x1]
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: ldp q4, q5, [x2]
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; CHECK-NEXT: fmla v4.8h, v0.8h, v1.8h
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; CHECK-NEXT: fmla v5.8h, v3.8h, v2.8h
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; CHECK-NEXT: stp q4, q5, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, ptr %a
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%op2 = load <16 x half>, ptr %b
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%op3 = load <16 x half>, ptr %c
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%res = call <16 x half> @llvm.fma.v16f16(<16 x half> %op1, <16 x half> %op2, <16 x half> %op3)
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store <16 x half> %res, ptr %a
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ret void
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}
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define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) #0 {
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; CHECK-LABEL: fma_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmla v2.2s, v1.2s, v0.2s
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; CHECK-NEXT: fmov d0, d2
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; CHECK-NEXT: ret
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%res = call <2 x float> @llvm.fma.v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3)
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ret <2 x float> %res
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}
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define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) #0 {
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; CHECK-LABEL: fma_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmla v2.4s, v1.4s, v0.4s
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%res = call <4 x float> @llvm.fma.v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3)
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ret <4 x float> %res
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}
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define void @fma_v8f32(ptr %a, ptr %b, ptr %c) #0 {
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; CHECK-LABEL: fma_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q3, [x1]
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: ldp q4, q5, [x2]
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; CHECK-NEXT: fmla v4.4s, v0.4s, v1.4s
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; CHECK-NEXT: fmla v5.4s, v3.4s, v2.4s
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; CHECK-NEXT: stp q4, q5, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x float>, ptr %a
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%op2 = load <8 x float>, ptr %b
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%op3 = load <8 x float>, ptr %c
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%res = call <8 x float> @llvm.fma.v8f32(<8 x float> %op1, <8 x float> %op2, <8 x float> %op3)
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store <8 x float> %res, ptr %a
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ret void
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}
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define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) #0 {
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; CHECK-LABEL: fma_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmla v2.2d, v1.2d, v0.2d
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.fma.v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3)
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ret <2 x double> %res
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}
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define void @fma_v4f64(ptr %a, ptr %b, ptr %c) #0 {
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; CHECK-LABEL: fma_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q3, [x1]
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: ldp q4, q5, [x2]
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; CHECK-NEXT: fmla v4.2d, v0.2d, v1.2d
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; CHECK-NEXT: fmla v5.2d, v3.2d, v2.2d
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; CHECK-NEXT: stp q4, q5, [x0]
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; CHECK-NEXT: ret
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%op1 = load <4 x double>, ptr %a
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%op2 = load <4 x double>, ptr %b
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%op3 = load <4 x double>, ptr %c
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%res = call <4 x double> @llvm.fma.v4f64(<4 x double> %op1, <4 x double> %op2, <4 x double> %op3)
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store <4 x double> %res, ptr %a
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ret void
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}
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;
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; FMUL
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;
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define <2 x half> @fmul_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
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; CHECK-LABEL: fmul_v2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = fmul <2 x half> %op1, %op2
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ret <2 x half> %res
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}
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define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
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; CHECK-LABEL: fmul_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = fmul <4 x half> %op1, %op2
|
||||
ret <4 x half> %res
|
||||
}
|
||||
|
||||
define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
|
||||
; CHECK-LABEL: fmul_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.h, vl8
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%res = fmul <8 x half> %op1, %op2
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define void @fmul_v16f16(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fmul_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: ptrue p0.h, vl8
|
||||
; CHECK-NEXT: ldp q2, q3, [x1]
|
||||
; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z2.h
|
||||
; CHECK-NEXT: fmul z1.h, p0/m, z1.h, z3.h
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x half>, ptr %a
|
||||
%op2 = load <16 x half>, ptr %b
|
||||
%res = fmul <16 x half> %op1, %op2
|
||||
store <16 x half> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
|
||||
; CHECK-LABEL: fmul_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.s, vl2
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%res = fmul <2 x float> %op1, %op2
|
||||
ret <2 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
|
||||
; CHECK-LABEL: fmul_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.s, vl4
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%res = fmul <4 x float> %op1, %op2
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define void @fmul_v8f32(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fmul_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: ptrue p0.s, vl4
|
||||
; CHECK-NEXT: ldp q2, q3, [x1]
|
||||
; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z2.s
|
||||
; CHECK-NEXT: fmul z1.s, p0/m, z1.s, z3.s
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x float>, ptr %a
|
||||
%op2 = load <8 x float>, ptr %b
|
||||
%res = fmul <8 x float> %op1, %op2
|
||||
store <8 x float> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
|
||||
; CHECK-LABEL: fmul_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: ptrue p0.d, vl2
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%res = fmul <2 x double> %op1, %op2
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define void @fmul_v4f64(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fmul_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: ptrue p0.d, vl2
|
||||
; CHECK-NEXT: ldp q2, q3, [x1]
|
||||
; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z2.d
|
||||
; CHECK-NEXT: fmul z1.d, p0/m, z1.d, z3.d
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, ptr %a
|
||||
%op2 = load <4 x double>, ptr %b
|
||||
%res = fmul <4 x double> %op1, %op2
|
||||
store <4 x double> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FNEG
|
||||
;
|
||||
|
||||
define <2 x half> @fneg_v2f16(<2 x half> %op) #0 {
|
||||
; CHECK-LABEL: fneg_v2f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fneg v0.4h, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = fneg <2 x half> %op
|
||||
ret <2 x half> %res
|
||||
}
|
||||
|
||||
define <4 x half> @fneg_v4f16(<4 x half> %op) #0 {
|
||||
; CHECK-LABEL: fneg_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fneg v0.4h, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = fneg <4 x half> %op
|
||||
ret <4 x half> %res
|
||||
}
|
||||
|
||||
define <8 x half> @fneg_v8f16(<8 x half> %op) #0 {
|
||||
; CHECK-LABEL: fneg_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fneg v0.8h, v0.8h
|
||||
; CHECK-NEXT: ret
|
||||
%res = fneg <8 x half> %op
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define void @fneg_v16f16(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fneg_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fneg v0.8h, v0.8h
|
||||
; CHECK-NEXT: fneg v1.8h, v1.8h
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <16 x half>, ptr %a
|
||||
%res = fneg <16 x half> %op
|
||||
store <16 x half> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @fneg_v2f32(<2 x float> %op) #0 {
|
||||
; CHECK-LABEL: fneg_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fneg v0.2s, v0.2s
|
||||
; CHECK-NEXT: ret
|
||||
%res = fneg <2 x float> %op
|
||||
ret <2 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @fneg_v4f32(<4 x float> %op) #0 {
|
||||
; CHECK-LABEL: fneg_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fneg v0.4s, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%res = fneg <4 x float> %op
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define void @fneg_v8f32(ptr %a) #0 {
|
||||
; CHECK-LABEL: fneg_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fneg v0.4s, v0.4s
|
||||
; CHECK-NEXT: fneg v1.4s, v1.4s
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <8 x float>, ptr %a
|
||||
%res = fneg <8 x float> %op
|
||||
store <8 x float> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x double> @fneg_v2f64(<2 x double> %op) #0 {
|
||||
; CHECK-LABEL: fneg_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fneg v0.2d, v0.2d
|
||||
; CHECK-NEXT: ret
|
||||
%res = fneg <2 x double> %op
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define void @fneg_v4f64(ptr %a) #0 {
|
||||
; CHECK-LABEL: fneg_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fneg v0.2d, v0.2d
|
||||
; CHECK-NEXT: fneg v1.2d, v1.2d
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <4 x double>, ptr %a
|
||||
%res = fneg <4 x double> %op
|
||||
store <4 x double> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FSQRT
|
||||
;
|
||||
|
||||
define <2 x half> @fsqrt_v2f16(<2 x half> %op) #0 {
|
||||
; CHECK-LABEL: fsqrt_v2f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsqrt v0.4h, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <2 x half> @llvm.sqrt.v2f16(<2 x half> %op)
|
||||
ret <2 x half> %res
|
||||
}
|
||||
|
||||
define <4 x half> @fsqrt_v4f16(<4 x half> %op) #0 {
|
||||
; CHECK-LABEL: fsqrt_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsqrt v0.4h, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <4 x half> @llvm.sqrt.v4f16(<4 x half> %op)
|
||||
ret <4 x half> %res
|
||||
}
|
||||
|
||||
define <8 x half> @fsqrt_v8f16(<8 x half> %op) #0 {
|
||||
; CHECK-LABEL: fsqrt_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsqrt v0.8h, v0.8h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %op)
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define void @fsqrt_v16f16(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fsqrt_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fsqrt v0.8h, v0.8h
|
||||
; CHECK-NEXT: fsqrt v1.8h, v1.8h
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <16 x half>, ptr %a
|
||||
%res = call <16 x half> @llvm.sqrt.v16f16(<16 x half> %op)
|
||||
store <16 x half> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @fsqrt_v2f32(<2 x float> %op) #0 {
|
||||
; CHECK-LABEL: fsqrt_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsqrt v0.2s, v0.2s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %op)
|
||||
ret <2 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @fsqrt_v4f32(<4 x float> %op) #0 {
|
||||
; CHECK-LABEL: fsqrt_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsqrt v0.4s, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %op)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define void @fsqrt_v8f32(ptr %a) #0 {
|
||||
; CHECK-LABEL: fsqrt_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fsqrt v0.4s, v0.4s
|
||||
; CHECK-NEXT: fsqrt v1.4s, v1.4s
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <8 x float>, ptr %a
|
||||
%res = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %op)
|
||||
store <8 x float> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x double> @fsqrt_v2f64(<2 x double> %op) #0 {
|
||||
; CHECK-LABEL: fsqrt_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsqrt v0.2d, v0.2d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %op)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define void @fsqrt_v4f64(ptr %a) #0 {
|
||||
; CHECK-LABEL: fsqrt_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fsqrt v0.2d, v0.2d
|
||||
; CHECK-NEXT: fsqrt v1.2d, v1.2d
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <4 x double>, ptr %a
|
||||
%res = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %op)
|
||||
store <4 x double> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FSUB
|
||||
;
|
||||
|
||||
define <2 x half> @fsub_v2f16(<2 x half> %op1, <2 x half> %op2) #0 {
|
||||
; CHECK-LABEL: fsub_v2f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsub v0.4h, v0.4h, v1.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = fsub <2 x half> %op1, %op2
|
||||
ret <2 x half> %res
|
||||
}
|
||||
|
||||
define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
|
||||
; CHECK-LABEL: fsub_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsub v0.4h, v0.4h, v1.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = fsub <4 x half> %op1, %op2
|
||||
ret <4 x half> %res
|
||||
}
|
||||
|
||||
define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
|
||||
; CHECK-LABEL: fsub_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsub v0.8h, v0.8h, v1.8h
|
||||
; CHECK-NEXT: ret
|
||||
%res = fsub <8 x half> %op1, %op2
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define void @fsub_v16f16(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fsub_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: ldp q2, q3, [x1]
|
||||
; CHECK-NEXT: fsub v0.8h, v0.8h, v2.8h
|
||||
; CHECK-NEXT: fsub v1.8h, v1.8h, v3.8h
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x half>, ptr %a
|
||||
%op2 = load <16 x half>, ptr %b
|
||||
%res = fsub <16 x half> %op1, %op2
|
||||
store <16 x half> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
|
||||
; CHECK-LABEL: fsub_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsub v0.2s, v0.2s, v1.2s
|
||||
; CHECK-NEXT: ret
|
||||
%res = fsub <2 x float> %op1, %op2
|
||||
ret <2 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
|
||||
; CHECK-LABEL: fsub_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: ret
|
||||
%res = fsub <4 x float> %op1, %op2
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define void @fsub_v8f32(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fsub_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: ldp q2, q3, [x1]
|
||||
; CHECK-NEXT: fsub v0.4s, v0.4s, v2.4s
|
||||
; CHECK-NEXT: fsub v1.4s, v1.4s, v3.4s
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x float>, ptr %a
|
||||
%op2 = load <8 x float>, ptr %b
|
||||
%res = fsub <8 x float> %op1, %op2
|
||||
store <8 x float> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
|
||||
; CHECK-LABEL: fsub_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fsub v0.2d, v0.2d, v1.2d
|
||||
; CHECK-NEXT: ret
|
||||
%res = fsub <2 x double> %op1, %op2
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define void @fsub_v4f64(ptr %a, ptr %b) #0 {
|
||||
; CHECK-LABEL: fsub_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: ldp q2, q3, [x1]
|
||||
; CHECK-NEXT: fsub v0.2d, v0.2d, v2.2d
|
||||
; CHECK-NEXT: fsub v1.2d, v1.2d, v3.2d
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, ptr %a
|
||||
%op2 = load <4 x double>, ptr %b
|
||||
%res = fsub <4 x double> %op1, %op2
|
||||
store <4 x double> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; FABS
|
||||
;
|
||||
|
||||
define <2 x half> @fabs_v2f16(<2 x half> %op) #0 {
|
||||
; CHECK-LABEL: fabs_v2f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabs v0.4h, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <2 x half> @llvm.fabs.v2f16(<2 x half> %op)
|
||||
ret <2 x half> %res
|
||||
}
|
||||
|
||||
define <4 x half> @fabs_v4f16(<4 x half> %op) #0 {
|
||||
; CHECK-LABEL: fabs_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabs v0.4h, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <4 x half> @llvm.fabs.v4f16(<4 x half> %op)
|
||||
ret <4 x half> %res
|
||||
}
|
||||
|
||||
define <8 x half> @fabs_v8f16(<8 x half> %op) #0 {
|
||||
; CHECK-LABEL: fabs_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabs v0.8h, v0.8h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <8 x half> @llvm.fabs.v8f16(<8 x half> %op)
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define void @fabs_v16f16(ptr %a) #0 {
|
||||
; CHECK-LABEL: fabs_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fabs v0.8h, v0.8h
|
||||
; CHECK-NEXT: fabs v1.8h, v1.8h
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <16 x half>, ptr %a
|
||||
%res = call <16 x half> @llvm.fabs.v16f16(<16 x half> %op)
|
||||
store <16 x half> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @fabs_v2f32(<2 x float> %op) #0 {
|
||||
; CHECK-LABEL: fabs_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabs v0.2s, v0.2s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <2 x float> @llvm.fabs.v2f32(<2 x float> %op)
|
||||
ret <2 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @fabs_v4f32(<4 x float> %op) #0 {
|
||||
; CHECK-LABEL: fabs_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabs v0.4s, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <4 x float> @llvm.fabs.v4f32(<4 x float> %op)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define void @fabs_v8f32(ptr %a) #0 {
|
||||
; CHECK-LABEL: fabs_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fabs v0.4s, v0.4s
|
||||
; CHECK-NEXT: fabs v1.4s, v1.4s
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <8 x float>, ptr %a
|
||||
%res = call <8 x float> @llvm.fabs.v8f32(<8 x float> %op)
|
||||
store <8 x float> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x double> @fabs_v2f64(<2 x double> %op) #0 {
|
||||
; CHECK-LABEL: fabs_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fabs v0.2d, v0.2d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <2 x double> @llvm.fabs.v2f64(<2 x double> %op)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define void @fabs_v4f64(ptr %a) #0 {
|
||||
; CHECK-LABEL: fabs_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: fabs v0.2d, v0.2d
|
||||
; CHECK-NEXT: fabs v1.2d, v1.2d
|
||||
; CHECK-NEXT: stp q0, q1, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op = load <4 x double>, ptr %a
|
||||
%res = call <4 x double> @llvm.fabs.v4f64(<4 x double> %op)
|
||||
store <4 x double> %res, ptr %a
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
|
||||
declare <2 x half> @llvm.fma.v2f16(<2 x half>, <2 x half>, <2 x half>)
|
||||
declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
|
||||
declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
|
||||
declare <16 x half> @llvm.fma.v16f16(<16 x half>, <16 x half>, <16 x half>)
|
||||
declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)
|
||||
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
|
||||
declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>)
|
||||
declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
|
||||
declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>)
|
||||
|
||||
declare <2 x half> @llvm.sqrt.v2f16(<2 x half>)
|
||||
declare <4 x half> @llvm.sqrt.v4f16(<4 x half>)
|
||||
declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
|
||||
declare <16 x half> @llvm.sqrt.v16f16(<16 x half>)
|
||||
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)
|
||||
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
|
||||
declare <8 x float> @llvm.sqrt.v8f32(<8 x float>)
|
||||
declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
|
||||
declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
|
||||
|
||||
declare <2 x half> @llvm.fabs.v2f16(<2 x half>)
|
||||
declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
|
||||
declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
|
||||
declare <16 x half> @llvm.fabs.v16f16(<16 x half>)
|
||||
declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
|
||||
declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
|
||||
declare <8 x float> @llvm.fabs.v8f32(<8 x float>)
|
||||
declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
|
||||
declare <4 x double> @llvm.fabs.v4f64(<4 x double>)
|
||||
@ -0,0 +1,135 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
|
||||
|
||||
target triple = "aarch64-unknown-linux-gnu"
|
||||
|
||||
;
|
||||
; FMA
|
||||
;
|
||||
|
||||
define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) #0 {
|
||||
; CHECK-LABEL: fma_v4f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmla v2.4h, v1.4h, v0.4h
|
||||
; CHECK-NEXT: fmov d0, d2
|
||||
; CHECK-NEXT: ret
|
||||
%mul = fmul contract <4 x half> %op1, %op2
|
||||
%res = fadd contract <4 x half> %mul, %op3
|
||||
ret <4 x half> %res
|
||||
}
|
||||
|
||||
define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) #0 {
|
||||
; CHECK-LABEL: fma_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmla v2.8h, v1.8h, v0.8h
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mul = fmul contract <8 x half> %op1, %op2
|
||||
%res = fadd contract <8 x half> %mul, %op3
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) #0 {
|
||||
; CHECK-LABEL: fma_v16f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q3, [x1]
|
||||
; CHECK-NEXT: ldp q1, q2, [x0]
|
||||
; CHECK-NEXT: ldp q4, q5, [x2]
|
||||
; CHECK-NEXT: fmla v4.8h, v0.8h, v1.8h
|
||||
; CHECK-NEXT: fmla v5.8h, v3.8h, v2.8h
|
||||
; CHECK-NEXT: stp q4, q5, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x half>, <16 x half>* %a
|
||||
%op2 = load <16 x half>, <16 x half>* %b
|
||||
%op3 = load <16 x half>, <16 x half>* %c
|
||||
%mul = fmul contract <16 x half> %op1, %op2
|
||||
%res = fadd contract <16 x half> %mul, %op3
|
||||
store <16 x half> %res, <16 x half>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) #0 {
|
||||
; CHECK-LABEL: fma_v2f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmla v2.2s, v1.2s, v0.2s
|
||||
; CHECK-NEXT: fmov d0, d2
|
||||
; CHECK-NEXT: ret
|
||||
%mul = fmul contract <2 x float> %op1, %op2
|
||||
%res = fadd contract <2 x float> %mul, %op3
|
||||
ret <2 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) #0 {
|
||||
; CHECK-LABEL: fma_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmla v2.4s, v1.4s, v0.4s
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mul = fmul contract <4 x float> %op1, %op2
|
||||
%res = fadd contract <4 x float> %mul, %op3
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) #0 {
|
||||
; CHECK-LABEL: fma_v8f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q3, [x1]
|
||||
; CHECK-NEXT: ldp q1, q2, [x0]
|
||||
; CHECK-NEXT: ldp q4, q5, [x2]
|
||||
; CHECK-NEXT: fmla v4.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: fmla v5.4s, v3.4s, v2.4s
|
||||
; CHECK-NEXT: stp q4, q5, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x float>, <8 x float>* %a
|
||||
%op2 = load <8 x float>, <8 x float>* %b
|
||||
%op3 = load <8 x float>, <8 x float>* %c
|
||||
%mul = fmul contract <8 x float> %op1, %op2
|
||||
%res = fadd contract <8 x float> %mul, %op3
|
||||
store <8 x float> %res, <8 x float>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double> %op3) #0 {
|
||||
; CHECK-LABEL: fma_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: fmadd d0, d0, d1, d2
|
||||
; CHECK-NEXT: ret
|
||||
%mul = fmul contract <1 x double> %op1, %op2
|
||||
%res = fadd contract <1 x double> %mul, %op3
|
||||
ret <1 x double> %res
|
||||
}
|
||||
|
||||
define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) #0 {
|
||||
; CHECK-LABEL: fma_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmla v2.2d, v1.2d, v0.2d
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mul = fmul contract <2 x double> %op1, %op2
|
||||
%res = fadd contract <2 x double> %mul, %op3
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) #0 {
|
||||
; CHECK-LABEL: fma_v4f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q3, [x1]
|
||||
; CHECK-NEXT: ldp q1, q2, [x0]
|
||||
; CHECK-NEXT: ldp q4, q5, [x2]
|
||||
; CHECK-NEXT: fmla v4.2d, v0.2d, v1.2d
|
||||
; CHECK-NEXT: fmla v5.2d, v3.2d, v2.2d
|
||||
; CHECK-NEXT: stp q4, q5, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x double>, <4 x double>* %a
|
||||
%op2 = load <4 x double>, <4 x double>* %b
|
||||
%op3 = load <4 x double>, <4 x double>* %c
|
||||
%mul = fmul contract <4 x double> %op1, %op2
|
||||
%res = fadd contract <4 x double> %mul, %op3
|
||||
store <4 x double> %res, <4 x double>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
Loading…
x
Reference in New Issue
Block a user