[VPlan] Preserve nusw in createInBoundsPtrAdd (#151549)
Rename createInBoundsPtrAdd to createNoWrapPtrAdd, and preserve nusw as well as inbounds at the callsite.
This commit is contained in:
Ramkumar Ramachandra
GitHub
parent
1b60236200
commit
97f554249c
@ -256,13 +256,15 @@ public:
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new VPInstruction(VPInstruction::PtrAdd, {Ptr, Offset},
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GEPNoWrapFlags::none(), DL, Name));
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}
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VPInstruction *createInBoundsPtrAdd(VPValue *Ptr, VPValue *Offset,
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DebugLoc DL = DebugLoc::getUnknown(),
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const Twine &Name = "") {
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return tryInsertInstruction(
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new VPInstruction(VPInstruction::PtrAdd, {Ptr, Offset},
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GEPNoWrapFlags::inBounds(), DL, Name));
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VPInstruction *createNoWrapPtrAdd(VPValue *Ptr, VPValue *Offset,
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GEPNoWrapFlags GEPFlags,
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DebugLoc DL = DebugLoc::getUnknown(),
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const Twine &Name = "") {
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return tryInsertInstruction(new VPInstruction(
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VPInstruction::PtrAdd, {Ptr, Offset}, GEPFlags, DL, Name));
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}
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VPInstruction *createWidePtrAdd(VPValue *Ptr, VPValue *Offset,
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DebugLoc DL = DebugLoc::getUnknown(),
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const Twine &Name = "") {
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@ -2615,9 +2615,7 @@ void VPlanTransforms::createInterleaveGroups(
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VPValue *OffsetVPV =
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Plan.getOrAddLiveIn(ConstantInt::get(Plan.getContext(), -Offset));
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VPBuilder B(InsertPos);
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Addr = NW.isInBounds()
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? B.createInBoundsPtrAdd(InsertPos->getAddr(), OffsetVPV)
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: B.createPtrAdd(InsertPos->getAddr(), OffsetVPV);
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Addr = B.createNoWrapPtrAdd(InsertPos->getAddr(), OffsetVPV, NW);
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}
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// If the group is reverse, adjust the index to refer to the last vector
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// lane instead of the first. We adjust the index from the first vector
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@ -86,7 +86,7 @@ define void @test_ig_insert_pos_at_end_of_vpbb(ptr noalias %dst, ptr noalias %sr
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr nusw { i16, i16, i16, i16 }, ptr [[SRC]], i64 [[TMP3]], i32 2
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP4]], i32 -4
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr nusw i8, ptr [[TMP4]], i32 -4
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <16 x i16>, ptr [[TMP5]], align 2
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i16> [[WIDE_VEC]], <16 x i16> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
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; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <16 x i16> [[WIDE_VEC]], <16 x i16> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
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@ -185,3 +185,151 @@ loop:
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exit:
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ret void
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}
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define void @nusw_preservation_2(ptr %src, ptr noalias %dst) {
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; CHECK-LABEL: define void @nusw_preservation_2(
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; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP0:%.*]] = or disjoint i64 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr nusw i8, ptr [[SRC]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr nusw i8, ptr [[TMP1]], i32 -1
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i8> [[STRIDED_VEC1]], [[STRIDED_VEC]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr nusw i8, ptr [[DST]], i64 [[INDEX]]
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; CHECK-NEXT: store <4 x i8> [[TMP3]], ptr [[TMP4]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br [[EXIT:label %.*]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv2 = phi i64 [ 0, %entry ], [ %iv2.next, %loop ]
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%or.1 = or disjoint i64 %iv2, 1
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%gep.src.or.1 = getelementptr nusw i8, ptr %src, i64 %or.1
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%load.src.1 = load i8, ptr %gep.src.or.1, align 1
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%gep.src.iv2 = getelementptr nusw i8, ptr %src, i64 %iv2
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%load.src.2 = load i8, ptr %gep.src.iv2, align 1
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%add = add i8 %load.src.1, %load.src.2
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%gep.dst.iv = getelementptr nusw i8, ptr %dst, i64 %iv
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store i8 %add, ptr %gep.dst.iv, align 1
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%iv2.next = add i64 %iv2, 2
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%iv.next = add i64 %iv, 1
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%exit.cond = icmp eq i64 %iv.next, 100
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br i1 %exit.cond, label %exit, label %loop
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exit:
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ret void
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}
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define void @inbounds_preservation_2(ptr %src, ptr noalias %dst) {
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; CHECK-LABEL: define void @inbounds_preservation_2(
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; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP0:%.*]] = or disjoint i64 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 -1
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i8> [[STRIDED_VEC1]], [[STRIDED_VEC]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX]]
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; CHECK-NEXT: store <4 x i8> [[TMP3]], ptr [[TMP4]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br [[EXIT:label %.*]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv2 = phi i64 [ 0, %entry ], [ %iv2.next, %loop ]
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%or.1 = or disjoint i64 %iv2, 1
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%gep.src.or.1 = getelementptr inbounds i8, ptr %src, i64 %or.1
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%load.src.1 = load i8, ptr %gep.src.or.1, align 1
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%gep.src.iv2 = getelementptr inbounds i8, ptr %src, i64 %iv2
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%load.src.2 = load i8, ptr %gep.src.iv2, align 1
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%add = add i8 %load.src.1, %load.src.2
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%gep.dst.iv = getelementptr inbounds i8, ptr %dst, i64 %iv
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store i8 %add, ptr %gep.dst.iv, align 1
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%iv2.next = add i64 %iv2, 2
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%iv.next = add i64 %iv, 1
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%exit.cond = icmp eq i64 %iv.next, 100
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br i1 %exit.cond, label %exit, label %loop
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exit:
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ret void
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}
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define void @nuw_drop_2(ptr %src, ptr noalias %dst) {
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; CHECK-LABEL: define void @nuw_drop_2(
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; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP0:%.*]] = or disjoint i64 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr nuw i8, ptr [[SRC]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 -1
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i8>, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x i8> [[WIDE_VEC]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i8> [[STRIDED_VEC1]], [[STRIDED_VEC]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr nuw i8, ptr [[DST]], i64 [[INDEX]]
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; CHECK-NEXT: store <4 x i8> [[TMP3]], ptr [[TMP4]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br [[EXIT:label %.*]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv2 = phi i64 [ 0, %entry ], [ %iv2.next, %loop ]
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%or.1 = or disjoint i64 %iv2, 1
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%gep.src.or.1 = getelementptr nuw i8, ptr %src, i64 %or.1
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%load.src.1 = load i8, ptr %gep.src.or.1, align 1
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%gep.src.iv2 = getelementptr nuw i8, ptr %src, i64 %iv2
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%load.src.2 = load i8, ptr %gep.src.iv2, align 1
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%add = add i8 %load.src.1, %load.src.2
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%gep.dst.iv = getelementptr nuw i8, ptr %dst, i64 %iv
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store i8 %add, ptr %gep.dst.iv, align 1
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%iv2.next = add i64 %iv2, 2
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%iv.next = add i64 %iv, 1
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%exit.cond = icmp eq i64 %iv.next, 100
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br i1 %exit.cond, label %exit, label %loop
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exit:
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ret void
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}
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