Revert "[ELF] -r: Synthesize R_RISCV_ALIGN at input section start" (#151639)
This reverts commit 6f53f1c8d2bdd13e30da7d1b85ed6a3ae4c4a856. synthesiedAligns is not cleared, leading to stray relocations for unrelated sections. Revert for now.
This commit is contained in:
Fangrui Song
parent
856290d1c1
commit
98164d4706
@ -45,21 +45,7 @@ public:
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uint64_t val) const override;
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void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override;
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bool relaxOnce(int pass) const override;
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template <class ELFT, class RelTy>
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bool synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels);
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template <class ELFT, class RelTy>
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void finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels);
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template <class ELFT>
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bool synthesizeAlignAux(uint64_t &dot, InputSection *sec);
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bool synthesizeAlign(uint64_t &dot, InputSection *sec) override;
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void finalizeRelax(int passes) const override;
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// The following two variables are used by synthesized ALIGN relocations.
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InputSection *baseSec = nullptr;
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// r_offset and r_addend pairs.
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SmallVector<std::pair<uint64_t, uint64_t>, 0> synthesizedAligns;
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};
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} // end anonymous namespace
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@ -970,116 +956,6 @@ bool RISCV::relaxOnce(int pass) const {
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return changed;
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}
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// If the section alignment is >= 4, advance `dot` to insert NOPs and synthesize
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// an ALIGN relocation. Otherwise, return false to use default handling.
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template <class ELFT, class RelTy>
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bool RISCV::synthesizeAlignForInput(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels) {
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if (!baseSec) {
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// Record the first input section with RELAX relocations. We will synthesize
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// ALIGN relocations here.
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for (auto rel : rels) {
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if (rel.getType(false) == R_RISCV_RELAX) {
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baseSec = sec;
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break;
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}
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}
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} else if (sec->addralign >= 4) {
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// If the alignment is >= 4 and the section does not start with an ALIGN
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// relocation, synthesize one.
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bool hasAlignRel = llvm::any_of(rels, [](const RelTy &rel) {
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return rel.r_offset == 0 && rel.getType(false) == R_RISCV_ALIGN;
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});
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if (!hasAlignRel) {
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synthesizedAligns.emplace_back(dot - baseSec->getVA(),
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sec->addralign - 2);
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dot += sec->addralign - 2;
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return true;
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}
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}
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return false;
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}
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// Finalize the relocation section by appending synthesized ALIGN relocations
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// after processing all input sections.
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template <class ELFT, class RelTy>
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void RISCV::finalizeSynthesizeAligns(uint64_t &dot, InputSection *sec,
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Relocs<RelTy> rels) {
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auto *f = cast<ObjFile<ELFT>>(baseSec->file);
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auto shdr = f->template getELFShdrs<ELFT>()[baseSec->relSecIdx];
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// Create a copy of InputSection.
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sec = make<InputSection>(*f, shdr, baseSec->name);
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auto *baseRelSec = cast<InputSection>(f->getSections()[baseSec->relSecIdx]);
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*sec = *baseRelSec;
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baseSec = nullptr;
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// Allocate buffer for original and synthesized relocations in RELA format.
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// If CREL is used, OutputSection::finalizeNonAllocCrel will convert RELA to
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// CREL.
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auto newSize = rels.size() + synthesizedAligns.size();
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auto *relas = makeThreadLocalN<typename ELFT::Rela>(newSize);
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sec->size = newSize * sizeof(typename ELFT::Rela);
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sec->content_ = reinterpret_cast<uint8_t *>(relas);
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sec->type = SHT_RELA;
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// Copy original relocations to the new buffer, potentially converting CREL to
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// RELA.
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for (auto [i, r] : llvm::enumerate(rels)) {
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relas[i].r_offset = r.r_offset;
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relas[i].setSymbolAndType(r.getSymbol(0), r.getType(0), false);
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if constexpr (RelTy::HasAddend)
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relas[i].r_addend = r.r_addend;
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}
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// Append synthesized ALIGN relocations to the buffer.
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for (auto [i, r] : llvm::enumerate(synthesizedAligns)) {
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auto &rela = relas[rels.size() + i];
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rela.r_offset = r.first;
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rela.setSymbolAndType(0, R_RISCV_ALIGN, false);
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rela.r_addend = r.second;
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}
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// Replace the old relocation section with the new one in the output section.
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// addOrphanSections ensures that the output relocation section is processed
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// after osec.
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for (SectionCommand *cmd : sec->getParent()->commands) {
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auto *isd = dyn_cast<InputSectionDescription>(cmd);
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if (!isd)
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continue;
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for (auto *&isec : isd->sections)
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if (isec == baseRelSec)
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isec = sec;
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}
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}
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template <class ELFT>
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bool RISCV::synthesizeAlignAux(uint64_t &dot, InputSection *sec) {
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bool ret = false;
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if (sec) {
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invokeOnRelocs(*sec, ret = synthesizeAlignForInput<ELFT>, dot, sec);
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} else if (baseSec) {
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invokeOnRelocs(*baseSec, finalizeSynthesizeAligns<ELFT>, dot, sec);
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}
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return ret;
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}
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// Without linker relaxation enabled for a particular relocatable file or
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// section, the assembler will not generate R_RISCV_ALIGN relocations for
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// alignment directives. This becomes problematic in a two-stage linking
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// process: ld -r a.o b.o -o ab.o; ld ab.o -o ab. This function synthesizes an
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// R_RISCV_ALIGN relocation at section start when needed.
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//
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// When called with an input section (`sec` is not null): If the section
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// alignment is >= 4, advance `dot` to insert NOPs and synthesize an ALIGN
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// relocation.
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//
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// When called after all input sections are processed (`sec` is null): The
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// output relocation section is updated with all the newly synthesized ALIGN
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// relocations.
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bool RISCV::synthesizeAlign(uint64_t &dot, InputSection *sec) {
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assert(ctx.arg.relocatable);
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if (ctx.arg.is64)
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return synthesizeAlignAux<ELF64LE>(dot, sec);
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return synthesizeAlignAux<ELF32LE>(dot, sec);
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}
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void RISCV::finalizeRelax(int passes) const {
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llvm::TimeTraceScope timeScope("Finalize RISC-V relaxation");
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Log(ctx) << "relaxation passes: " << passes;
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@ -1230,9 +1230,6 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
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if (sec->firstInOverlay)
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state->overlaySize = 0;
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bool synthesizeAlign = ctx.arg.relocatable && ctx.arg.relax &&
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(sec->flags & SHF_EXECINSTR) &&
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ctx.arg.emachine == EM_RISCV;
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// We visited SectionsCommands from processSectionCommands to
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// layout sections. Now, we visit SectionsCommands again to fix
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// section offsets.
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@ -1263,10 +1260,7 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
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if (isa<PotentialSpillSection>(isec))
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continue;
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const uint64_t pos = dot;
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// If synthesized ALIGN may be needed, call maybeSynthesizeAlign and
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// disable the default handling if the return value is true.
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if (!(synthesizeAlign && ctx.target->synthesizeAlign(dot, isec)))
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dot = alignToPowerOf2(dot, isec->addralign);
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dot = alignToPowerOf2(dot, isec->addralign);
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isec->outSecOff = dot - sec->addr;
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dot += isec->getSize();
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@ -1282,12 +1276,6 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
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if (ctx.in.relroPadding && sec == ctx.in.relroPadding->getParent())
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expandOutputSection(alignToPowerOf2(dot, ctx.arg.commonPageSize) - dot);
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if (synthesizeAlign) {
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const uint64_t pos = dot;
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ctx.target->synthesizeAlign(dot, nullptr);
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expandOutputSection(dot - pos);
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}
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// Non-SHF_ALLOC sections do not affect the addresses of other OutputSections
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// as they are not part of the process image.
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if (!(sec->flags & SHF_ALLOC)) {
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@ -889,17 +889,9 @@ void OutputSection::sortInitFini() {
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std::array<uint8_t, 4> OutputSection::getFiller(Ctx &ctx) {
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if (filler)
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return *filler;
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if (!(flags & SHF_EXECINSTR))
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return {0, 0, 0, 0};
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if (ctx.arg.relocatable && ctx.arg.emachine == EM_RISCV) {
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// See RISCV::maybeSynthesizeAlign: Synthesized NOP bytes and ALIGN
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// relocations might be needed between two input sections. Use a NOP for the
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// filler.
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if (ctx.arg.eflags & EF_RISCV_RVC)
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return {1, 0, 1, 0};
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return {0x13, 0, 0, 0};
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}
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return ctx.target->trapInstr;
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if (flags & SHF_EXECINSTR)
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return ctx.target->trapInstr;
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return {0, 0, 0, 0};
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}
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void OutputSection::checkDynRelAddends(Ctx &ctx) {
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@ -96,9 +96,6 @@ public:
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// Do a linker relaxation pass and return true if we changed something.
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virtual bool relaxOnce(int pass) const { return false; }
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virtual bool synthesizeAlign(uint64_t &dot, InputSection *sec) {
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return false;
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}
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// Do finalize relaxation after collecting relaxation infos.
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virtual void finalizeRelax(int passes) const {}
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@ -1,130 +0,0 @@
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# RUN: rm -rf %t && split-file %s %t && cd %t
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax a.s -o ac.o
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax b.s -o bc.o
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax b1.s -o b1c.o
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax c.s -o cc.o
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c d.s -o dc.o
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## No RELAX. Don't synthesize ALIGN.
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# RUN: ld.lld -r bc.o dc.o -o bd.ro
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# RUN: llvm-readelf -r bd.ro | FileCheck %s --check-prefix=NOREL
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# NOREL: no relocations
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# RUN: ld.lld -r bc.o bc.o ac.o bc.o b1c.o cc.o dc.o -o out.ro
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# RUN: llvm-objdump -dr -M no-aliases out.ro | FileCheck %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax a.s -o a.o
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax b.s -o b.o
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax d.s -o d.o
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# RUN: ld.lld -r a.o b.o d.o -o out0.ro
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# RUN: ld.lld -Ttext=0x10000 out0.ro -o out0
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# RUN: llvm-objdump -dr -M no-aliases out0 | FileCheck %s --check-prefix=CHECK1
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# CHECK: <b0>:
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# CHECK-NEXT: 0: 00158513 addi a0, a1, 0x1
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# CHECK-NEXT: 4: 0001 c.nop
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# CHECK-NEXT: 6: 0001 c.nop
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# CHECK-EMPTY:
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# CHECK-NEXT: <b0>:
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# CHECK-NEXT: 8: 00158513 addi a0, a1, 0x1
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# CHECK-EMPTY:
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# CHECK-NEXT: <_start>:
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# CHECK-NEXT: c: 00000097 auipc ra, 0x0
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# CHECK-NEXT: 000000000000000c: R_RISCV_CALL_PLT foo
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# CHECK-NEXT: 000000000000000c: R_RISCV_RELAX *ABS*
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# CHECK-NEXT: 10: 000080e7 jalr ra, 0x0(ra) <_start>
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# CHECK-NEXT: 14: 0001 c.nop
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# CHECK-NEXT: 0000000000000014: R_RISCV_ALIGN *ABS*+0x6
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# CHECK-NEXT: 16: 0001 c.nop
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# CHECK-NEXT: 18: 0001 c.nop
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# CHECK-EMPTY:
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# CHECK-NEXT: <b0>:
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# CHECK-NEXT: 1a: 00158513 addi a0, a1, 0x1
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# CHECK-NEXT: 1e: 0001 c.nop
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# CHECK-NEXT: 20: 0001 c.nop
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# CHECK-NEXT: 0000000000000020: R_RISCV_ALIGN *ABS*+0x6
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# CHECK-NEXT: 22: 0001 c.nop
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# CHECK-NEXT: 24: 00000013 addi zero, zero, 0x0
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# CHECK-EMPTY:
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# CHECK-NEXT: <b0>:
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# CHECK-NEXT: 28: 00158513 addi a0, a1, 0x1
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# CHECK-EMPTY:
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# CHECK-NEXT: <c0>:
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# CHECK-NEXT: 2c: 00000097 auipc ra, 0x0
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# CHECK-NEXT: 000000000000002c: R_RISCV_CALL_PLT foo
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# CHECK-NEXT: 000000000000002c: R_RISCV_RELAX *ABS*
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# CHECK-NEXT: 30: 000080e7 jalr ra, 0x0(ra) <c0>
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# CHECK-NEXT: 34: 0001 c.nop
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# CHECK-NEXT: 0000000000000034: R_RISCV_ALIGN *ABS*+0x2
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# CHECK-EMPTY:
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# CHECK-NEXT: <d0>:
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# CHECK-NEXT: 36: 00258513 addi a0, a1, 0x2
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# CHECK1: <_start>:
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# CHECK1-NEXT: 010000ef jal ra, 0x10010 <foo>
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# CHECK1-NEXT: 00000013 addi zero, zero, 0x0
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# CHECK1-EMPTY:
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# CHECK1-NEXT: <b0>:
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# CHECK1-NEXT: 00158513 addi a0, a1, 0x1
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# CHECK1-EMPTY:
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# CHECK1-NEXT: <d0>:
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# CHECK1-NEXT: 00258513 addi a0, a1, 0x2
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## Test CREL.
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax --crel a.s -o acrel.o
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# RUN: ld.lld -r acrel.o bc.o -o out1.ro
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# RUN: llvm-objdump -dr -M no-aliases out1.ro | FileCheck %s --check-prefix=CHECK2
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# CHECK2: <_start>:
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# CHECK2-NEXT: 0: 00000097 auipc ra, 0x0
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# CHECK2-NEXT: 0000000000000000: R_RISCV_CALL_PLT foo
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# CHECK2-NEXT: 0000000000000000: R_RISCV_RELAX *ABS*
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# CHECK2-NEXT: 4: 000080e7 jalr ra, 0x0(ra) <_start>
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# CHECK2-NEXT: 8: 0001 c.nop
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# CHECK2-NEXT: 0000000000000008: R_RISCV_ALIGN *ABS*+0x6
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# CHECK2-NEXT: a: 0001 c.nop
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# CHECK2-NEXT: c: 0001 c.nop
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# CHECK2-EMPTY:
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# CHECK2-NEXT: <b0>:
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# CHECK2-NEXT: e: 00158513 addi a0, a1, 0x1
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#--- a.s
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.globl _start
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_start:
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call foo
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.section .text1,"ax"
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.globl foo
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foo:
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#--- b.s
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## Needs synthesized ALIGN
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.option push
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.option norelax
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.balign 8
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b0:
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addi a0, a1, 1
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.option pop
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#--- b1.s
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.option push
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.option norelax
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.reloc ., R_RISCV_ALIGN, 6
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addi x0, x0, 0
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c.nop
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.balign 8
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b0:
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addi a0, a1, 1
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.option pop
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#--- c.s
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.balign 2
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c0:
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call foo
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#--- d.s
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## Needs synthesized ALIGN
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.balign 4
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d0:
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addi a0, a1, 2
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