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AMDGPU: Use srcvalue and delete Ignore complex pattern (#161359)

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Petar Avramovic 2025-09-30 16:18:51 +02:00 committed by GitHub
parent 4a873d58df
commit 98d43ef2d8
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GPG Key ID: B5690EEEBB952194
7 changed files with 1 additions and 22 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPUGISel.td
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@ -13,10 +13,6 @@
include "AMDGPU.td"
include "AMDGPUCombine.td"
def gi_ignore :
GIComplexOperandMatcher<s32, "selectIgnore">,
GIComplexPatternEquiv<Ignore>;
def sd_vsrc0 : ComplexPattern<i32, 1, "">;
def gi_vsrc0 :
GIComplexOperandMatcher<s32, "selectVSRC0">,

2
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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@ -4312,8 +4312,6 @@ bool AMDGPUDAGToDAGISel::SelectBITOP3(SDValue In, SDValue &Src0, SDValue &Src1,
return true;
}
bool AMDGPUDAGToDAGISel::SelectIgnore(SDValue In) const { return true; }
SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
if (In.isUndef())
return CurDAG->getUNDEF(MVT::i32);

2
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
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@ -305,8 +305,6 @@ private:
void SelectWAVE_ADDRESS(SDNode *N);
void SelectSTACKRESTORE(SDNode *N);
bool SelectIgnore(SDValue In) const;
protected:
// Include the pieces autogenerated from the target description.
#include "AMDGPUGenDAGISel.inc"

8
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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@ -4266,14 +4266,6 @@ Register AMDGPUInstructionSelector::copyToVGPRIfSrcFolded(
return Src;
}
InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectIgnore(MachineOperand &Root) const {
// Don't render anything.
ComplexRendererFns Renderers;
Renderers.emplace();
return Renderers;
}
///
/// This will select either an SGPR or VGPR operand and will save us from
/// having to write an extra tablegen pattern.

3
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
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@ -166,9 +166,6 @@ private:
MachineOperand Root, MachineInstr *InsertPt,
bool ForceVGPR = false) const;
InstructionSelector::ComplexRendererFns
selectIgnore(MachineOperand &Root) const;
InstructionSelector::ComplexRendererFns
selectVCSRC(MachineOperand &Root) const;

2
llvm/lib/Target/AMDGPU/SIInstrInfo.td
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@ -1710,8 +1710,6 @@ def VOP3PMadMixBF16Mods : ComplexPattern<untyped, 2, "SelectVOP3PMadMixBF16Mods"
def VINTERPMods : ComplexPattern<untyped, 2, "SelectVINTERPMods">;
def VINTERPModsHi : ComplexPattern<untyped, 2, "SelectVINTERPModsHi">;
def Ignore : ComplexPattern<untyped, 0, "SelectIgnore">;
//===----------------------------------------------------------------------===//
// SI assembler operands
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/AMDGPU/SOPInstructions.td
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@ -1617,7 +1617,7 @@ def S_BARRIER_WAIT : SOPP_Pseudo <"s_barrier_wait", (ins i16imm:$simm16), "$simm
}
def S_BARRIER_LEAVE : SOPP_Pseudo <"s_barrier_leave",
(ins), "", [(int_amdgcn_s_barrier_leave (Ignore))] > {
(ins), "", [(int_amdgcn_s_barrier_leave (i16 srcvalue))] > {
let SchedRW = [WriteBarrier];
let simm16 = 0;
let fixed_imm = 1;