[LoongArch] Break MUL into SLLI and SUB or ADD
Further, after MUL is decomposed, use ALSL instead of SLLI and ADD Differential Revision: https://reviews.llvm.org/D140282
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gonglingqin
parent
4a2807d248
commit
9aa5de9746
@ -26,6 +26,7 @@
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#include "llvm/IR/IntrinsicsLoongArch.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/KnownBits.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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@ -2858,3 +2859,24 @@ LoongArchTargetLowering::getRegisterByName(const char *RegName, LLT VT,
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StringRef(RegName) + "\"."));
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return Reg;
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}
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bool LoongArchTargetLowering::decomposeMulByConstant(LLVMContext &Context,
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EVT VT, SDValue C) const {
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// TODO: Support vectors.
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if (!VT.isScalarInteger())
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return false;
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// Omit the optimization if the data size exceeds GRLen.
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if (VT.getSizeInBits() > Subtarget.getGRLen())
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return false;
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// Break MUL into (SLLI + ADD/SUB) or ALSL.
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if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
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const APInt &Imm = ConstNode->getAPIntValue();
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if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
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(1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2())
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return true;
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}
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return false;
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}
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@ -169,6 +169,9 @@ public:
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
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SDValue C) const override;
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private:
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/// Target-specific function used to lower LoongArch calling conventions.
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typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
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@ -128,19 +128,16 @@ entry:
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ret i64 %zext
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}
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;; Check that alsl.w or alsl.d is not emitted.
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define i8 @mul_add_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: mul_add_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 3
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 1
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 3
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 1
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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@ -192,12 +189,14 @@ entry:
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define i64 @mul_add_i64(i64 signext %a, i64 signext %b) nounwind {
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; LA32-LABEL: mul_add_i64:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: slli.w $a4, $a1, 4
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; LA32-NEXT: sub.w $a1, $a4, $a1
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; LA32-NEXT: ori $a4, $zero, 15
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; LA32-NEXT: mul.w $a1, $a1, $a4
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; LA32-NEXT: mulh.wu $a5, $a0, $a4
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; LA32-NEXT: add.w $a1, $a5, $a1
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; LA32-NEXT: mulh.wu $a4, $a0, $a4
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; LA32-NEXT: add.w $a1, $a4, $a1
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; LA32-NEXT: add.w $a1, $a3, $a1
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; LA32-NEXT: mul.w $a0, $a0, $a4
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; LA32-NEXT: slli.w $a3, $a0, 4
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; LA32-NEXT: sub.w $a0, $a3, $a0
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; LA32-NEXT: add.w $a0, $a2, $a0
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; LA32-NEXT: sltu $a2, $a0, $a2
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; LA32-NEXT: add.w $a1, $a1, $a2
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@ -205,8 +204,8 @@ define i64 @mul_add_i64(i64 signext %a, i64 signext %b) nounwind {
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;
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; LA64-LABEL: mul_add_i64:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 15
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: slli.d $a2, $a0, 4
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; LA64-NEXT: sub.d $a0, $a2, $a0
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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@ -218,16 +217,14 @@ entry:
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define i32 @mul_add_zext_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: mul_add_zext_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 5
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: andi $a0, $a0, 255
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_zext_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 5
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: andi $a0, $a0, 255
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; LA64-NEXT: ret
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@ -241,16 +238,16 @@ entry:
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define i32 @mul_add_zext_i16(i16 signext %a, i16 signext %b) nounwind {
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; LA32-LABEL: mul_add_zext_i16:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 15
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: slli.w $a2, $a0, 4
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; LA32-NEXT: sub.w $a0, $a2, $a0
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_zext_i16:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 15
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: slli.d $a2, $a0, 4
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; LA64-NEXT: sub.d $a0, $a2, $a0
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
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; LA64-NEXT: ret
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@ -261,20 +258,17 @@ entry:
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ret i32 %zext
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}
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;; Check that alsl.wu is not emitted.
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define i64 @mul_add_zext_i32(i32 signext %a, i32 signext %b) nounwind {
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; LA32-LABEL: mul_add_zext_i32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 5
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: move $a1, $zero
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_zext_i32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 5
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
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; LA64-NEXT: ret
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@ -284,3 +278,86 @@ entry:
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%zext = zext i32 %add to i64
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ret i64 %zext
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}
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define i8 @alsl_neg_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: alsl_neg_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 1
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; LA32-NEXT: sub.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_neg_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 1
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; LA64-NEXT: sub.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i8 %a, -3
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%add = add nsw i8 %b, %mul
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ret i8 %add
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}
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define i16 @alsl_neg_i16(i16 signext %a, i16 signext %b) nounwind {
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; LA32-LABEL: alsl_neg_i16:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 2
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; LA32-NEXT: sub.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_neg_i16:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 2
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; LA64-NEXT: sub.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i16 %a, -5
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%add = add nsw i16 %b, %mul
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ret i16 %add
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}
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define i32 @alsl_neg_i32(i32 signext %a, i32 signext %b) nounwind {
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; LA32-LABEL: alsl_neg_i32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 3
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; LA32-NEXT: sub.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_neg_i32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 3
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; LA64-NEXT: sub.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i32 %a, -9
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%add = add nsw i32 %b, %mul
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ret i32 %add
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}
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define i64 @mul_add_neg_i64(i64 signext %a, i64 signext %b) nounwind {
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; LA32-LABEL: mul_add_neg_i64:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: slli.w $a4, $a1, 4
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; LA32-NEXT: sub.w $a1, $a1, $a4
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; LA32-NEXT: addi.w $a4, $zero, -15
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; LA32-NEXT: mulh.wu $a4, $a0, $a4
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; LA32-NEXT: sub.w $a4, $a4, $a0
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; LA32-NEXT: add.w $a1, $a4, $a1
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; LA32-NEXT: add.w $a1, $a3, $a1
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; LA32-NEXT: slli.w $a3, $a0, 4
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; LA32-NEXT: sub.w $a0, $a0, $a3
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; LA32-NEXT: add.w $a0, $a2, $a0
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; LA32-NEXT: sltu $a2, $a0, $a2
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; LA32-NEXT: add.w $a1, $a1, $a2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_neg_i64:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: slli.d $a2, $a0, 4
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; LA64-NEXT: sub.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i64 %a, -15
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%add = add nsw i64 %b, %mul
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ret i64 %add
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}
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@ -105,16 +105,15 @@ define i64 @mul_p5(i64 %a) {
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; LA32-LABEL: mul_p5:
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; LA32: # %bb.0:
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; LA32-NEXT: ori $a2, $zero, 5
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; LA32-NEXT: mul.w $a1, $a1, $a2
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; LA32-NEXT: mulh.wu $a3, $a0, $a2
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; LA32-NEXT: add.w $a1, $a3, $a1
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: mulh.wu $a2, $a0, $a2
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; LA32-NEXT: alsl.w $a1, $a1, $a1, 2
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; LA32-NEXT: add.w $a1, $a2, $a1
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; LA32-NEXT: alsl.w $a0, $a0, $a0, 2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_p5:
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; LA64: # %bb.0:
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; LA64-NEXT: ori $a1, $zero, 5
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; LA64-NEXT: mul.d $a0, $a0, $a1
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; LA64-NEXT: alsl.d $a0, $a0, $a0, 2
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; LA64-NEXT: ret
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%1 = mul i64 %a, 5
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ret i64 %1
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