Revert "[OpenMP] Move OpenMP implicit argument to the end and reformat" (#186309)
Reverts llvm/llvm-project#185989
This commit is contained in:
theRonShark
GitHub
parent
a8c6cce956
commit
9b61ff210f
@ -10639,11 +10639,8 @@ emitTargetCallFallback(CGOpenMPRuntime *OMPRuntime, llvm::Function *OutlinedFn,
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CapturedVars.clear();
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CGF.GenerateOpenMPCapturedVars(CS, CapturedVars);
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}
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llvm::SmallVector<llvm::Value *, 16> Args(CapturedVars.begin(),
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CapturedVars.end());
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Args.push_back(llvm::Constant::getNullValue(CGF.Builder.getPtrTy()));
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OMPRuntime->emitOutlinedFunctionCall(CGF, D.getBeginLoc(), OutlinedFn,
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Args);
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CapturedVars);
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}
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}
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@ -10880,22 +10877,6 @@ static void emitTargetCallKernelLaunch(
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CGOpenMPRuntime::TargetDataInfo Info;
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genMapInfo(D, CGF, CS, CapturedVars, OMPBuilder, CombinedInfo);
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// Append a null entry for the implicit dyn_ptr argument.
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using OpenMPOffloadMappingFlags = llvm::omp::OpenMPOffloadMappingFlags;
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auto *NullPtr = llvm::Constant::getNullValue(CGF.Builder.getPtrTy());
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CombinedInfo.BasePointers.push_back(NullPtr);
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CombinedInfo.Pointers.push_back(NullPtr);
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CombinedInfo.DevicePointers.push_back(
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llvm::OpenMPIRBuilder::DeviceInfoTy::None);
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CombinedInfo.Sizes.push_back(CGF.Builder.getInt64(0));
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CombinedInfo.Types.push_back(OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM |
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OpenMPOffloadMappingFlags::OMP_MAP_LITERAL);
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if (!CombinedInfo.Names.empty())
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CombinedInfo.Names.push_back(NullPtr);
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CombinedInfo.Exprs.push_back(nullptr);
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CombinedInfo.Mappers.push_back(nullptr);
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CombinedInfo.DevicePtrDecls.push_back(nullptr);
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emitOffloadingArraysAndArgs(CGF, CombinedInfo, Info, OMPBuilder,
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/*IsNonContiguous=*/true, /*ForEndCall=*/false);
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@ -4473,12 +4473,12 @@ static SmallVector<SemaOpenMP::CapturedParamNameType>
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getTargetRegionParams(Sema &SemaRef) {
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ASTContext &Context = SemaRef.getASTContext();
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SmallVector<SemaOpenMP::CapturedParamNameType> Params;
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if (SemaRef.getLangOpts().OpenMPIsTargetDevice) {
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QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict();
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Params.push_back(std::make_pair(StringRef("dyn_ptr"), VoidPtrTy));
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}
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// __context with shared vars
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Params.push_back(std::make_pair(StringRef(), QualType()));
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// Implicit dyn_ptr argument, appended as the last parameter. Present on both
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// host and device so argument counts match without runtime manipulation.
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QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict();
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Params.push_back(std::make_pair(StringRef("dyn_ptr"), VoidPtrTy));
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return Params;
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}
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@ -68,7 +68,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:4:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:5:23> col:23 implicit 'int'
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@ -127,7 +126,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:4:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:5:23> col:23 implicit 'int'
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@ -201,7 +199,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:11:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:10:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:11:23> col:23 implicit 'int'
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@ -294,7 +291,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:11:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:10:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:11:23> col:23 implicit 'int'
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@ -389,7 +385,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:18:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:17:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:18:23> col:23 implicit 'int'
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@ -482,7 +477,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:18:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:17:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:18:23> col:23 implicit 'int'
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@ -577,7 +571,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:25:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:26:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:24:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:25:23> col:23 implicit 'int'
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@ -670,7 +663,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:25:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:26:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:24:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:25:23> col:23 implicit 'int'
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@ -782,7 +774,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:33:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:31:1) *const restrict'
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// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:32:23> col:23 implicit 'int'
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@ -909,7 +900,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:33:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for-simd.c:31:1) *const restrict'
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// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:32:23> col:23 implicit 'int'
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@ -68,7 +68,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:4:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:5:3> col:3 implicit 'int'
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@ -127,7 +126,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:4:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:5:3> col:3 implicit 'int'
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@ -201,7 +199,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:11:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:10:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:11:3> col:3 implicit 'int'
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@ -294,7 +291,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:11:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:10:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:11:3> col:3 implicit 'int'
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@ -389,7 +385,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:18:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:17:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:18:3> col:3 implicit 'int'
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@ -482,7 +477,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:18:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:17:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:18:3> col:3 implicit 'int'
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@ -577,7 +571,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:25:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:26:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:24:1) *const restrict'
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// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:25:3> col:3 implicit 'int'
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@ -670,7 +663,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:25:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:26:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:24:1) *const restrict'
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// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
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// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
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// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
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// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:25:3> col:3 implicit 'int'
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@ -782,7 +774,6 @@ void test_five(int x, int y, int z) {
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// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:33:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
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// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:32:3> col:3 implicit 'int'
|
||||
@ -909,7 +900,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:33:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel-for.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:32:3> col:3 implicit 'int'
|
||||
|
||||
@ -20,7 +20,6 @@ void test(void) {
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .bound_tid. 'const int *const restrict'
|
||||
// CHECK-NEXT: | | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
@ -45,7 +44,6 @@ void test(void) {
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .bound_tid. 'const int *const restrict'
|
||||
// CHECK-NEXT: | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-parallel.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
|
||||
@ -60,7 +60,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} <col:26> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | | | `-NullStmt {{.*}} <line:6:5>
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | `-VarDecl {{.*}} <line:5:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
@ -90,7 +89,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <col:26> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | `-NullStmt {{.*}} <line:6:5>
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | `-VarDecl {{.*}} <line:5:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int'
|
||||
@ -132,7 +130,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} <col:28> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | | | `-NullStmt {{.*}} <line:13:7>
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-VarDecl {{.*}} <line:11:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | `-VarDecl {{.*}} <line:12:10, col:18> col:14 used i 'int' cinit
|
||||
@ -179,7 +176,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <col:28> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | `-NullStmt {{.*}} <line:13:7>
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-VarDecl {{.*}} <line:11:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | `-VarDecl {{.*}} <line:12:10, col:18> col:14 used i 'int' cinit
|
||||
@ -228,7 +224,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} <col:28> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | | | `-NullStmt {{.*}} <line:20:7>
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-VarDecl {{.*}} <line:18:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | `-VarDecl {{.*}} <line:19:10, col:18> col:14 used i 'int' cinit
|
||||
@ -275,7 +270,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <col:28> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | `-NullStmt {{.*}} <line:20:7>
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-VarDecl {{.*}} <line:18:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | `-VarDecl {{.*}} <line:19:10, col:18> col:14 used i 'int' cinit
|
||||
@ -324,7 +318,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-DeclRefExpr {{.*}} <col:28> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | | | `-NullStmt {{.*}} <line:27:7>
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-VarDecl {{.*}} <line:25:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | `-VarDecl {{.*}} <line:26:10, col:18> col:14 used i 'int' cinit
|
||||
@ -371,7 +364,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <col:28> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | `-NullStmt {{.*}} <line:27:7>
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-VarDecl {{.*}} <line:25:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | `-VarDecl {{.*}} <line:26:10, col:18> col:14 used i 'int' cinit
|
||||
@ -434,7 +426,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:30> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | | | `-NullStmt {{.*}} <line:35:9>
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-VarDecl {{.*}} <line:32:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | |-VarDecl {{.*}} <line:33:10, col:18> col:14 used i 'int' cinit
|
||||
@ -498,7 +489,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:30> 'int' lvalue Var {{.*}} 'i' 'int'
|
||||
// CHECK-NEXT: | | `-NullStmt {{.*}} <line:35:9>
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-simd.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-VarDecl {{.*}} <line:32:8, col:16> col:12 used i 'int' cinit
|
||||
// CHECK-NEXT: | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | |-VarDecl {{.*}} <line:33:10, col:18> col:14 used i 'int' cinit
|
||||
|
||||
@ -101,7 +101,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:5:23> col:23 implicit 'int'
|
||||
@ -226,7 +225,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:5:23> col:23 implicit 'int'
|
||||
@ -383,7 +381,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:11:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:11:23> col:23 implicit 'int'
|
||||
@ -576,7 +573,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:11:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:11:23> col:23 implicit 'int'
|
||||
@ -771,7 +767,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:18:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:18:23> col:23 implicit 'int'
|
||||
@ -964,7 +959,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:18:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:18:23> col:23 implicit 'int'
|
||||
@ -1159,7 +1153,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:25:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:26:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:25:23> col:23 implicit 'int'
|
||||
@ -1352,7 +1345,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:25:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:26:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:25:23> col:23 implicit 'int'
|
||||
@ -1581,7 +1573,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:33:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:32:23> col:23 implicit 'int'
|
||||
@ -1842,7 +1833,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:33:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for-simd.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:32:23> col:23 implicit 'int'
|
||||
|
||||
@ -101,7 +101,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:5:3> col:3 implicit 'int'
|
||||
@ -226,7 +225,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:5:3> col:3 implicit 'int'
|
||||
@ -383,7 +381,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:11:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:11:3> col:3 implicit 'int'
|
||||
@ -576,7 +573,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:11:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:11:3> col:3 implicit 'int'
|
||||
@ -771,7 +767,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:18:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:18:3> col:3 implicit 'int'
|
||||
@ -964,7 +959,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:18:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:18:3> col:3 implicit 'int'
|
||||
@ -1159,7 +1153,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:25:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:26:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:25:3> col:3 implicit 'int'
|
||||
@ -1352,7 +1345,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:25:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:26:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:25:3> col:3 implicit 'int'
|
||||
@ -1581,7 +1573,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:33:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:32:3> col:3 implicit 'int'
|
||||
@ -1842,7 +1833,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:33:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-parallel-for.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:32:3> col:3 implicit 'int'
|
||||
|
||||
@ -68,7 +68,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:5:23> col:23 implicit 'int'
|
||||
@ -127,7 +126,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:5:23> col:23 implicit 'int'
|
||||
@ -201,7 +199,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:11:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:11:23> col:23 implicit 'int'
|
||||
@ -294,7 +291,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:11:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:11:23> col:23 implicit 'int'
|
||||
@ -389,7 +385,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:18:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:18:23> col:23 implicit 'int'
|
||||
@ -482,7 +477,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:18:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:18:23> col:23 implicit 'int'
|
||||
@ -577,7 +571,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:25:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:26:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:25:23> col:23 implicit 'int'
|
||||
@ -670,7 +663,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:25:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:26:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:25:23> col:23 implicit 'int'
|
||||
@ -782,7 +774,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:33:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:32:23> col:23 implicit 'int'
|
||||
@ -909,7 +900,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:33:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute-simd.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:32:23> col:23 implicit 'int'
|
||||
|
||||
@ -68,7 +68,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:5:3> col:3 implicit 'int'
|
||||
@ -127,7 +126,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:5:3> col:3 implicit 'int'
|
||||
@ -201,7 +199,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:11:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:11:3> col:3 implicit 'int'
|
||||
@ -294,7 +291,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:11:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:12:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:10:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:10:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:11:3> col:3 implicit 'int'
|
||||
@ -389,7 +385,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:18:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:18:3> col:3 implicit 'int'
|
||||
@ -482,7 +477,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:18:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:19:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:17:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:17:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:18:3> col:3 implicit 'int'
|
||||
@ -577,7 +571,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:25:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:26:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:25:3> col:3 implicit 'int'
|
||||
@ -670,7 +663,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:25:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:26:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:24:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:24:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:25:3> col:3 implicit 'int'
|
||||
@ -782,7 +774,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:33:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:32:3> col:3 implicit 'int'
|
||||
@ -909,7 +900,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:33:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:34:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:31:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams-distribute.c:31:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:32:3> col:3 implicit 'int'
|
||||
|
||||
@ -20,7 +20,6 @@ void test(void) {
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .bound_tid. 'const int *const restrict'
|
||||
// CHECK-NEXT: | | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
@ -45,7 +44,6 @@ void test(void) {
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .bound_tid. 'const int *const restrict'
|
||||
// CHECK-NEXT: | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target-teams.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: |-RecordDecl {{.*}} <col:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
|
||||
@ -14,8 +14,7 @@ void test(void) {
|
||||
// CHECK-NEXT: |-CapturedStmt {{.*}} <col:3>
|
||||
// CHECK-NEXT: | `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
// CHECK-NEXT: | |-NullStmt {{.*}} <col:3>
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | `-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: |-AlwaysInlineAttr {{.*}} <<invalid sloc>> Implicit __forceinline
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .global_tid. 'const int'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .part_id. 'const int *const restrict'
|
||||
@ -27,5 +26,4 @@ void test(void) {
|
||||
// CHECK-NEXT: | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
// CHECK-NEXT: |-NullStmt {{.*}} <line:5:3>
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: `-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-target.c:4:1) *const restrict'
|
||||
|
||||
@ -106,7 +106,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:6:23> col:23 implicit 'int &'
|
||||
@ -247,7 +246,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:6:23> col:23 implicit 'int &'
|
||||
@ -419,7 +417,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:13:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:13:23> col:23 implicit 'int &'
|
||||
@ -625,7 +622,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:13:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:13:23> col:23 implicit 'int &'
|
||||
@ -833,7 +829,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:21:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:21:23> col:23 implicit 'int &'
|
||||
@ -1043,7 +1038,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:21:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:21:23> col:23 implicit 'int &'
|
||||
@ -1251,7 +1245,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:29:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:30:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:29:23> col:23 implicit 'int &'
|
||||
@ -1480,7 +1473,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:29:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:30:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:29:23> col:23 implicit 'int &'
|
||||
@ -1740,7 +1732,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:38:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:37:23> col:23 implicit 'int &'
|
||||
@ -2034,7 +2025,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:38:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for-simd.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:37:23> col:23 implicit 'int &'
|
||||
|
||||
@ -106,7 +106,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:6:3> col:3 implicit 'int &'
|
||||
@ -247,7 +246,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:6:3> col:3 implicit 'int &'
|
||||
@ -419,7 +417,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:13:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:13:3> col:3 implicit 'int &'
|
||||
@ -625,7 +622,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:13:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:13:3> col:3 implicit 'int &'
|
||||
@ -833,7 +829,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:21:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:21:3> col:3 implicit 'int &'
|
||||
@ -1043,7 +1038,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:21:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:21:3> col:3 implicit 'int &'
|
||||
@ -1251,7 +1245,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:29:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:30:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:29:3> col:3 implicit 'int &'
|
||||
@ -1480,7 +1473,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:29:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:30:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:29:3> col:3 implicit 'int &'
|
||||
@ -1740,7 +1732,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:38:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:37:3> col:3 implicit 'int &'
|
||||
@ -2034,7 +2025,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:38:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-parallel-for.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:37:3> col:3 implicit 'int &'
|
||||
|
||||
@ -74,7 +74,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:6:23> col:23 implicit 'int &'
|
||||
@ -151,7 +150,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:6:23> col:23 implicit 'int &'
|
||||
@ -243,7 +241,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:13:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:13:23> col:23 implicit 'int &'
|
||||
@ -353,7 +350,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:13:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:13:23> col:23 implicit 'int &'
|
||||
@ -465,7 +461,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:21:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:21:23> col:23 implicit 'int &'
|
||||
@ -579,7 +574,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:21:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:21:23> col:23 implicit 'int &'
|
||||
@ -691,7 +685,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:29:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:30:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:29:23> col:23 implicit 'int &'
|
||||
@ -824,7 +817,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:29:23> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:30:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:29:23> col:23 implicit 'int &'
|
||||
@ -972,7 +964,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:38:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:37:23> col:23 implicit 'int &'
|
||||
@ -1138,7 +1129,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:38:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute-simd.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:37:23> col:23 implicit 'int &'
|
||||
|
||||
@ -74,7 +74,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | `-FieldDecl {{.*}} <line:6:3> col:3 implicit 'int &'
|
||||
@ -151,7 +150,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | `-IntegerLiteral {{.*}} <col:16> 'int' 0
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <col:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | `-FieldDecl {{.*}} <line:6:3> col:3 implicit 'int &'
|
||||
@ -243,7 +241,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:13:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:13:3> col:3 implicit 'int &'
|
||||
@ -353,7 +350,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:13:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:14:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:11:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:11:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:12:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:13:3> col:3 implicit 'int &'
|
||||
@ -465,7 +461,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:21:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:21:3> col:3 implicit 'int &'
|
||||
@ -579,7 +574,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:21:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:22:25> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:19:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:19:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:20:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:21:3> col:3 implicit 'int &'
|
||||
@ -691,7 +685,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | | |-DeclRefExpr {{.*}} <line:29:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | | `-DeclRefExpr {{.*}} <line:30:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | | |-FieldDecl {{.*}} <line:29:3> col:3 implicit 'int &'
|
||||
@ -824,7 +817,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | |-DeclRefExpr {{.*}} <line:29:3> 'int' lvalue ParmVar {{.*}} 'x' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | `-DeclRefExpr {{.*}} <line:30:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <line:27:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:27:1) *const restrict'
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | |-RecordDecl {{.*}} <line:28:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | |-FieldDecl {{.*}} <line:29:3> col:3 implicit 'int &'
|
||||
@ -972,7 +964,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | | | |-DeclRefExpr {{.*}} <line:38:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | | | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | | | |-FieldDecl {{.*}} <line:37:3> col:3 implicit 'int &'
|
||||
@ -1138,7 +1129,6 @@ void test_five(int x, int y, int z) {
|
||||
// CHECK-NEXT: | | |-DeclRefExpr {{.*}} <line:38:5> 'int' lvalue ParmVar {{.*}} 'y' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | | `-DeclRefExpr {{.*}} <line:39:27> 'int' lvalue ParmVar {{.*}} 'z' 'int' refers_to_enclosing_variable_or_capture
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:35:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams-distribute.c:35:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <line:36:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | |-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | | |-FieldDecl {{.*}} <line:37:3> col:3 implicit 'int &'
|
||||
|
||||
@ -22,7 +22,6 @@ void test(void) {
|
||||
// CHECK-NEXT: | | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .bound_tid. 'const int *const restrict'
|
||||
// CHECK-NEXT: | | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams.c:5:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: | |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: | `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
@ -48,7 +47,6 @@ void test(void) {
|
||||
// CHECK-NEXT: | |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit .bound_tid. 'const int *const restrict'
|
||||
// CHECK-NEXT: | `-ImplicitParamDecl {{.*}} <col:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams.c:5:1) *const restrict'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <line:4:1> col:1 implicit __context 'struct (unnamed at {{.*}}ast-dump-openmp-teams.c:4:1) *const restrict'
|
||||
// CHECK-NEXT: |-ImplicitParamDecl {{.*}} <col:1> col:1 implicit dyn_ptr 'void *const restrict'
|
||||
// CHECK-NEXT: |-RecordDecl {{.*}} <line:5:1> col:1 implicit struct definition
|
||||
// CHECK-NEXT: | `-CapturedRecordAttr {{.*}} <<invalid sloc>> Implicit
|
||||
// CHECK-NEXT: `-CapturedDecl {{.*}} <<invalid sloc>> <invalid sloc> nothrow
|
||||
|
||||
@ -29,17 +29,17 @@ int test_amdgcn_target_tid_threads_simd() {
|
||||
|
||||
#endif
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z30test_amdgcn_target_tid_threadsv_l14
|
||||
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[ARR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[ARR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[ARR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[ARR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
|
||||
// CHECK-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR_ASCAST]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z30test_amdgcn_target_tid_threadsv_l14_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -60,7 +60,7 @@ int test_amdgcn_target_tid_threads_simd() {
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
|
||||
// CHECK-NEXT: store i32 [[INC]], ptr [[I_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
// CHECK: worker.exit:
|
||||
// CHECK-NEXT: ret void
|
||||
// CHECK: for.end:
|
||||
@ -69,21 +69,21 @@ int test_amdgcn_target_tid_threads_simd() {
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z35test_amdgcn_target_tid_threads_simdv_l23
|
||||
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[ARR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[ARR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[ARR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[ARR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
|
||||
// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr
|
||||
// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
|
||||
// CHECK-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z35test_amdgcn_target_tid_threads_simdv_l23_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -91,26 +91,26 @@ int test_amdgcn_target_tid_threads_simd() {
|
||||
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IV_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK: omp.inner.for.cond:
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 1000
|
||||
// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK: omp.inner.for.body:
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
|
||||
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
|
||||
// CHECK-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK: omp.body.continue:
|
||||
// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK: omp.inner.for.inc:
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1
|
||||
// CHECK-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
||||
// CHECK-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
||||
// CHECK: worker.exit:
|
||||
// CHECK-NEXT: ret void
|
||||
// CHECK: omp.inner.for.end:
|
||||
|
||||
@ -97,23 +97,23 @@ int main() {
|
||||
|
||||
#endif
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1v_l12
|
||||
// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[N:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[I1:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[N_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N]] to ptr
|
||||
// CHECK-NEXT: [[__VLA_EXPR0_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__VLA_EXPR0]] to ptr
|
||||
// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
|
||||
// CHECK-NEXT: [[I1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I1]] to ptr
|
||||
// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1v_l12_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -145,7 +145,7 @@ int main() {
|
||||
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[I_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
|
||||
// CHECK-NEXT: store i32 [[INC]], ptr [[I_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
||||
// CHECK: worker.exit:
|
||||
// CHECK-NEXT: ret void
|
||||
// CHECK: for.end:
|
||||
@ -169,7 +169,7 @@ int main() {
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I1_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP18]], 1
|
||||
// CHECK-NEXT: store i32 [[INC8]], ptr [[I1_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP12:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP15:![0-9]+]]
|
||||
// CHECK: for.end9:
|
||||
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP7]])
|
||||
// CHECK-NEXT: call void @__kmpc_target_deinit()
|
||||
@ -177,28 +177,28 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30
|
||||
// CHECK-SAME: (i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RESULT_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[M_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_CASTED]] to ptr
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[M]], ptr [[M_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -259,7 +259,7 @@ int main() {
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
@ -424,7 +424,7 @@ int main() {
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
@ -496,7 +496,7 @@ int main() {
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP23]], 1
|
||||
// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
|
||||
// CHECK: for.end:
|
||||
// CHECK-NEXT: store i32 0, ptr [[J11_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND12:%.*]]
|
||||
@ -521,7 +521,7 @@ int main() {
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[J11_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP30]], 1
|
||||
// CHECK-NEXT: store i32 [[INC21]], ptr [[J11_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP14:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP17:![0-9]+]]
|
||||
// CHECK: for.end22:
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = load ptr addrspace(5), ptr [[SAVED_STACK_ASCAST]], align 4
|
||||
// CHECK-NEXT: call void @llvm.stackrestore.p5(ptr addrspace(5) [[TMP31]])
|
||||
@ -546,28 +546,28 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52
|
||||
// CHECK-SAME: (i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RESULT_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[M_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_CASTED]] to ptr
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[M]], ptr [[M_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -630,7 +630,7 @@ int main() {
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[N:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4)
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
@ -725,7 +725,7 @@ int main() {
|
||||
// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[J_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP36]], 1
|
||||
// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
||||
// CHECK: for.end:
|
||||
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP21]])
|
||||
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
@ -786,9 +786,9 @@ int main() {
|
||||
// CHECK-NEXT: store ptr [[N]], ptr [[N_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
@ -903,33 +903,33 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76
|
||||
// CHECK-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RESULT_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[M_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_CASTED]] to ptr
|
||||
// CHECK-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr
|
||||
// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[M]], ptr [[M_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -998,7 +998,7 @@ int main() {
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[N1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4)
|
||||
// CHECK-NEXT: store i32 [[TMP2]], ptr [[N1]], align 4
|
||||
@ -1094,7 +1094,7 @@ int main() {
|
||||
// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[J_ASCAST]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP37]], 1
|
||||
// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
||||
// CHECK: for.end:
|
||||
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP22]])
|
||||
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
@ -1155,9 +1155,9 @@ int main() {
|
||||
// CHECK-NEXT: store ptr [[N]], ptr [[N_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
|
||||
|
||||
@ -19,23 +19,23 @@ void write_to_aligned_array(int *a, int N) {
|
||||
|
||||
#endif
|
||||
// CHECK-AMD-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14
|
||||
// CHECK-AMD-SAME: (i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-AMD-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-AMD-NEXT: entry:
|
||||
// CHECK-AMD-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5)
|
||||
// CHECK-AMD-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr
|
||||
// CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr
|
||||
// CHECK-AMD-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-AMD-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr
|
||||
// CHECK-AMD-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr
|
||||
// CHECK-AMD-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
|
||||
// CHECK-AMD-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8
|
||||
// CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-AMD-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-AMD-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-AMD-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK-AMD-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
|
||||
@ -21,6 +21,6 @@ void zoo(void) {
|
||||
}
|
||||
}
|
||||
|
||||
// CHECK: @{{.+}} = private unnamed_addr constant [2 x i64] [i64 288, i64 288]
|
||||
// SIMD-ONLY0-NOT: @{{.+}} = private unnamed_addr constant [2 x i64] [i64 288, i64 288]
|
||||
// CHECK: @{{.+}} = private unnamed_addr constant [1 x i64] [i64 288]
|
||||
// SIMD-ONLY0-NOT: @{{.+}} = private unnamed_addr constant [1 x i64] [i64 288]
|
||||
|
||||
|
||||
@ -17,10 +17,10 @@ int kernel_within_loop(int *a, int *b, int N, int num_iters) {
|
||||
return a[N-1];
|
||||
}
|
||||
//.
|
||||
// CHECK: @.offload_sizes = private unnamed_addr constant [6 x i64] [i64 4, i64 0, i64 8, i64 0, i64 8, i64 0]
|
||||
// CHECK: @.offload_maptypes = private unnamed_addr constant [6 x i64] [i64 800, i64 35, i64 16384, i64 35, i64 16384, i64 288]
|
||||
// CHECK: @.offload_sizes.1 = private unnamed_addr constant [6 x i64] [i64 4, i64 0, i64 8, i64 0, i64 8, i64 0]
|
||||
// CHECK: @.offload_maptypes.2 = private unnamed_addr constant [6 x i64] [i64 800, i64 35, i64 16384, i64 35, i64 16384, i64 288]
|
||||
// CHECK: @.offload_sizes = private unnamed_addr constant [5 x i64] [i64 4, i64 0, i64 8, i64 0, i64 8]
|
||||
// CHECK: @.offload_maptypes = private unnamed_addr constant [5 x i64] [i64 800, i64 35, i64 16384, i64 35, i64 16384]
|
||||
// CHECK: @.offload_sizes.1 = private unnamed_addr constant [5 x i64] [i64 4, i64 0, i64 8, i64 0, i64 8]
|
||||
// CHECK: @.offload_maptypes.2 = private unnamed_addr constant [5 x i64] [i64 800, i64 35, i64 16384, i64 35, i64 16384]
|
||||
//.
|
||||
// CHECK-LABEL: define dso_local noundef signext i32 @_Z18kernel_within_loopPiS_ii
|
||||
// CHECK-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i32 noundef signext [[N:%.*]], i32 noundef signext [[NUM_ITERS:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
@ -31,16 +31,16 @@ int kernel_within_loop(int *a, int *b, int N, int num_iters) {
|
||||
// CHECK-NEXT: [[NUM_ITERS_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
||||
// CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [6 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [6 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [6 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_SIZES11:%.*]] = alloca [6 x i64], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [5 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [5 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [5 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_SIZES11:%.*]] = alloca [5 x i64], align 8
|
||||
// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca i32, align 4
|
||||
@ -74,215 +74,201 @@ int kernel_within_loop(int *a, int *b, int N, int num_iters) {
|
||||
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[TMP12]] to i64
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = mul nuw i64 [[CONV2]], 4
|
||||
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 48, i1 false)
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 40, i1 false)
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i64 [[TMP3]], ptr [[TMP14]], align 8
|
||||
// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i64 [[TMP3]], ptr [[TMP15]], align 8
|
||||
// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP16]], align 8
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 8
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX]], ptr [[TMP18]], align 8
|
||||
// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
||||
// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP19]], align 8
|
||||
// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[A_ADDR]], ptr [[TMP21]], align 8
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX]], ptr [[TMP22]], align 8
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP23]], align 8
|
||||
// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
||||
// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP24]], align 8
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX1]], ptr [[TMP25]], align 8
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
||||
// CHECK-NEXT: store i64 [[TMP13]], ptr [[TMP26]], align 8
|
||||
// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
||||
// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP27]], align 8
|
||||
// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
||||
// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[B_ADDR]], ptr [[TMP28]], align 8
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX1]], ptr [[TMP29]], align 8
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP30]], align 8
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP33]], align 8
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i32 4, ptr [[TMP37]], align 4
|
||||
// CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i32 6, ptr [[TMP38]], align 4
|
||||
// CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 8
|
||||
// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 8
|
||||
// CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[TMP36]], ptr [[TMP41]], align 8
|
||||
// CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr @.offload_maptypes, ptr [[TMP42]], align 8
|
||||
// CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP43]], align 8
|
||||
// CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP44]], align 8
|
||||
// CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP45]], align 8
|
||||
// CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP46]], align 8
|
||||
// CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP47]], align 4
|
||||
// CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4
|
||||
// CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK-NEXT: store i32 0, ptr [[TMP49]], align 4
|
||||
// CHECK-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l9.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
|
||||
// CHECK-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i32 3, ptr [[TMP34]], align 4
|
||||
// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i32 5, ptr [[TMP35]], align 4
|
||||
// CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[TMP31]], ptr [[TMP36]], align 8
|
||||
// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP32]], ptr [[TMP37]], align 8
|
||||
// CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 8
|
||||
// CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr @.offload_maptypes, ptr [[TMP39]], align 8
|
||||
// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP40]], align 8
|
||||
// CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP41]], align 8
|
||||
// CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP42]], align 8
|
||||
// CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP43]], align 8
|
||||
// CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP44]], align 4
|
||||
// CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
|
||||
// CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK-NEXT: store i32 0, ptr [[TMP46]], align 4
|
||||
// CHECK-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l9.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
|
||||
// CHECK-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK: omp_offload.failed:
|
||||
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l9(i64 [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l9(i64 [[TMP3]], ptr [[TMP4]], ptr [[TMP5]]) #[[ATTR2:[0-9]+]]
|
||||
// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK: omp_offload.cont:
|
||||
// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP52]], ptr [[N_CASTED3]], align 4
|
||||
// CHECK-NEXT: [[TMP53:%.*]] = load i64, ptr [[N_CASTED3]], align 8
|
||||
// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP49]], ptr [[N_CASTED3]], align 4
|
||||
// CHECK-NEXT: [[TMP50:%.*]] = load i64, ptr [[N_CASTED3]], align 8
|
||||
// CHECK-NEXT: [[TMP51:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP55:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP56:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP57:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP57]], i64 0
|
||||
// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[CONV5:%.*]] = sext i32 [[TMP58]] to i64
|
||||
// CHECK-NEXT: [[TMP59:%.*]] = mul nuw i64 [[CONV5]], 4
|
||||
// CHECK-NEXT: [[TMP60:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP61:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP61]], i64 0
|
||||
// CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[CONV7:%.*]] = sext i32 [[TMP62]] to i64
|
||||
// CHECK-NEXT: [[TMP63:%.*]] = mul nuw i64 [[CONV7]], 4
|
||||
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES11]], ptr align 8 @.offload_sizes.1, i64 48, i1 false)
|
||||
// CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i64 [[TMP53]], ptr [[TMP64]], align 8
|
||||
// CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i64 [[TMP53]], ptr [[TMP65]], align 8
|
||||
// CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 0
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP66]], align 8
|
||||
// CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr [[TMP56]], ptr [[TMP67]], align 8
|
||||
// CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX4]], ptr [[TMP68]], align 8
|
||||
// CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES11]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i64 [[TMP59]], ptr [[TMP69]], align 8
|
||||
// CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 1
|
||||
// CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP54]], i64 0
|
||||
// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[CONV5:%.*]] = sext i32 [[TMP55]] to i64
|
||||
// CHECK-NEXT: [[TMP56:%.*]] = mul nuw i64 [[CONV5]], 4
|
||||
// CHECK-NEXT: [[TMP57:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP58:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP58]], i64 0
|
||||
// CHECK-NEXT: [[TMP59:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[CONV7:%.*]] = sext i32 [[TMP59]] to i64
|
||||
// CHECK-NEXT: [[TMP60:%.*]] = mul nuw i64 [[CONV7]], 4
|
||||
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES11]], ptr align 8 @.offload_sizes.1, i64 40, i1 false)
|
||||
// CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i64 [[TMP50]], ptr [[TMP61]], align 8
|
||||
// CHECK-NEXT: [[TMP62:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i64 [[TMP50]], ptr [[TMP62]], align 8
|
||||
// CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 0
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP63]], align 8
|
||||
// CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr [[TMP53]], ptr [[TMP64]], align 8
|
||||
// CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX4]], ptr [[TMP65]], align 8
|
||||
// CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES11]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i64 [[TMP56]], ptr [[TMP66]], align 8
|
||||
// CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 1
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP67]], align 8
|
||||
// CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[A_ADDR]], ptr [[TMP68]], align 8
|
||||
// CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX4]], ptr [[TMP69]], align 8
|
||||
// CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 2
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP70]], align 8
|
||||
// CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[A_ADDR]], ptr [[TMP71]], align 8
|
||||
// CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX4]], ptr [[TMP72]], align 8
|
||||
// CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 2
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP73]], align 8
|
||||
// CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP60]], ptr [[TMP74]], align 8
|
||||
// CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP75]], align 8
|
||||
// CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES11]], i32 0, i32 3
|
||||
// CHECK-NEXT: store i64 [[TMP63]], ptr [[TMP76]], align 8
|
||||
// CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 3
|
||||
// CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP57]], ptr [[TMP71]], align 8
|
||||
// CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP72]], align 8
|
||||
// CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES11]], i32 0, i32 3
|
||||
// CHECK-NEXT: store i64 [[TMP60]], ptr [[TMP73]], align 8
|
||||
// CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 3
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP74]], align 8
|
||||
// CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[B_ADDR]], ptr [[TMP75]], align 8
|
||||
// CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP76]], align 8
|
||||
// CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 4
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP77]], align 8
|
||||
// CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[B_ADDR]], ptr [[TMP78]], align 8
|
||||
// CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP79]], align 8
|
||||
// CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 4
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP80]], align 8
|
||||
// CHECK-NEXT: [[TMP81:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP81]], align 8
|
||||
// CHECK-NEXT: [[TMP82:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP82]], align 8
|
||||
// CHECK-NEXT: [[TMP83:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 5
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP83]], align 8
|
||||
// CHECK-NEXT: [[TMP84:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP85:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP86:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES11]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP87:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP88]], -2
|
||||
// CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES11]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP81]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP82]], -2
|
||||
// CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[SUB]], 3
|
||||
// CHECK-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1
|
||||
// CHECK-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP89]], 1
|
||||
// CHECK-NEXT: [[TMP90:%.*]] = zext i32 [[ADD]] to i64
|
||||
// CHECK-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i32 4, ptr [[TMP91]], align 4
|
||||
// CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i32 6, ptr [[TMP92]], align 4
|
||||
// CHECK-NEXT: [[TMP93:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[TMP84]], ptr [[TMP93]], align 8
|
||||
// CHECK-NEXT: [[TMP94:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP85]], ptr [[TMP94]], align 8
|
||||
// CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[TMP86]], ptr [[TMP95]], align 8
|
||||
// CHECK-NEXT: [[TMP96:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP96]], align 8
|
||||
// CHECK-NEXT: [[TMP97:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP97]], align 8
|
||||
// CHECK-NEXT: [[TMP98:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP98]], align 8
|
||||
// CHECK-NEXT: [[TMP99:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
|
||||
// CHECK-NEXT: store i64 [[TMP90]], ptr [[TMP99]], align 8
|
||||
// CHECK-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP100]], align 8
|
||||
// CHECK-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP101]], align 4
|
||||
// CHECK-NEXT: [[TMP102:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP102]], align 4
|
||||
// CHECK-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
|
||||
// CHECK-NEXT: store i32 0, ptr [[TMP103]], align 4
|
||||
// CHECK-NEXT: [[TMP104:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l13.region_id, ptr [[KERNEL_ARGS14]])
|
||||
// CHECK-NEXT: [[TMP105:%.*]] = icmp ne i32 [[TMP104]], 0
|
||||
// CHECK-NEXT: br i1 [[TMP105]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
|
||||
// CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP83]], 1
|
||||
// CHECK-NEXT: [[TMP84:%.*]] = zext i32 [[ADD]] to i64
|
||||
// CHECK-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i32 3, ptr [[TMP85]], align 4
|
||||
// CHECK-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i32 5, ptr [[TMP86]], align 4
|
||||
// CHECK-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[TMP78]], ptr [[TMP87]], align 8
|
||||
// CHECK-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP79]], ptr [[TMP88]], align 8
|
||||
// CHECK-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr [[TMP80]], ptr [[TMP89]], align 8
|
||||
// CHECK-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP90]], align 8
|
||||
// CHECK-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP91]], align 8
|
||||
// CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP92]], align 8
|
||||
// CHECK-NEXT: [[TMP93:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
|
||||
// CHECK-NEXT: store i64 [[TMP84]], ptr [[TMP93]], align 8
|
||||
// CHECK-NEXT: [[TMP94:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP94]], align 8
|
||||
// CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP95]], align 4
|
||||
// CHECK-NEXT: [[TMP96:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP96]], align 4
|
||||
// CHECK-NEXT: [[TMP97:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
|
||||
// CHECK-NEXT: store i32 0, ptr [[TMP97]], align 4
|
||||
// CHECK-NEXT: [[TMP98:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l13.region_id, ptr [[KERNEL_ARGS14]])
|
||||
// CHECK-NEXT: [[TMP99:%.*]] = icmp ne i32 [[TMP98]], 0
|
||||
// CHECK-NEXT: br i1 [[TMP99]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
|
||||
// CHECK: omp_offload.failed15:
|
||||
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l13(i64 [[TMP53]], ptr [[TMP54]], ptr [[TMP55]], ptr null) #[[ATTR2]]
|
||||
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l13(i64 [[TMP50]], ptr [[TMP51]], ptr [[TMP52]]) #[[ATTR2]]
|
||||
// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT16]]
|
||||
// CHECK: omp_offload.cont16:
|
||||
// CHECK-NEXT: br label [[FOR_INC:%.*]]
|
||||
// CHECK: for.inc:
|
||||
// CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP106]], 1
|
||||
// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP100]], 1
|
||||
// CHECK-NEXT: store i32 [[INC]], ptr [[I]], align 4
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK: for.end:
|
||||
// CHECK-NEXT: [[TMP107:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP108:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP108]], 1
|
||||
// CHECK-NEXT: [[TMP101:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP102:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP102]], 1
|
||||
// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB17]] to i64
|
||||
// CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, ptr [[TMP107]], i64 [[IDXPROM]]
|
||||
// CHECK-NEXT: [[TMP109:%.*]] = load i32, ptr [[ARRAYIDX18]], align 4
|
||||
// CHECK-NEXT: ret i32 [[TMP109]]
|
||||
// CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, ptr [[TMP101]], i64 [[IDXPROM]]
|
||||
// CHECK-NEXT: [[TMP103:%.*]] = load i32, ptr [[ARRAYIDX18]], align 4
|
||||
// CHECK-NEXT: ret i32 [[TMP103]]
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l9
|
||||
// CHECK-SAME: (i64 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK-SAME: (i64 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 4
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
@ -391,17 +377,15 @@ int kernel_within_loop(int *a, int *b, int N, int num_iters) {
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18kernel_within_loopPiS_ii_l13
|
||||
// CHECK-SAME: (i64 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK-SAME: (i64 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]]) #[[ATTR1]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 4
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[N_CASTED]], align 8
|
||||
|
||||
@ -25,7 +25,7 @@ void test(double *d_value)
|
||||
*d_value = h_chebyshev_coefs[1]; return;
|
||||
}
|
||||
|
||||
// CHECK: void @__omp_offloading_{{.+}}test{{.+}}(ptr %0, ptr null)
|
||||
// CHECK: void @__omp_offloading_{{.+}}test{{.+}}(ptr %0)
|
||||
|
||||
int main() {
|
||||
#pragma omp target
|
||||
@ -33,4 +33,4 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: call void @__omp_offloading_{{.+}}_main_{{.+}}(ptr null)
|
||||
// CHECK: call void @__omp_offloading_{{.+}}_main_{{.+}}()
|
||||
|
||||
@ -43,21 +43,21 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [12 x i64] [i64 0, i64 0, i64 0, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 32, i64 8, i64 0]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [12 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x3]], i64 [[#0x4000]], i64 288]
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [11 x i64] [i64 0, i64 0, i64 0, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 32, i64 8]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [11 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x3]], i64 [[#0x4000]]]
|
||||
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [12 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [11 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Check for filling of three non-constant size elements here: the whole struct
|
||||
// size, the (padded) region covering p1 & p2, and the padding at the end of
|
||||
// struct T.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [12 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [11 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[P1P2:%.+]] = getelementptr inbounds [12 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[P1P2:%.+]] = getelementptr inbounds [11 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[P1P2]], align 8
|
||||
// CHECK-DAG: [[PAD:%.+]] = getelementptr inbounds [12 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: [[PAD:%.+]] = getelementptr inbounds [11 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[PAD]], align 8
|
||||
|
||||
@ -31,22 +31,22 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [8 x i64] [i64 0, i64 0, i64 0, i64 0, i64 4, i64 4, i64 4, i64 0]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [8 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 288]
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [7 x i64] [i64 0, i64 0, i64 0, i64 0, i64 4, i64 4, i64 4]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [7 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]]]
|
||||
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [8 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [7 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Fill four non-constant size elements here: the whole struct size, the region
|
||||
// covering v.x, the region covering v.mid and the region covering v.b and v.c.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[X]], align 8
|
||||
// CHECK-DAG: [[MID:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: [[MID:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[MID]], align 8
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 3
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 3
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[BC]], align 8
|
||||
|
||||
@ -27,20 +27,20 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [7 x i64] [i64 0, i64 0, i64 0, i64 4, i64 4, i64 4, i64 0]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [7 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 288]
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [6 x i64] [i64 0, i64 0, i64 0, i64 4, i64 4, i64 4]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [6 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]]]
|
||||
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [7 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [6 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Fill three non-constant size elements here: the whole struct size, the region
|
||||
// covering v.x, and the region covering v.b and v.c.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [6 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [6 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[X]], align 8
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [6 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[BC]], align 8
|
||||
|
||||
@ -26,23 +26,23 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [8 x i64] [i64 0, i64 0, i64 0, i64 0, i64 4, i64 1, i64 4, i64 0]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [8 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 288]
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [7 x i64] [i64 0, i64 0, i64 0, i64 0, i64 4, i64 1, i64 4]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [7 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]]]
|
||||
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [8 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [7 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Fill four non-constant size elements here: the whole struct size, the region
|
||||
// covering v.x, the region covering padding after v.z and the region covering
|
||||
// v.b and v.c.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[X]], align 8
|
||||
// CHECK-DAG: [[PAD:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: [[PAD:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[PAD]], align 8
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 3
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 3
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[BC]], align 8
|
||||
|
||||
@ -28,23 +28,23 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [8 x i64] [i64 0, i64 0, i64 0, i64 0, i64 4, i64 1, i64 4, i64 0]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [8 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 288]
|
||||
// CHECK: [[CSTSZ:@.+]] = private {{.*}}constant [7 x i64] [i64 0, i64 0, i64 0, i64 0, i64 4, i64 1, i64 4]
|
||||
// CHECK: [[CSTTY:@.+]] = private {{.*}}constant [7 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]]]
|
||||
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [8 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [7 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Fill four non-constant size elements here: the whole struct size, the region
|
||||
// covering v.x, the region covering padding after v.z and the region covering
|
||||
// v.b and v.c.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[X:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[X]], align 8
|
||||
// CHECK-DAG: [[PAD:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: [[PAD:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 2
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[PAD]], align 8
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [8 x i64], ptr [[SIZES]], i32 0, i32 3
|
||||
// CHECK-DAG: [[BC:%.+]] = getelementptr inbounds [7 x i64], ptr [[SIZES]], i32 0, i32 3
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[BC]], align 8
|
||||
|
||||
@ -49,26 +49,26 @@ int main() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// CHECK: [[CSTSZ0:@.+]] = private {{.*}}constant [5 x i64] [i64 0, i64 0, i64 4, i64 4, i64 0]
|
||||
// CHECK: [[CSTTY0:@.+]] = private {{.*}}constant [5 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 288]
|
||||
// CHECK: [[CSTSZ0:@.+]] = private {{.*}}constant [4 x i64] [i64 0, i64 0, i64 4, i64 4]
|
||||
// CHECK: [[CSTTY0:@.+]] = private {{.*}}constant [4 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]]]
|
||||
|
||||
// CHECK: [[CSTSZ1:@.+]] = private {{.*}}constant [6 x i64] [i64 0, i64 0, i64 4, i64 4, i64 8, i64 0]
|
||||
// CHECK: [[CSTTY1:@.+]] = private {{.*}}constant [6 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x3]], i64 [[#0x4000]], i64 288]
|
||||
// CHECK: [[CSTSZ1:@.+]] = private {{.*}}constant [5 x i64] [i64 0, i64 0, i64 4, i64 4, i64 8]
|
||||
// CHECK: [[CSTTY1:@.+]] = private {{.*}}constant [5 x i64] [i64 [[#0x20]], i64 [[#0x1000000000003]], i64 [[#0x1000000000003]], i64 [[#0x3]], i64 [[#0x4000]]]
|
||||
|
||||
// CHECK: [[CSTSZ2:@.+]] = private {{.*}}constant [4 x i64] [i64 24, i64 4, i64 8, i64 0]
|
||||
// CHECK: [[CSTTY2:@.+]] = private {{.*}}constant [4 x i64] [i64 [[#0x23]], i64 [[#0x3]], i64 [[#0x4000]], i64 288]
|
||||
// CHECK: [[CSTSZ2:@.+]] = private {{.*}}constant [3 x i64] [i64 24, i64 4, i64 8]
|
||||
// CHECK: [[CSTTY2:@.+]] = private {{.*}}constant [3 x i64] [i64 [[#0x23]], i64 [[#0x3]], i64 [[#0x4000]]]
|
||||
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [5 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [4 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Fill two non-constant size elements here: the whole struct size, and the
|
||||
// region covering v.arr and v.y.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [5 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [4 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[ARRY:%.+]] = getelementptr inbounds [5 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[ARRY:%.+]] = getelementptr inbounds [4 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[ARRY]], align 8
|
||||
|
||||
// CHECK: call void
|
||||
@ -76,14 +76,14 @@ int main() {
|
||||
// CHECK-DAG: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[KSIZE:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZBASE:%.+]], ptr [[KSIZE]], align 8
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [6 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZBASE]] = getelementptr inbounds [5 x i64], ptr [[SIZES:%[^,]*]], i32 0, i32 0
|
||||
|
||||
// Fill two non-constant size elements here: the whole struct size, and the
|
||||
// region covering v.arr, v.y and v.z.
|
||||
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [6 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: [[STR:%.+]] = getelementptr inbounds [5 x i64], ptr [[SIZES]], i32 0, i32 0
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[STR]], align 8
|
||||
// CHECK-DAG: [[ARRYZ:%.+]] = getelementptr inbounds [6 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: [[ARRYZ:%.+]] = getelementptr inbounds [5 x i64], ptr [[SIZES]], i32 0, i32 1
|
||||
// CHECK-DAG: store i64 %{{.+}}, ptr [[ARRYZ]], align 8
|
||||
|
||||
// CHECK: call void
|
||||
|
||||
@ -28,11 +28,11 @@
|
||||
// CK0: [[ANON_T_0:%.+]] = type { ptr }
|
||||
// CK0: [[KMP_TASK_T_WITH_PRIVATES:%.+]] = type { [[KMP_TASK_T:%[^,]+]], [[KMP_PRIVATES_T:%.+]] }
|
||||
// CK0: [[KMP_TASK_T]] = type { ptr, ptr, i32, %{{[^,]+}}, %{{[^,]+}} }
|
||||
// CK0-32: [[KMP_PRIVATES_T]] = type { [2 x i64], [2 x ptr], [2 x ptr], [2 x ptr] }
|
||||
// CK0-64: [[KMP_PRIVATES_T]] = type { [2 x ptr], [2 x ptr], [2 x i64], [2 x ptr] }
|
||||
// CK0-32: [[KMP_PRIVATES_T]] = type { [1 x i64], [1 x ptr], [1 x ptr], [1 x ptr] }
|
||||
// CK0-64: [[KMP_PRIVATES_T]] = type { [1 x ptr], [1 x ptr], [1 x i64], [1 x ptr] }
|
||||
// CK0: [[KMP_TASK_T_WITH_PRIVATES_1:%.+]] = type { [[KMP_TASK_T]], [[KMP_PRIVATES_T_2:%.+]] }
|
||||
// CK0-32: [[KMP_PRIVATES_T_2]] = type { [2 x i64], [2 x ptr], [2 x ptr], [2 x ptr] }
|
||||
// CK0-64: [[KMP_PRIVATES_T_2]] = type { [2 x ptr], [2 x ptr], [2 x i64], [2 x ptr] }
|
||||
// CK0-32: [[KMP_PRIVATES_T_2]] = type { [1 x i64], [1 x ptr], [1 x ptr], [1 x ptr] }
|
||||
// CK0-64: [[KMP_PRIVATES_T_2]] = type { [1 x ptr], [1 x ptr], [1 x i64], [1 x ptr] }
|
||||
// CK0: [[KMP_TASK_T_WITH_PRIVATES_4:%.+]] = type { [[KMP_TASK_T]], [[KMP_PRIVATES_T_5:%.+]] }
|
||||
// CK0-32: [[KMP_PRIVATES_T_5]] = type { [1 x i64], [1 x ptr], [1 x ptr], [1 x ptr] }
|
||||
// CK0-64: [[KMP_PRIVATES_T_5]] = type { [1 x ptr], [1 x ptr], [1 x i64], [1 x ptr] }
|
||||
@ -44,18 +44,18 @@
|
||||
// CK0-64: [[KMP_PRIVATES_T_11]] = type { [1 x ptr], [1 x ptr], [1 x i64], [1 x ptr] }
|
||||
|
||||
// CK0-LABEL: @.__omp_offloading_{{.*}}foo{{.*}}.region_id = weak constant i8 0
|
||||
// CK0-64: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK0-32: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 8, i64 0]
|
||||
// CK0: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 35, i64 288]
|
||||
// CK0-64: [[NWSIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK0-32: [[NWSIZES:@.+]] = {{.+}}constant [2 x i64] [i64 8, i64 0]
|
||||
// CK0: [[NWTYPES:@.+]] = {{.+}}constant [2 x i64] [i64 35, i64 288]
|
||||
// CK0-64: [[TEAMSIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK0-32: [[TEAMSIZES:@.+]] = {{.+}}constant [2 x i64] [i64 8, i64 0]
|
||||
// CK0: [[TEAMTYPES:@.+]] = {{.+}}constant [2 x i64] [i64 33, i64 288]
|
||||
// CK0-64: [[TEAMNWSIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK0-32: [[TEAMNWSIZES:@.+]] = {{.+}}constant [2 x i64] [i64 8, i64 0]
|
||||
// CK0: [[TEAMNWTYPES:@.+]] = {{.+}}constant [2 x i64] [i64 33, i64 288]
|
||||
// CK0-64: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// CK0-32: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// CK0: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 35]
|
||||
// CK0-64: [[NWSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// CK0-32: [[NWSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// CK0: [[NWTYPES:@.+]] = {{.+}}constant [1 x i64] [i64 35]
|
||||
// CK0-64: [[TEAMSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// CK0-32: [[TEAMSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// CK0: [[TEAMTYPES:@.+]] = {{.+}}constant [1 x i64] [i64 33]
|
||||
// CK0-64: [[TEAMNWSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// CK0-32: [[TEAMNWSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// CK0: [[TEAMNWTYPES:@.+]] = {{.+}}constant [1 x i64] [i64 33]
|
||||
// CK0-64: [[EDSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// CK0-32: [[EDSIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// CK0: [[EDTYPES:@.+]] = {{.+}}constant [1 x i64] [i64 1]
|
||||
@ -239,23 +239,23 @@ void foo(int a){
|
||||
// CK0-DAG: store ptr [[VAL:%[^,]+]], ptr [[BP1]]
|
||||
// CK0-DAG: store ptr [[VAL]], ptr [[P1]]
|
||||
// CK0-DAG: store ptr [[MPRFUNC]], ptr [[MPR1]]
|
||||
// CK0: call void [[KERNEL_1:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK0: call void [[KERNEL_1:@.+]](ptr [[VAL]])
|
||||
#pragma omp target map(mapper(id), tofrom \
|
||||
: c)
|
||||
{
|
||||
++c.a;
|
||||
}
|
||||
|
||||
// CK0: [[BP2GEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_BP2:%[^,]+]], i32 0, i32 0
|
||||
// CK0: [[BP2GEP:%.+]] = getelementptr inbounds [1 x ptr], ptr [[OFFLOAD_BP2:%[^,]+]], i32 0, i32 0
|
||||
// CK0: store ptr [[CADDR:%[^,]+]], ptr [[BP2GEP]], align
|
||||
// CK0: [[P2GEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_P2:%[^,]+]], i32 0, i32 0
|
||||
// CK0: [[P2GEP:%.+]] = getelementptr inbounds [1 x ptr], ptr [[OFFLOAD_P2:%[^,]+]], i32 0, i32 0
|
||||
// CK0: store ptr [[CADDR]], ptr [[P2GEP]], align
|
||||
// CK0: [[MAPPER2GEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_MAPPER2:%[^,]+]], i[[SZ:32|64]] 0, i[[SZ]] 0
|
||||
// CK0: [[MAPPER2GEP:%.+]] = getelementptr inbounds [1 x ptr], ptr [[OFFLOAD_MAPPER2:%[^,]+]], i[[SZ:32|64]] 0, i[[SZ]] 0
|
||||
// CK0: store ptr [[MPRFUNC]], ptr [[MAPPER2GEP]], align
|
||||
// CK0: [[BP2:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_BP2]], i32 0, i32 0
|
||||
// CK0: [[P2:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_P2]], i32 0, i32 0
|
||||
// CK0-32: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i32 60, i32 4, ptr [[TASK_ENTRY:@.+]], i64 -1)
|
||||
// CK0-64: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i64 104, i64 8, ptr [[TASK_ENTRY:@.+]], i64 -1)
|
||||
// CK0: [[BP2:%.+]] = getelementptr inbounds [1 x ptr], ptr [[OFFLOAD_BP2]], i32 0, i32 0
|
||||
// CK0: [[P2:%.+]] = getelementptr inbounds [1 x ptr], ptr [[OFFLOAD_P2]], i32 0, i32 0
|
||||
// CK0-32: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i32 40, i32 4, ptr [[TASK_ENTRY:@.+]], i64 -1)
|
||||
// CK0-64: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i64 72, i64 8, ptr [[TASK_ENTRY:@.+]], i64 -1)
|
||||
// CK0: [[TASK_WITH_PRIVATES:%.+]] = getelementptr inbounds nuw [[KMP_TASK_T_WITH_PRIVATES]], ptr [[TASK]], i32 0, i32 1
|
||||
// CK0: {{.+}} = call i32 @__kmpc_omp_task(ptr @1, i32 {{.+}}, ptr [[TASK]])
|
||||
#pragma omp target map(mapper(id),tofrom: c) nowait
|
||||
@ -278,15 +278,15 @@ void foo(int a){
|
||||
// CK0-DAG: store ptr [[VAL:%[^,]+]], ptr [[BP1]]
|
||||
// CK0-DAG: store ptr [[VAL]], ptr [[P1]]
|
||||
// CK0-DAG: store ptr [[MPRFUNC]], ptr [[MPR1]]
|
||||
// CK0: call void [[KERNEL_3:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK0: call void [[KERNEL_3:@.+]](ptr [[VAL]])
|
||||
#pragma omp target teams map(mapper(id), to \
|
||||
: c)
|
||||
{
|
||||
++c.a;
|
||||
}
|
||||
|
||||
// CK0-32: [[TASK_1:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i32 60, i32 4, ptr [[TASK_ENTRY_1:@.+]], i64 -1)
|
||||
// CK0-64: [[TASK_1:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i64 104, i64 8, ptr [[TASK_ENTRY_1:@.+]], i64 -1)
|
||||
// CK0-32: [[TASK_1:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i32 40, i32 4, ptr [[TASK_ENTRY_1:@.+]], i64 -1)
|
||||
// CK0-64: [[TASK_1:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{@.+}}, i32 {{%.+}}, i32 1, i64 72, i64 8, ptr [[TASK_ENTRY_1:@.+]], i64 -1)
|
||||
// CK0: [[TASK_CAST_GET_1:%.+]] = getelementptr inbounds nuw [[KMP_TASK_T_WITH_PRIVATES_1]], ptr [[TASK_1]], i32 0, i32 0
|
||||
// CK0: {{.+}} = getelementptr inbounds nuw [[KMP_TASK_T]], ptr [[TASK_CAST_GET_1]], i32 0, i32 0
|
||||
// CK0: {{.+}} = call i32 @__kmpc_omp_task(ptr @1, i32 {{.+}}, ptr [[TASK_1]])
|
||||
@ -413,7 +413,7 @@ void foo(int a){
|
||||
}
|
||||
|
||||
|
||||
// CK0: define internal void [[KERNEL_1]](ptr {{[^,]+}} [[ARG:%.+]], ptr {{.*}})
|
||||
// CK0: define internal void [[KERNEL_1]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK0: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK0: store ptr [[ARG]], ptr [[ADDR]]
|
||||
// CK0: [[CADDR:%.+]] = load ptr, ptr [[ADDR]]
|
||||
@ -422,7 +422,7 @@ void foo(int a){
|
||||
// CK0: {{.+}} = add nsw i32 [[VAL]], 1
|
||||
// CK0: }
|
||||
|
||||
// CK0: define internal void [[KERNEL_2:@.+]](ptr {{[^,]+}} [[ARG:%.+]], ptr {{.*}})
|
||||
// CK0: define internal void [[KERNEL_2:@.+]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK0: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK0: store ptr [[ARG]], ptr [[ADDR]]
|
||||
// CK0: [[CADDR:%.+]] = load ptr, ptr [[ADDR]]
|
||||
@ -441,16 +441,16 @@ void foo(int a){
|
||||
// CK0-DAG: store ptr [[SIZEGEP:%.+]], ptr [[SARG]]
|
||||
// CK0-DAG: [[MARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 7
|
||||
// CK0-DAG: store ptr [[MPRGEP:%.+]], ptr [[MARG]]
|
||||
// CK0-DAG: [[BPGEP]] = getelementptr inbounds [2 x ptr], ptr [[BPFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[PGEP]] = getelementptr inbounds [2 x ptr], ptr [[PFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[SIZEGEP]] = getelementptr inbounds [2 x i64], ptr [[SIZEFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[MPRGEP]] = getelementptr inbounds [2 x ptr], ptr [[MPRFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[BPGEP]] = getelementptr inbounds [1 x ptr], ptr [[BPFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[PGEP]] = getelementptr inbounds [1 x ptr], ptr [[PFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[SIZEGEP]] = getelementptr inbounds [1 x i64], ptr [[SIZEFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[MPRGEP]] = getelementptr inbounds [1 x ptr], ptr [[MPRFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[BPFPADDR]] = load ptr, ptr [[FPPTRADDR_BP:%.+]], align
|
||||
// CK0-DAG: [[PFPADDR]] = load ptr, ptr [[FPPTRADDR_P:%.+]], align
|
||||
// CK0-DAG: [[SIZEFPADDR]] = load ptr, ptr [[FPPTRADDR_SIZE:%.+]], align
|
||||
// CK0-DAG: [[MPRFPADDR]] = load ptr, ptr [[FPPTRADDR_MPR:%.+]], align
|
||||
// CK0-DAG: call void %1(ptr %2, {{.+}}[[FPPTRADDR_BP]], {{.+}}[[FPPTRADDR_P]], {{.+}}[[FPPTRADDR_SIZE]], {{.+}}[[FPPTRADDR_MPR]])
|
||||
// CK0-DAG: call void [[KERNEL_2:@.+]](ptr [[KERNELARG:%.+]], ptr null)
|
||||
// CK0-DAG: call void [[KERNEL_2:@.+]](ptr [[KERNELARG:%.+]])
|
||||
// CK0-DAG: [[KERNELARG]] = load ptr, ptr [[KERNELARGGEP:%.+]], align
|
||||
// CK0-DAG: [[KERNELARGGEP]] = getelementptr inbounds nuw [[ANON_T]], ptr [[CTX:%.+]], i32 0, i32 0
|
||||
// CK0-DAG: [[CTX]] = load ptr, ptr [[CTXADDR:%.+]], align
|
||||
@ -477,16 +477,16 @@ void foo(int a){
|
||||
// CK0-DAG: store ptr [[SIZEGEP:%.+]], ptr [[SARG]]
|
||||
// CK0-DAG: [[MARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 7
|
||||
// CK0-DAG: store ptr [[MPRGEP:%.+]], ptr [[MARG]]
|
||||
// CK0-DAG: [[BPGEP]] = getelementptr inbounds [2 x ptr], ptr [[BPFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[PGEP]] = getelementptr inbounds [2 x ptr], ptr [[PFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[SIZEGEP]] = getelementptr inbounds [2 x i64], ptr [[SIZEFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[MPRGEP]] = getelementptr inbounds [2 x ptr], ptr [[MPRFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[BPGEP]] = getelementptr inbounds [1 x ptr], ptr [[BPFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[PGEP]] = getelementptr inbounds [1 x ptr], ptr [[PFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[SIZEGEP]] = getelementptr inbounds [1 x i64], ptr [[SIZEFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[MPRGEP]] = getelementptr inbounds [1 x ptr], ptr [[MPRFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0
|
||||
// CK0-DAG: [[BPFPADDR]] = load ptr, ptr [[FPPTRADDR_BP:%.+]], align
|
||||
// CK0-DAG: [[PFPADDR]] = load ptr, ptr [[FPPTRADDR_P:%.+]], align
|
||||
// CK0-DAG: [[SIZEFPADDR]] = load ptr, ptr [[FPPTRADDR_SIZE:%.+]], align
|
||||
// CK0-DAG: [[MPRFPADDR]] = load ptr, ptr [[FPPTRADDR_MPR:%.+]], align
|
||||
// CK0-DAG: call void %1(ptr %2, {{.+}}[[FPPTRADDR_BP]], {{.+}}[[FPPTRADDR_P]], {{.+}}[[FPPTRADDR_SIZE]], {{.+}}[[FPPTRADDR_MPR]])
|
||||
// CK0-DAG: call void [[KERNEL_2:@.+]](ptr [[KERNELARG:%.+]], ptr null)
|
||||
// CK0-DAG: call void [[KERNEL_2:@.+]](ptr [[KERNELARG:%.+]])
|
||||
// CK0-DAG: [[KERNELARG]] = load ptr, ptr [[KERNELARGGEP:%.+]], align
|
||||
// CK0-DAG: [[KERNELARGGEP]] = getelementptr inbounds nuw [[ANON_T_0]], ptr [[CTX:%.+]], i32 0, i32 0
|
||||
// CK0-DAG: [[CTX]] = load ptr, ptr [[CTXADDR:%.+]], align
|
||||
@ -787,8 +787,8 @@ public:
|
||||
// map of array sections and nested components.
|
||||
|
||||
// CK3-LABEL: @.__omp_offloading_{{.*}}foo{{.*}}.region_id = weak constant i8 0
|
||||
// CK3-DAG: [[SIZES:@.+]] = {{.+}}constant [3 x i64] [i64 {{8|16}}, i64 {{80|160}}, i64 0]
|
||||
// CK3-DAG: [[TYPES:@.+]] = {{.+}}constant [3 x i64] [i64 35, i64 35, i64 288]
|
||||
// CK3-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 {{8|16}}, i64 {{80|160}}]
|
||||
// CK3-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 35, i64 35]
|
||||
|
||||
class C {
|
||||
public:
|
||||
@ -836,7 +836,7 @@ void foo(int a){
|
||||
// CK3-DAG: [[CVALGEP:%.+]] = getelementptr inbounds {{.+}}[[CVAL]], i{{64|32}} 0, i{{64|32}} 0
|
||||
// CK3-DAG: store ptr [[CVALGEP]], ptr [[P2]]
|
||||
// CK3-DAG: store ptr [[MPRFUNC]], ptr [[MPR2]]
|
||||
// CK3: call void [[KERNEL:@.+]](ptr [[BVAL]], ptr [[CVAL]], ptr null)
|
||||
// CK3: call void [[KERNEL:@.+]](ptr [[BVAL]], ptr [[CVAL]])
|
||||
#pragma omp target map(mapper(id), tofrom \
|
||||
: c [0:10], b.c)
|
||||
for (int i = 0; i < 10; i++) {
|
||||
@ -845,7 +845,7 @@ void foo(int a){
|
||||
}
|
||||
|
||||
|
||||
// CK3: define internal void [[KERNEL]](ptr {{[^,]+}}, ptr {{[^,]+}}, ptr {{[^)]*}})
|
||||
// CK3: define internal void [[KERNEL]](ptr {{[^,]+}}, ptr {{[^,]+}})
|
||||
|
||||
#endif // CK3
|
||||
|
||||
|
||||
@ -150,7 +150,7 @@ int bar() { return 1 + foo() + bar() + baz1() + baz2(); }
|
||||
int maini1() {
|
||||
int a;
|
||||
static long aa = 32 + bbb + ccc + fff + ggg;
|
||||
// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}, ptr {{.*}})
|
||||
// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](ptr {{.*}}, ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}})
|
||||
#pragma omp target map(tofrom \
|
||||
: a, b)
|
||||
{
|
||||
@ -163,7 +163,7 @@ int maini1() {
|
||||
|
||||
int baz3() { return 2 + baz2(); }
|
||||
int baz2() {
|
||||
// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz2{{.*}}_l[[@LINE+1]](i64 {{.*}}, ptr {{.*}})
|
||||
// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz2{{.*}}_l[[@LINE+1]](ptr {{.*}}, i64 {{.*}})
|
||||
#pragma omp target parallel
|
||||
++c;
|
||||
return 2 + baz3();
|
||||
@ -175,7 +175,7 @@ static __typeof(create) __t_create __attribute__((__weakref__("__create")));
|
||||
|
||||
int baz5() {
|
||||
bool a;
|
||||
// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz5{{.*}}_l[[@LINE+1]](i64 {{.*}}, ptr {{.*}})
|
||||
// CHECK-DAG: define weak_odr protected void @__omp_offloading_{{.*}}baz5{{.*}}_l[[@LINE+1]](ptr {{.*}}, i64 {{.*}})
|
||||
#pragma omp target
|
||||
a = __extension__(void *) & __t_create != 0;
|
||||
return a;
|
||||
|
||||
@ -25,14 +25,14 @@ int maini1() {
|
||||
|
||||
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -57,7 +57,7 @@ int maini1() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(ptr noundef nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR7:[0-9]+]]
|
||||
// CHECK1-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z3barv() #[[ATTR7]]
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
|
||||
@ -70,7 +70,7 @@ int maini1() {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: ret i32 [[TMP1]]
|
||||
//
|
||||
|
||||
@ -24,8 +24,8 @@
|
||||
// HOST-DAG: @[[D_PTR:.+]] = weak global ptr @[[D]]
|
||||
// DEVICE-NOT: @c =
|
||||
// DEVICE: @c_decl_tgt_ref_ptr = weak global ptr null
|
||||
// HOST: [[SIZES:@.+]] = private unnamed_addr constant [4 x i64] [i64 4, i64 4, i64 4, i64 0]
|
||||
// HOST: [[MAPTYPES:@.+]] = private unnamed_addr constant [4 x i64] [i64 35, i64 531, i64 531, i64 288]
|
||||
// HOST: [[SIZES:@.+]] = private unnamed_addr constant [3 x i64] [i64 4, i64 4, i64 4]
|
||||
// HOST: [[MAPTYPES:@.+]] = private unnamed_addr constant [3 x i64] [i64 35, i64 531, i64 531]
|
||||
// HOST: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [{{[0-9]+}} x i8] c"c_decl_tgt_ref_ptr\00"
|
||||
// HOST: @.offloading.entry.c_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { i64 0, i16 1, i16 1, i32 1, ptr @c_decl_tgt_ref_ptr, ptr @.offloading.entry_name, i64 8, i64 0, ptr null }, section "llvm_offload_entries"
|
||||
// HOST-COFF: @.offloading.entry.{{.*}} = weak constant %struct.__tgt_offload_entry { {{.*}} }, section "llvm_offload_entries$OE"
|
||||
@ -52,34 +52,34 @@ int maini1() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// DEVICE: define weak_odr protected void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}}
|
||||
// DEVICE: define weak_odr protected void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr {{[^,]+}}, ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}}
|
||||
// DEVICE: [[C_REF:%.+]] = load ptr, ptr @c_decl_tgt_ref_ptr,
|
||||
// DEVICE: [[C:%.+]] = load i32, ptr [[C_REF]],
|
||||
// DEVICE: store i32 [[C]], ptr %
|
||||
|
||||
// HOST: define {{.*}}i32 @{{.*}}maini1{{.*}}()
|
||||
// HOST: [[BASEPTRS:%.+]] = alloca [4 x ptr],
|
||||
// HOST: [[PTRS:%.+]] = alloca [4 x ptr],
|
||||
// HOST: getelementptr inbounds [4 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: [[BASEPTRS:%.+]] = alloca [3 x ptr],
|
||||
// HOST: [[PTRS:%.+]] = alloca [3 x ptr],
|
||||
// HOST: getelementptr inbounds [3 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
|
||||
// HOST: [[BP1:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// HOST: [[BP1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// HOST: store ptr @c_decl_tgt_ref_ptr, ptr [[BP1]],
|
||||
// HOST: [[P1:%.+]] = getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// HOST: [[P1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
||||
// HOST: store ptr @c, ptr [[P1]],
|
||||
|
||||
// HOST: [[BP2:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
|
||||
// HOST: [[BP2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
|
||||
// HOST: store ptr @[[D_PTR]], ptr [[BP2]],
|
||||
// HOST: [[P2:%.+]] = getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
|
||||
// HOST: [[P2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
|
||||
// HOST: store ptr @[[D]], ptr [[P2]],
|
||||
|
||||
// HOST: [[BP0:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: [[P0:%.+]] = getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: [[BP0:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BASEPTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: [[P0:%.+]] = getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
||||
// HOST: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr %{{.+}})
|
||||
// HOST: call void @__omp_offloading_{{.*}}_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr %{{[^,]+}}, ptr null)
|
||||
// HOST: call void @__omp_offloading_{{.*}}_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr %{{[^,]+}})
|
||||
// HOST: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 0, i32 0, ptr @.{{.+}}.region_id, ptr %{{.+}})
|
||||
|
||||
// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}}, ptr {{.*}})
|
||||
// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l44(ptr noundef nonnull align {{[0-9]+}} dereferenceable{{.*}})
|
||||
// HOST: [[C:%.*]] = load i32, ptr @c,
|
||||
// HOST: store i32 [[C]], ptr %
|
||||
|
||||
|
||||
@ -29,7 +29,7 @@ int base();
|
||||
// HOST-LABEL: define{{.*}} void @foo()
|
||||
// HOST: call i32 @hst(double noundef -1.000000e+00)
|
||||
// HOST: call i32 @hst(double noundef -2.000000e+00)
|
||||
// HOST: call void [[OFFL:@.+_foo_l36]](ptr null)
|
||||
// HOST: call void [[OFFL:@.+_foo_l36]]()
|
||||
void foo() {
|
||||
base(-1);
|
||||
hst(-2);
|
||||
@ -40,7 +40,7 @@ void foo() {
|
||||
}
|
||||
}
|
||||
|
||||
// HOST: define {{.*}}void [[OFFL]](ptr {{[^,]+}})
|
||||
// HOST: define {{.*}}void [[OFFL]]()
|
||||
// HOST: call i32 @hst(double noundef -3.000000e+00)
|
||||
// HOST: call i32 @dev(double noundef -4.000000e+00)
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -123,106 +123,82 @@ int main() {
|
||||
// CHECK1-LABEL: define {{[^@]+}}@_Z9gtid_testv
|
||||
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47(ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47() #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP29]], align 8
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP30]], align 8
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, ptr [[KERNEL_ARGS5]])
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
||||
// CHECK1: omp_offload.failed6:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
||||
// CHECK1: omp_offload.cont7:
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.region_id, ptr [[KERNEL_ARGS2]])
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
||||
// CHECK1: omp_offload.failed3:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
||||
// CHECK1: omp_offload.cont4:
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-SAME: () #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -358,10 +334,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l52.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -506,165 +480,135 @@ int main() {
|
||||
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP11:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS12:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[_TMP5:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP29]], align 8
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP30]], align 8
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS5]])
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
||||
// CHECK1: omp_offload.failed6:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
||||
// CHECK1: omp_offload.cont7:
|
||||
// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr @Arg, align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP40]], ptr [[ARG_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[ARG_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP41]], ptr [[TMP42]], align 8
|
||||
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP41]], ptr [[TMP43]], align 8
|
||||
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS2]])
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
||||
// CHECK1: omp_offload.failed3:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
||||
// CHECK1: omp_offload.cont4:
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr @Arg, align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP30]], ptr [[ARG_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[ARG_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP38]], align 4
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP35]], ptr [[TMP39]], align 8
|
||||
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 8
|
||||
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP41]], align 8
|
||||
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP42]], align 8
|
||||
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP43]], align 8
|
||||
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP44]], align 8
|
||||
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP45]], align 8
|
||||
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP46]], align 8
|
||||
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP47]], align 8
|
||||
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP50]], align 4
|
||||
// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 2, ptr [[TMP51]], align 4
|
||||
// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 8
|
||||
// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 8
|
||||
// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP54]], align 8
|
||||
// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP55]], align 8
|
||||
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 8
|
||||
// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP57]], align 8
|
||||
// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP58]], align 8
|
||||
// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP59]], align 8
|
||||
// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4
|
||||
// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP61]], align 4
|
||||
// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP62]], align 4
|
||||
// CHECK1-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, ptr [[KERNEL_ARGS12]])
|
||||
// CHECK1-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
||||
// CHECK1: omp_offload.failed13:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP41]], ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
||||
// CHECK1: omp_offload.cont14:
|
||||
// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr @Arg, align 4
|
||||
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP65]])
|
||||
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP45]], align 8
|
||||
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP46]], align 8
|
||||
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
|
||||
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4
|
||||
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP49]], align 4
|
||||
// CHECK1-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, ptr [[KERNEL_ARGS6]])
|
||||
// CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
||||
// CHECK1: omp_offload.failed7:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP31]]) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
||||
// CHECK1: omp_offload.cont8:
|
||||
// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr @Arg, align 4
|
||||
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP52]])
|
||||
// CHECK1-NEXT: ret i32 [[CALL]]
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l85.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -801,10 +745,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -946,12 +888,10 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103
|
||||
// CHECK1-SAME: (i64 noundef [[ARG:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store i64 [[ARG]], ptr [[ARG_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.omp_outlined, ptr [[ARG_ADDR]])
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -973,7 +913,7 @@ int main() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -1108,163 +1048,133 @@ int main() {
|
||||
// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP11:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS12:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[_TMP5:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: store i32 [[ARG]], ptr [[ARG_ADDR]], align 4
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.11, ptr [[TMP29]], align 8
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP30]], align 8
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, ptr [[KERNEL_ARGS5]])
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
||||
// CHECK1: omp_offload.failed6:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
||||
// CHECK1: omp_offload.cont7:
|
||||
// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[ARG_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP40]], ptr [[ARG_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[ARG_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP41]], ptr [[TMP42]], align 8
|
||||
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP41]], ptr [[TMP43]], align 8
|
||||
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP23]], align 8
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.region_id, ptr [[KERNEL_ARGS2]])
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
||||
// CHECK1: omp_offload.failed3:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
||||
// CHECK1: omp_offload.cont4:
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARG_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP30]], ptr [[ARG_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[ARG_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP38]], align 4
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP35]], ptr [[TMP39]], align 8
|
||||
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 8
|
||||
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP41]], align 8
|
||||
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP42]], align 8
|
||||
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP43]], align 8
|
||||
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP44]], align 8
|
||||
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP45]], align 8
|
||||
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP46]], align 8
|
||||
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP47]], align 8
|
||||
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP50]], align 4
|
||||
// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 2, ptr [[TMP51]], align 4
|
||||
// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 8
|
||||
// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 8
|
||||
// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.13, ptr [[TMP54]], align 8
|
||||
// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP55]], align 8
|
||||
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 8
|
||||
// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP57]], align 8
|
||||
// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP58]], align 8
|
||||
// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP59]], align 8
|
||||
// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4
|
||||
// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP61]], align 4
|
||||
// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS12]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP62]], align 4
|
||||
// CHECK1-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, ptr [[KERNEL_ARGS12]])
|
||||
// CHECK1-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
||||
// CHECK1: omp_offload.failed13:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP41]], ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
||||
// CHECK1: omp_offload.cont14:
|
||||
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 100, ptr [[TMP45]], align 8
|
||||
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP46]], align 8
|
||||
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
|
||||
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4
|
||||
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP49]], align 4
|
||||
// CHECK1-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.region_id, ptr [[KERNEL_ARGS6]])
|
||||
// CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
||||
// CHECK1: omp_offload.failed7:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75(i64 [[TMP31]]) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
||||
// CHECK1: omp_offload.cont8:
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l63.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -1401,10 +1311,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l69.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -1546,12 +1454,10 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75
|
||||
// CHECK1-SAME: (i64 noundef [[ARG:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store i64 [[ARG]], ptr [[ARG_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75.omp_outlined, ptr [[ARG_ADDR]])
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -1573,7 +1479,7 @@ int main() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8, !nonnull [[META20]], !align [[META21]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -149,10 +149,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -290,14 +288,14 @@ int main() {
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
||||
// CHECK1-NEXT: store double 1.000000e+00, ptr [[G]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: store i32 3, ptr [[SVAR]], align 4
|
||||
// CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[G]], ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[SVAR]], ptr [[TMP14]], align 8
|
||||
@ -333,10 +331,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined)
|
||||
// CHECK3-NEXT: ret void
|
||||
//
|
||||
@ -470,14 +466,14 @@ int main() {
|
||||
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
||||
// CHECK3-NEXT: store double 1.000000e+00, ptr [[G]], align 8
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 4
|
||||
// CHECK3-NEXT: store i32 3, ptr [[SVAR]], align 4
|
||||
// CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store ptr [[G]], ptr [[TMP11]], align 4
|
||||
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
|
||||
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 4
|
||||
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
|
||||
// CHECK3-NEXT: store ptr [[SVAR]], ptr [[TMP14]], align 4
|
||||
@ -510,9 +506,6 @@ int main() {
|
||||
// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4
|
||||
// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
@ -525,63 +518,55 @@ int main() {
|
||||
// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
|
||||
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
|
||||
// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9: omp_offload.failed:
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95(ptr null) #[[ATTR4:[0-9]+]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]]
|
||||
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK9: omp_offload.cont:
|
||||
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
|
||||
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK9: arraydestroy.body:
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
||||
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK9: arraydestroy.done2:
|
||||
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP21]]
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP16]]
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
||||
@ -608,10 +593,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -793,7 +776,7 @@ int main() {
|
||||
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]]
|
||||
@ -845,9 +828,6 @@ int main() {
|
||||
// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4
|
||||
// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
@ -858,62 +838,54 @@ int main() {
|
||||
// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
|
||||
// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
|
||||
// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9: omp_offload.failed:
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(ptr null) #[[ATTR4]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]]
|
||||
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK9: omp_offload.cont:
|
||||
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK9: arraydestroy.body:
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
||||
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK9: arraydestroy.done2:
|
||||
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP21]]
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP16]]
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
||||
@ -974,10 +946,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3]] {
|
||||
// CHECK9-SAME: () #[[ATTR3]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -1157,7 +1127,7 @@ int main() {
|
||||
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
|
||||
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]]
|
||||
@ -1245,9 +1215,6 @@ int main() {
|
||||
// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4
|
||||
// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
@ -1260,63 +1227,55 @@ int main() {
|
||||
// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1
|
||||
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
|
||||
// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr undef, ptr [[_TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11: omp_offload.failed:
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95(ptr null) #[[ATTR4:[0-9]+]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]]
|
||||
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK11: omp_offload.cont:
|
||||
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
|
||||
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK11: arraydestroy.body:
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
|
||||
// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK11: arraydestroy.done2:
|
||||
// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP21]]
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP16]]
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
||||
@ -1343,10 +1302,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1523,7 +1480,7 @@ int main() {
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]]
|
||||
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false)
|
||||
@ -1574,9 +1531,6 @@ int main() {
|
||||
// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4
|
||||
// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
@ -1587,62 +1541,54 @@ int main() {
|
||||
// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
|
||||
// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
|
||||
// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr undef, ptr [[_TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11: omp_offload.failed:
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(ptr null) #[[ATTR4]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]]
|
||||
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK11: omp_offload.cont:
|
||||
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK11: arraydestroy.body:
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
|
||||
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK11: arraydestroy.done2:
|
||||
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP21]]
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP16]]
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
||||
@ -1703,10 +1649,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3]] {
|
||||
// CHECK11-SAME: () #[[ATTR3]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1881,7 +1825,7 @@ int main() {
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
|
||||
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]]
|
||||
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false)
|
||||
|
||||
@ -57,108 +57,84 @@ int main() {
|
||||
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37(ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37() #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP29]], align 8
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP30]], align 8
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS5]])
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
||||
// CHECK1: omp_offload.failed6:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
||||
// CHECK1: omp_offload.cont7:
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP23]], align 8
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS2]])
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
||||
// CHECK1: omp_offload.failed3:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
||||
// CHECK1: omp_offload.cont4:
|
||||
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
|
||||
// CHECK1-NEXT: ret i32 [[CALL]]
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-SAME: () #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -295,10 +271,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -437,60 +411,47 @@ int main() {
|
||||
// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
|
||||
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
|
||||
@ -48,20 +48,18 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARGC_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14(i64 [[TMP1]], ptr [[TMP2]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14(i64 [[TMP1]], ptr [[TMP2]]) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14
|
||||
// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARGC_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8
|
||||
@ -166,7 +164,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
|
||||
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
||||
// CHECK1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -531,31 +529,31 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
|
||||
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META13:![0-9]+]]
|
||||
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
|
||||
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
|
||||
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
|
||||
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META2]], !align [[META3]]
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META3]], !align [[META4]]
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META13]]
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14]]
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP16]], ptr [[TMP15]], ptr [[TMP14]])
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 1
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8, !nonnull [[META2]], !align [[META3]]
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8, !nonnull [[META3]], !align [[META4]]
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = sext i32 [[TMP23]] to i64
|
||||
// CHECK1-NEXT: [[LB_ADD_LEN_I:%.*]] = add nsw i64 -1, [[TMP24]]
|
||||
@ -569,7 +567,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = sub i64 [[TMP28]], [[TMP29]]
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = add nuw i64 [[TMP30]], 1
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP31]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
|
||||
// CHECK1-NEXT: store i64 [[TMP31]], ptr @{{reduction_size[.].+[.]}}, align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store i64 [[TMP31]], ptr @{{reduction_size[.].+[.]}}, align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP16]], ptr [[TMP33]], ptr [[TMP20]])
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
|
||||
@ -579,8 +577,8 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = ptrtoaddr ptr [[TMP20]] to i64
|
||||
// CHECK1-NEXT: [[TMP40:%.*]] = sub i64 [[TMP38]], [[TMP39]]
|
||||
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[TMP34]], i64 [[TMP40]]
|
||||
// CHECK1-NEXT: store ptr [[TMP4_I]], ptr [[TMP_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store ptr [[TMP41]], ptr [[TMP4_I]], align 8, !noalias [[META13]]
|
||||
// CHECK1-NEXT: store ptr [[TMP4_I]], ptr [[TMP_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: store ptr [[TMP41]], ptr [[TMP4_I]], align 8, !noalias [[META14]]
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -57,108 +57,84 @@ int main() {
|
||||
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37(ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37() #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP29]], align 8
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP30]], align 8
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS5]])
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
|
||||
// CHECK1: omp_offload.failed6:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]]
|
||||
// CHECK1: omp_offload.cont7:
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP23]], align 8
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS2]])
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]]
|
||||
// CHECK1: omp_offload.failed3:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]]
|
||||
// CHECK1: omp_offload.cont4:
|
||||
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
|
||||
// CHECK1-NEXT: ret i32 [[CALL]]
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-SAME: () #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -199,24 +175,24 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
||||
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -277,23 +253,23 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
||||
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK1: omp.body.continue:
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -309,10 +285,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -353,24 +327,24 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
||||
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -431,23 +405,23 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
|
||||
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
||||
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
|
||||
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
|
||||
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK1: omp.body.continue:
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
|
||||
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -465,60 +439,47 @@ int main() {
|
||||
// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
|
||||
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 1000, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29(ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29() #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: () #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -559,24 +520,24 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
||||
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: call void @__kmpc_push_proc_bind(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l29.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -637,23 +598,23 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
|
||||
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
||||
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
|
||||
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
|
||||
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK1: omp.body.continue:
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
|
||||
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -689,23 +650,23 @@ int main() {
|
||||
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK3: omp.inner.for.cond:
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
|
||||
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK3: omp.inner.for.body:
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK3: omp.body.continue:
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK3: omp.inner.for.inc:
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
||||
// CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
|
||||
// CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
// CHECK3: omp.inner.for.end:
|
||||
// CHECK3-NEXT: store i32 1000, ptr [[I]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB3]], align 4
|
||||
@ -714,23 +675,23 @@ int main() {
|
||||
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]
|
||||
// CHECK3: omp.inner.for.cond7:
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
||||
// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]]
|
||||
// CHECK3: omp.inner.for.body9:
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1
|
||||
// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
|
||||
// CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]]
|
||||
// CHECK3: omp.body.continue12:
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]]
|
||||
// CHECK3: omp.inner.for.inc13:
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1
|
||||
// CHECK3-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
// CHECK3-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK3: omp.inner.for.end15:
|
||||
// CHECK3-NEXT: store i32 1000, ptr [[I6]], align 4
|
||||
// CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
|
||||
@ -751,23 +712,23 @@ int main() {
|
||||
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK3: omp.inner.for.cond:
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
|
||||
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK3: omp.inner.for.body:
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK3: omp.body.continue:
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK3: omp.inner.for.inc:
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
|
||||
// CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
// CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
|
||||
// CHECK3: omp.inner.for.end:
|
||||
// CHECK3-NEXT: store i32 1000, ptr [[I]], align 4
|
||||
// CHECK3-NEXT: ret i32 0
|
||||
|
||||
@ -128,10 +128,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined)
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -191,14 +189,14 @@ int main() {
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
||||
// CHECK1-NEXT: store double 1.000000e+00, ptr [[G]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: store i32 3, ptr [[SVAR]], align 4
|
||||
// CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[G]], ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[SVAR]], ptr [[TMP12]], align 8
|
||||
@ -234,10 +232,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined)
|
||||
// CHECK3-NEXT: ret void
|
||||
//
|
||||
@ -297,14 +293,14 @@ int main() {
|
||||
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
||||
// CHECK3-NEXT: store double 1.000000e+00, ptr [[G]], align 8
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 4
|
||||
// CHECK3-NEXT: store i32 3, ptr [[SVAR]], align 4
|
||||
// CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store ptr [[G]], ptr [[TMP9]], align 4
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
|
||||
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
|
||||
// CHECK3-NEXT: store ptr [[SVAR]], ptr [[TMP12]], align 4
|
||||
@ -337,18 +333,12 @@ int main() {
|
||||
// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4
|
||||
// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[_TMP5:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[KERNEL_ARGS3:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: store ptr [[G]], ptr [[G1]], align 8
|
||||
// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
|
||||
@ -358,104 +348,88 @@ int main() {
|
||||
// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
|
||||
// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
|
||||
// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9: omp_offload.failed:
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93(ptr null) #[[ATTR4:[0-9]+]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]]
|
||||
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK9: omp_offload.cont:
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP19]], align 8
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP20]], align 8
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP21]], align 8
|
||||
// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0
|
||||
// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP29]], align 8
|
||||
// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP30]], align 8
|
||||
// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP33]], align 8
|
||||
// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK9-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, ptr [[KERNEL_ARGS6]])
|
||||
// CHECK9-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
||||
// CHECK9: omp_offload.failed7:
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(ptr null) #[[ATTR4]]
|
||||
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
||||
// CHECK9: omp_offload.cont8:
|
||||
// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP23]], align 8
|
||||
// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK9-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, ptr [[KERNEL_ARGS3]])
|
||||
// CHECK9-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]]
|
||||
// CHECK9: omp_offload.failed4:
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]]
|
||||
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT5]]
|
||||
// CHECK9: omp_offload.cont5:
|
||||
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
|
||||
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK9: arraydestroy.body:
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
||||
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK9: arraydestroy.done9:
|
||||
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK9: arraydestroy.done6:
|
||||
// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP41]]
|
||||
// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP31]]
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
||||
@ -482,10 +456,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -562,7 +534,7 @@ int main() {
|
||||
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
|
||||
@ -606,10 +578,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3]] {
|
||||
// CHECK9-SAME: () #[[ATTR3]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -684,9 +654,6 @@ int main() {
|
||||
// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4
|
||||
// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
@ -697,62 +664,54 @@ int main() {
|
||||
// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
|
||||
// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
|
||||
// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr @.offload_sizes.3, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP10]], align 8
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK9-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK9-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK9-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK9-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK9: omp_offload.failed:
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(ptr null) #[[ATTR4]]
|
||||
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]]
|
||||
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK9: omp_offload.cont:
|
||||
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
|
||||
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK9: arraydestroy.body:
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
||||
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK9: arraydestroy.done2:
|
||||
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP21]]
|
||||
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK9-NEXT: ret i32 [[TMP16]]
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
||||
@ -813,10 +772,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49
|
||||
// CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3]] {
|
||||
// CHECK9-SAME: () #[[ATTR3]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined)
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -892,7 +849,7 @@ int main() {
|
||||
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
|
||||
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
|
||||
// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
|
||||
@ -980,18 +937,12 @@ int main() {
|
||||
// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4
|
||||
// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[_TMP5:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[KERNEL_ARGS3:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: store ptr [[G]], ptr [[G1]], align 4
|
||||
// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
|
||||
@ -1001,104 +952,88 @@ int main() {
|
||||
// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1
|
||||
// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
|
||||
// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr undef, ptr [[_TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11: omp_offload.failed:
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93(ptr null) #[[ATTR4:[0-9]+]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR4:[0-9]+]]
|
||||
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK11: omp_offload.cont:
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 3, ptr [[TMP15]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP16]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP17]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP18]], align 4
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP19]], align 4
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP20]], align 4
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP21]], align 4
|
||||
// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 4
|
||||
// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 4, ptr [[TMP25]], align 4
|
||||
// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 4
|
||||
// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 4
|
||||
// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP29]], align 4
|
||||
// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP30]], align 4
|
||||
// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP31]], align 4
|
||||
// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP32]], align 4
|
||||
// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP33]], align 8
|
||||
// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4
|
||||
// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK11-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, ptr [[KERNEL_ARGS6]])
|
||||
// CHECK11-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
||||
// CHECK11: omp_offload.failed7:
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(ptr null) #[[ATTR4]]
|
||||
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
||||
// CHECK11: omp_offload.cont8:
|
||||
// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP23]], align 8
|
||||
// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP24]], align 8
|
||||
// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
|
||||
// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
|
||||
// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS3]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP27]], align 4
|
||||
// CHECK11-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, ptr [[KERNEL_ARGS3]])
|
||||
// CHECK11-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]]
|
||||
// CHECK11: omp_offload.failed4:
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]]
|
||||
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT5]]
|
||||
// CHECK11: omp_offload.cont5:
|
||||
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
|
||||
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK11: arraydestroy.body:
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
|
||||
// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK11: arraydestroy.done9:
|
||||
// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK11: arraydestroy.done6:
|
||||
// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP41]]
|
||||
// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP31]]
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
||||
@ -1125,10 +1060,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1204,7 +1137,7 @@ int main() {
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]]
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
|
||||
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false)
|
||||
@ -1247,10 +1180,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3]] {
|
||||
// CHECK11-SAME: () #[[ATTR3]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1325,9 +1256,6 @@ int main() {
|
||||
// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4
|
||||
// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
@ -1338,62 +1266,54 @@ int main() {
|
||||
// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
|
||||
// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
|
||||
// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store ptr undef, ptr [[_TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 4, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr @.offload_sizes.3, ptr [[TMP9]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP13]], align 8
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK11-NEXT: store i32 3, ptr [[TMP0]], align 4
|
||||
// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP1]], align 4
|
||||
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK11-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK11-NEXT: store i64 2, ptr [[TMP8]], align 8
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK11-NEXT: store i64 0, ptr [[TMP9]], align 8
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
|
||||
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK11-NEXT: store i32 0, ptr [[TMP12]], align 4
|
||||
// CHECK11-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
||||
// CHECK11-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK11: omp_offload.failed:
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(ptr null) #[[ATTR4]]
|
||||
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49() #[[ATTR4]]
|
||||
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK11: omp_offload.cont:
|
||||
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0
|
||||
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
|
||||
// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
||||
// CHECK11: arraydestroy.body:
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
|
||||
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
||||
// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
|
||||
// CHECK11: arraydestroy.done2:
|
||||
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
||||
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP21]]
|
||||
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
|
||||
// CHECK11-NEXT: ret i32 [[TMP16]]
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
||||
@ -1454,10 +1374,8 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49
|
||||
// CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3]] {
|
||||
// CHECK11-SAME: () #[[ATTR3]] {
|
||||
// CHECK11-NEXT: entry:
|
||||
// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined)
|
||||
// CHECK11-NEXT: ret void
|
||||
//
|
||||
@ -1532,7 +1450,7 @@ int main() {
|
||||
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
|
||||
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10]], !align [[META11]]
|
||||
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
|
||||
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -87,60 +87,54 @@ int main() {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 2, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP15]], align 8
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP16]], align 8
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 2, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP21]], align 4
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP22]], align 4
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
|
||||
@ -148,12 +142,10 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
|
||||
// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, ptr [[SIVAR_ADDR]])
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -175,7 +167,7 @@ int main() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -199,27 +191,27 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
||||
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK1: omp.body.continue:
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -244,9 +236,9 @@ int main() {
|
||||
// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4
|
||||
@ -254,63 +246,55 @@ int main() {
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP10]], align 4
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 2, ptr [[TMP11]], align 4
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP15]], align 8
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP16]], align 8
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 2, ptr [[TMP18]], align 8
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP21]], align 4
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP22]], align 4
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]], ptr null) #[[ATTR2]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
|
||||
// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]])
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -332,7 +316,7 @@ int main() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -356,27 +340,27 @@ int main() {
|
||||
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK1: omp.inner.for.cond:
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
||||
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK1: omp.inner.for.body:
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK1: omp.body.continue:
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK1: omp.inner.for.inc:
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
|
||||
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
|
||||
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
||||
// CHECK1: omp.inner.for.end:
|
||||
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK1: omp.loop.exit:
|
||||
@ -400,60 +384,54 @@ int main() {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 4, ptr [[TMP10]], align 4
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store i32 2, ptr [[TMP11]], align 4
|
||||
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4
|
||||
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 4
|
||||
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP14]], align 4
|
||||
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP15]], align 4
|
||||
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP16]], align 4
|
||||
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4
|
||||
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK3-NEXT: store i64 2, ptr [[TMP18]], align 8
|
||||
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK3-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP21]], align 4
|
||||
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK3-NEXT: store i32 0, ptr [[TMP22]], align 4
|
||||
// CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK3-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
|
||||
// CHECK3-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4
|
||||
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4
|
||||
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4
|
||||
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4
|
||||
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8
|
||||
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4
|
||||
// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
||||
// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK3: omp_offload.failed:
|
||||
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
||||
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK3: omp_offload.cont:
|
||||
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
|
||||
@ -461,12 +439,10 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
|
||||
// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, ptr [[SIVAR_ADDR]])
|
||||
// CHECK3-NEXT: ret void
|
||||
//
|
||||
@ -488,7 +464,7 @@ int main() {
|
||||
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -512,27 +488,27 @@ int main() {
|
||||
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK3: omp.inner.for.cond:
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
||||
// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK3: omp.inner.for.body:
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
||||
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
|
||||
// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK3: omp.body.continue:
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK3: omp.inner.for.inc:
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
|
||||
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
|
||||
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK3: omp.inner.for.end:
|
||||
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK3: omp.loop.exit:
|
||||
@ -557,9 +533,9 @@ int main() {
|
||||
// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
||||
// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4
|
||||
@ -567,63 +543,55 @@ int main() {
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 4, ptr [[TMP10]], align 4
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store i32 2, ptr [[TMP11]], align 4
|
||||
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4
|
||||
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 4
|
||||
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP14]], align 4
|
||||
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP15]], align 4
|
||||
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP16]], align 4
|
||||
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4
|
||||
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK3-NEXT: store i64 2, ptr [[TMP18]], align 8
|
||||
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK3-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP21]], align 4
|
||||
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK3-NEXT: store i32 0, ptr [[TMP22]], align 4
|
||||
// CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK3-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
|
||||
// CHECK3-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 4
|
||||
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4
|
||||
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4
|
||||
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4
|
||||
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8
|
||||
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4
|
||||
// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
||||
// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK3: omp_offload.failed:
|
||||
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]], ptr null) #[[ATTR2]]
|
||||
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]]
|
||||
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK3: omp_offload.cont:
|
||||
// CHECK3-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
|
||||
// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]])
|
||||
// CHECK3-NEXT: ret void
|
||||
//
|
||||
@ -645,7 +613,7 @@ int main() {
|
||||
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -669,27 +637,27 @@ int main() {
|
||||
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK3: omp.inner.for.cond:
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
||||
// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK3: omp.inner.for.body:
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
||||
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
|
||||
// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK3: omp.body.continue:
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK3: omp.inner.for.inc:
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
|
||||
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
|
||||
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
||||
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
||||
// CHECK3: omp.inner.for.end:
|
||||
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK3: omp.loop.exit:
|
||||
@ -726,27 +694,27 @@ int main() {
|
||||
// CHECK5-NEXT: store i32 0, ptr [[SIVAR]], align 4
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK5: omp.inner.for.cond:
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
|
||||
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK5: omp.inner.for.body:
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
|
||||
// CHECK5-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK5: omp.body.continue:
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK5: omp.inner.for.inc:
|
||||
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
|
||||
// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP1]]
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
|
||||
// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
// CHECK5: omp.inner.for.end:
|
||||
// CHECK5-NEXT: store i32 2, ptr [[I]], align 4
|
||||
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
|
||||
@ -777,27 +745,27 @@ int main() {
|
||||
// CHECK5-NEXT: store i32 0, ptr [[T_VAR1]], align 4
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK5: omp.inner.for.cond:
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
|
||||
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK5: omp.inner.for.body:
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
|
||||
// CHECK5-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK5: omp.body.continue:
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK5: omp.inner.for.inc:
|
||||
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1
|
||||
// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK5: omp.inner.for.end:
|
||||
// CHECK5-NEXT: store i32 2, ptr [[I]], align 4
|
||||
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
@ -825,27 +793,27 @@ int main() {
|
||||
// CHECK7-NEXT: store i32 0, ptr [[SIVAR]], align 4
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK7: omp.inner.for.cond:
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
|
||||
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK7: omp.inner.for.body:
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
|
||||
// CHECK7-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK7: omp.body.continue:
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK7: omp.inner.for.inc:
|
||||
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
|
||||
// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
|
||||
// CHECK7: omp.inner.for.end:
|
||||
// CHECK7-NEXT: store i32 2, ptr [[I]], align 4
|
||||
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
|
||||
@ -876,27 +844,27 @@ int main() {
|
||||
// CHECK7-NEXT: store i32 0, ptr [[T_VAR1]], align 4
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK7: omp.inner.for.cond:
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
|
||||
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
|
||||
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK7: omp.inner.for.body:
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
|
||||
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
|
||||
// CHECK7-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK7: omp.body.continue:
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK7: omp.inner.for.inc:
|
||||
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1
|
||||
// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
|
||||
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
// CHECK7: omp.inner.for.end:
|
||||
// CHECK7-NEXT: store i32 2, ptr [[I]], align 4
|
||||
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4
|
||||
@ -917,12 +885,10 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45
|
||||
// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
// CHECK9-NEXT: entry:
|
||||
// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined, ptr [[SIVAR_ADDR]])
|
||||
// CHECK9-NEXT: ret void
|
||||
//
|
||||
@ -945,7 +911,7 @@ int main() {
|
||||
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8
|
||||
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -969,30 +935,30 @@ int main() {
|
||||
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
||||
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
||||
// CHECK9: omp.inner.for.cond:
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
|
||||
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
||||
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
||||
// CHECK9: omp.inner.for.body:
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
||||
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
||||
// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
|
||||
// CHECK9-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
||||
// CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
||||
// CHECK9: omp.body.continue:
|
||||
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
||||
// CHECK9: omp.inner.for.inc:
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
||||
// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
|
||||
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
|
||||
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
|
||||
// CHECK9: omp.inner.for.end:
|
||||
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
||||
// CHECK9: omp.loop.exit:
|
||||
|
||||
@ -32,15 +32,15 @@ int main(void) {
|
||||
}
|
||||
|
||||
// CHECK-USM-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25(
|
||||
// CHECK-USM-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[GI:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-USM-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GI:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-USM-NEXT: entry:
|
||||
// CHECK-USM-NEXT: [[GI_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-USM-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-USM-NEXT: [[GI_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GI_ADDR]] to ptr
|
||||
// CHECK-USM-NEXT: [[GI_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-USM-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-USM-NEXT: store ptr [[GI]], ptr [[GI_ADDR_ASCAST]], align 8
|
||||
// CHECK-USM-NEXT: [[GI_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GI_ADDR]] to ptr
|
||||
// CHECK-USM-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-USM-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GI_ADDR_ASCAST]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK-USM-NEXT: store ptr [[GI]], ptr [[GI_ADDR_ASCAST]], align 8
|
||||
// CHECK-USM-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GI_ADDR_ASCAST]], align 8
|
||||
// CHECK-USM-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-USM-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-USM-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -56,15 +56,15 @@ int main(void) {
|
||||
//
|
||||
//
|
||||
// CHECK-DEFAULT-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25(
|
||||
// CHECK-DEFAULT-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[GI:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-DEFAULT-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GI:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-DEFAULT-NEXT: entry:
|
||||
// CHECK-DEFAULT-NEXT: [[GI_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-DEFAULT-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-DEFAULT-NEXT: [[GI_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GI_ADDR]] to ptr
|
||||
// CHECK-DEFAULT-NEXT: [[GI_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
|
||||
// CHECK-DEFAULT-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
|
||||
// CHECK-DEFAULT-NEXT: store ptr [[GI]], ptr [[GI_ADDR_ASCAST]], align 8
|
||||
// CHECK-DEFAULT-NEXT: [[GI_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GI_ADDR]] to ptr
|
||||
// CHECK-DEFAULT-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
|
||||
// CHECK-DEFAULT-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GI_ADDR_ASCAST]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK-DEFAULT-NEXT: store ptr [[GI]], ptr [[GI_ADDR_ASCAST]], align 8
|
||||
// CHECK-DEFAULT-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GI_ADDR_ASCAST]], align 8
|
||||
// CHECK-DEFAULT-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment to ptr), ptr [[DYN_PTR]])
|
||||
// CHECK-DEFAULT-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-DEFAULT-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
|
||||
@ -40,8 +40,8 @@ int map_struct() {
|
||||
//.
|
||||
// CHECK: @.offload_sizes = private unnamed_addr constant [3 x i64] [i64 264, i64 40, i64 8]
|
||||
// CHECK: @.offload_maptypes = private unnamed_addr constant [3 x i64] [i64 [[#0x1]], i64 [[#0x1]], i64 [[#0x4000]]]
|
||||
// CHECK: @.offload_sizes.1 = private unnamed_addr constant [2 x i64] [i64 264, i64 0]
|
||||
// CHECK: @.offload_maptypes.2 = private unnamed_addr constant [2 x i64] [i64 [[#0x223]], i64 [[#0x120]]]
|
||||
// CHECK: @.offload_sizes.1 = private unnamed_addr constant [1 x i64] [i64 264]
|
||||
// CHECK: @.offload_maptypes.2 = private unnamed_addr constant [1 x i64] [i64 [[#0x223]]]
|
||||
// CHECK: @.offload_sizes.3 = private unnamed_addr constant [1 x i64] [i64 264]
|
||||
// CHECK: @.offload_maptypes.4 = private unnamed_addr constant [1 x i64] [i64 [[#0x2]]]
|
||||
//.
|
||||
@ -52,9 +52,9 @@ int map_struct() {
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 8
|
||||
@ -92,75 +92,67 @@ int map_struct() {
|
||||
// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-NEXT: call void @__tgt_target_data_begin_mapper(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 3, ptr [[TMP11]], ptr [[TMP12]], ptr @.offload_sizes, ptr @.offload_maptypes, ptr null, ptr null)
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[TMP13]], align 8
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[TMP14]], align 8
|
||||
// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
||||
// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP15]], align 8
|
||||
// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP16]], align 8
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i32 4, ptr [[TMP21]], align 4
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i32 2, ptr [[TMP22]], align 4
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8
|
||||
// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr @.offload_sizes.1, ptr [[TMP25]], align 8
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP26]], align 8
|
||||
// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP27]], align 8
|
||||
// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP28]], align 8
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP29]], align 8
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP30]], align 8
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP31]], align 4
|
||||
// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK-NEXT: store i32 0, ptr [[TMP33]], align 4
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10map_structv_l27.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
||||
// CHECK-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK-NEXT: store i32 3, ptr [[TMP18]], align 4
|
||||
// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK-NEXT: store i32 1, ptr [[TMP19]], align 4
|
||||
// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 8
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8
|
||||
// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP24]], align 8
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP25]], align 8
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP26]], align 8
|
||||
// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK-NEXT: store i64 0, ptr [[TMP27]], align 8
|
||||
// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP28]], align 4
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK-NEXT: store i32 0, ptr [[TMP30]], align 4
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10map_structv_l27.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
||||
// CHECK-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK: omp_offload.failed:
|
||||
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10map_structv_l27(ptr [[DAT]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10map_structv_l27(ptr [[DAT]]) #[[ATTR2:[0-9]+]]
|
||||
// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK: omp_offload.cont:
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[TMP33]], align 8
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[TMP34]], align 8
|
||||
// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP35]], align 8
|
||||
// CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[TMP36]], align 8
|
||||
// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[TMP37]], align 8
|
||||
// CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
|
||||
// CHECK-NEXT: store ptr null, ptr [[TMP38]], align 8
|
||||
// CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK-NEXT: call void @__tgt_target_data_end_mapper(ptr @[[GLOB1]], i64 -1, i32 1, ptr [[TMP39]], ptr [[TMP40]], ptr @.offload_sizes.3, ptr @.offload_maptypes.4, ptr null, ptr null)
|
||||
// CHECK-NEXT: call void @__tgt_target_data_end_mapper(ptr @[[GLOB1]], i64 -1, i32 1, ptr [[TMP36]], ptr [[TMP37]], ptr @.offload_sizes.3, ptr @.offload_maptypes.4, ptr null, ptr null)
|
||||
// CHECK-NEXT: [[XI10:%.*]] = getelementptr inbounds nuw [[STRUCT_DESCRIPTOR]], ptr [[DAT]], i32 0, i32 2
|
||||
// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[XI10]], align 8
|
||||
// CHECK-NEXT: ret i32 [[TMP41]]
|
||||
// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[XI10]], align 8
|
||||
// CHECK-NEXT: ret i32 [[TMP38]]
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10map_structv_l27(
|
||||
// CHECK-SAME: ptr noundef nonnull align 8 dereferenceable(264) [[DAT:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
// CHECK-SAME: ptr noundef nonnull align 8 dereferenceable(264) [[DAT:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DAT_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: store ptr [[DAT]], ptr [[DAT_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DAT_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DAT_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK-NEXT: [[XI:%.*]] = getelementptr inbounds nuw [[STRUCT_DESCRIPTOR:%.*]], ptr [[TMP0]], i32 0, i32 2
|
||||
// CHECK-NEXT: store i32 4, ptr [[XI]], align 8
|
||||
// CHECK-NEXT: [[XI1:%.*]] = getelementptr inbounds nuw [[STRUCT_DESCRIPTOR]], ptr [[TMP0]], i32 0, i32 2
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -67,11 +67,11 @@ int maini1() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// DEVICE-DAG: define weak{{.*}} void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-7]](ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}}, ptr {{[^)]*}})
|
||||
// DEVICE-DAG: define weak{{.*}} void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-7]](ptr {{[^,]*}}, ptr noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}}
|
||||
// DEVICE-DAG: [[C:%.+]] = load i32, ptr [[C_ADDR]],
|
||||
// DEVICE-DAG: store i32 [[C]], ptr %
|
||||
|
||||
// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-11]](ptr noundef nonnull align {{[0-9]+}} dereferenceable{{.*}}, ptr {{[^)]*}})
|
||||
// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-11]](ptr noundef nonnull align {{[0-9]+}} dereferenceable{{.*}})
|
||||
// HOST: [[C:%.*]] = load i32, ptr @[[C_ADDR]],
|
||||
// HOST: store i32 [[C]], ptr %
|
||||
|
||||
|
||||
@ -25,27 +25,27 @@ int main(int argc, char **argv) {
|
||||
|
||||
#endif
|
||||
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19
|
||||
// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK4-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK4-NEXT: entry:
|
||||
// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK4-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK4-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
|
||||
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -92,10 +92,10 @@ int main(int argc, char **argv) {
|
||||
// CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK4-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[C1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 40)
|
||||
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -250,11 +250,11 @@ int main(int argc, char **argv) {
|
||||
// CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
||||
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK4-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -343,27 +343,27 @@ int main(int argc, char **argv) {
|
||||
//
|
||||
//
|
||||
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19
|
||||
// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK5-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK5-NEXT: entry:
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK5-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
|
||||
// CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -410,10 +410,10 @@ int main(int argc, char **argv) {
|
||||
// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK5-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[C1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 40)
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -566,11 +566,11 @@ int main(int argc, char **argv) {
|
||||
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
||||
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -11,14 +11,14 @@
|
||||
#define HEADER
|
||||
|
||||
// CHECK: [[ANON_T:%.+]] = type { ptr, ptr }
|
||||
// CHECK-DAG: [[SIZES_TEMPLATE:@.+]] = private {{.+}} constant [6 x i[[PTRSZ:32|64]]] [i{{32|64}} 4, i{{32|64}} 4, i{{32|64}} {{8|16}}, i{{32|64}} 0, i{{32|64}} 0, i{{32|64}} 0]
|
||||
// CHECK-DAG: [[TYPES_TEMPLATE:@.+]] = private {{.+}} constant [6 x i64] [i64 800, i64 800, i64 673, i64 844424930132752, i64 844424930132752, i64 288]
|
||||
// CHECK-DAG: [[SIZES:@.+]] = private {{.+}} constant [4 x i[[PTRSZ:32|64]]] [i{{32|64}} {{8|16}}, i{{32|64}} 0, i{{32|64}} 0, i{{32|64}} 0]
|
||||
// CHECK-DAG: [[TYPES:@.+]] = private {{.+}} constant [4 x i64] [i64 673, i64 281474976711440, i64 281474976711440, i64 288]
|
||||
// CHECK-DAG: [[TYPES3:@.+]] = private {{.+}} constant [4 x i64] [i64 545, i64 281474976711440, i64 800, i64 288]
|
||||
// CHECK-DAG: [[TYPES11:@.+]] = private {{.+}} constant [6 x i64] [i64 800, i64 800, i64 549, i64 844424930132752, i64 844424930132752, i64 288]
|
||||
// CHECK-DAG: [[TYPES13:@.+]] = private {{.+}} constant [3 x i64] [i64 545, i64 281474976711440, i64 288]
|
||||
// CHECK-DAG: [[TYPES15:@.+]] = private {{.+}} constant [3 x i64] [i64 673, i64 281474976711440, i64 288]
|
||||
// CHECK-DAG: [[SIZES_TEMPLATE:@.+]] = private {{.+}} constant [5 x i[[PTRSZ:32|64]]] [i{{32|64}} 4, i{{32|64}} 4, i{{32|64}} {{8|16}}, i{{32|64}} 0, i{{32|64}} 0]
|
||||
// CHECK-DAG: [[TYPES_TEMPLATE:@.+]] = private {{.+}} constant [5 x i64] [i64 800, i64 800, i64 673, i64 844424930132752, i64 844424930132752]
|
||||
// CHECK-DAG: [[SIZES:@.+]] = private {{.+}} constant [3 x i[[PTRSZ:32|64]]] [i{{32|64}} {{8|16}}, i{{32|64}} 0, i{{32|64}} 0]
|
||||
// CHECK-DAG: [[TYPES:@.+]] = private {{.+}} constant [3 x i64] [i64 673, i64 281474976711440, i64 281474976711440]
|
||||
// CHECK-DAG: [[TYPES3:@.+]] = private {{.+}} constant [3 x i64] [i64 545, i64 281474976711440, i64 800]
|
||||
// CHECK-DAG: [[TYPES11:@.+]] = private {{.+}} constant [5 x i64] [i64 800, i64 800, i64 549, i64 844424930132752, i64 844424930132752]
|
||||
// CHECK-DAG: [[TYPES13:@.+]] = private {{.+}} constant [2 x i64] [i64 545, i64 281474976711440]
|
||||
// CHECK-DAG: [[TYPES15:@.+]] = private {{.+}} constant [2 x i64] [i64 673, i64 281474976711440]
|
||||
|
||||
template <typename F>
|
||||
void omp_loop(int start, int end, F body) {
|
||||
@ -71,8 +71,8 @@ int main()
|
||||
body(i);
|
||||
}
|
||||
|
||||
// CHECK: [[BASE_PTRS:%.+]] = alloca [4 x ptr]{{.+}}
|
||||
// CHECK: [[PTRS:%.+]] = alloca [4 x ptr]{{.+}}
|
||||
// CHECK: [[BASE_PTRS:%.+]] = alloca [3 x ptr]{{.+}}
|
||||
// CHECK: [[PTRS:%.+]] = alloca [3 x ptr]{{.+}}
|
||||
|
||||
// First gep of pointers inside lambdas to store the values across function call need to be ignored
|
||||
// CHECK: {{%.+}} = getelementptr inbounds nuw [[ANON_T]], ptr %{{.+}}, i{{.+}} 0, i{{.+}} 0
|
||||
@ -85,33 +85,33 @@ int main()
|
||||
// CHECK: [[PTR2:%.+]] = load ptr, ptr [[BASE_PTR2]]
|
||||
|
||||
// storage of pointers in baseptrs and ptrs arrays
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 0
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 0
|
||||
// CHECK: store ptr %{{.+}}, ptr [[LOC_LAMBDA]]{{.+}}
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 0
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 0
|
||||
// CHECK: store ptr %{{.+}}, ptr [[LOC_LAMBDA]]{{.+}}
|
||||
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 1
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 1
|
||||
// CHECK: store ptr [[BASE_PTR1]], ptr [[LOC_PTR1]]{{.+}}
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 1
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 1
|
||||
// CHECK: store ptr [[PTR1]], ptr [[LOC_PTR1]]{{.+}}
|
||||
|
||||
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: store ptr [[BASE_PTR2]], ptr [[LOC_PTR2]]{{.+}}
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [4 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: store ptr [[PTR2]], ptr [[LOC_PTR2]]{{.+}}
|
||||
|
||||
// actual target invocation
|
||||
// CHECK: [[BASES_GEP:%.+]] = getelementptr {{.+}} [4 x ptr], ptr [[BASE_PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: [[PTRS_GEP:%.+]] = getelementptr {{.+}} [4 x ptr], ptr [[PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: [[BASES_GEP:%.+]] = getelementptr {{.+}} [3 x ptr], ptr [[BASE_PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: [[PTRS_GEP:%.+]] = getelementptr {{.+}} [3 x ptr], ptr [[PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: {{%.+}} = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 0, i32 0, ptr @.{{.+}}.region_id, ptr %{{.+}})
|
||||
|
||||
omp_loop(0,100,body);
|
||||
omp_loop_ref(0,100,body);
|
||||
}
|
||||
|
||||
// CHECK: [[BASE_PTRS:%.+]] = alloca [6 x ptr]{{.+}}
|
||||
// CHECK: [[PTRS:%.+]] = alloca [6 x ptr]{{.+}}
|
||||
// CHECK: [[BASE_PTRS:%.+]] = alloca [5 x ptr]{{.+}}
|
||||
// CHECK: [[PTRS:%.+]] = alloca [5 x ptr]{{.+}}
|
||||
|
||||
// access of pointers inside lambdas
|
||||
// CHECK: [[BASE_PTR1:%.+]] = getelementptr inbounds nuw [[ANON_T]], ptr %{{.+}}, i{{.+}} 0, i{{.+}} 0
|
||||
@ -120,25 +120,25 @@ int main()
|
||||
// CHECK: [[PTR2:%.+]] = load ptr, ptr [[BASE_PTR2]]
|
||||
|
||||
// storage of pointers in baseptrs and ptrs arrays
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: store ptr %{{.+}}, ptr [[LOC_LAMBDA]]{{.+}}
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [6 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: [[LOC_LAMBDA:%.+]] = getelementptr inbounds [5 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 2
|
||||
// CHECK: store ptr %{{.+}}, ptr [[LOC_LAMBDA]]{{.+}}
|
||||
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 3
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 3
|
||||
// CHECK: store ptr [[BASE_PTR1]], ptr [[LOC_PTR1]]{{.+}}
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [6 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 3
|
||||
// CHECK: [[LOC_PTR1:%.+]] = getelementptr inbounds [5 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 3
|
||||
// CHECK: store ptr [[PTR1]], ptr [[LOC_PTR1]]{{.+}}
|
||||
|
||||
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 4
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BASE_PTRS]], i{{.+}} 0, i{{.+}} 4
|
||||
// CHECK: store ptr [[BASE_PTR2]], ptr [[LOC_PTR2]]{{.+}}
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [6 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 4
|
||||
// CHECK: [[LOC_PTR2:%.+]] = getelementptr inbounds [5 x ptr], ptr [[PTRS]], i{{.+}} 0, i{{.+}} 4
|
||||
// CHECK: store ptr [[PTR2]], ptr [[LOC_PTR2]]{{.+}}
|
||||
|
||||
// actual target invocation
|
||||
// CHECK: [[BASES_GEP:%.+]] = getelementptr {{.+}} [6 x ptr], ptr [[BASE_PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: [[PTRS_GEP:%.+]] = getelementptr {{.+}} [6 x ptr], ptr [[PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: [[BASES_GEP:%.+]] = getelementptr {{.+}} [5 x ptr], ptr [[BASE_PTRS]], {{.+}} 0, {{.+}} 0
|
||||
// CHECK: [[PTRS_GEP:%.+]] = getelementptr {{.+}} [5 x ptr], ptr [[PTRS]], {{.+}} 0, {{.+}} 0
|
||||
|
||||
// CHECK: define internal void @{{.+}}omp_loop_ref{{.+}}(
|
||||
// CHECK: [[BODY:%body.addr]] = alloca ptr
|
||||
|
||||
@ -34,14 +34,14 @@ int main() {
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -79,7 +79,7 @@ int main() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: call void @_Z3usePi(ptr noundef [[TMP0]]) #[[ATTR6]]
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -111,7 +111,7 @@ int main() {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META4]], !align [[META6:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: call void @_Z4workPi(ptr noundef [[TMP1]]) #[[ATTR6]]
|
||||
// CHECK1-NEXT: ret void
|
||||
@ -146,14 +146,14 @@ int main() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -191,7 +191,7 @@ int main() {
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: call void @_Z3usePi(ptr noundef [[TMP0]]) #[[ATTR6]]
|
||||
// CHECK2-NEXT: ret void
|
||||
//
|
||||
@ -223,7 +223,7 @@ int main() {
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
|
||||
// CHECK2-NEXT: call void @_Z4workPi(ptr noundef [[TMP1]]) #[[ATTR6]]
|
||||
// CHECK2-NEXT: ret void
|
||||
|
||||
@ -74,15 +74,15 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26
|
||||
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS2:%.*]] = alloca [0 x ptr], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -182,20 +182,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -254,13 +254,13 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55
|
||||
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -292,7 +292,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i64 @__kmpc_warp_active_thread_mask()
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
|
||||
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
||||
@ -343,15 +343,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26
|
||||
// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS2:%.*]] = alloca [0 x ptr], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -451,20 +451,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
|
||||
// CHECK2-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -523,13 +523,13 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55
|
||||
// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -561,7 +561,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i64 @__kmpc_warp_active_thread_mask()
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block()
|
||||
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
|
||||
|
||||
@ -33,16 +33,16 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13
|
||||
// CHECK-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -85,8 +85,8 @@ int bar(int n){
|
||||
// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
||||
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
|
||||
@ -145,16 +145,16 @@ void unreachable_call() {
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25
|
||||
// CHECK1-SAME: (ptr [[PTR1:%.*]], ptr nonnull align 8 dereferenceable(8) [[PTR2:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr [[PTR1:%.*]], ptr nonnull align 8 dereferenceable(8) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[PTR1_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[PTR2_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[PTR1]], ptr [[PTR1_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[PTR2]], ptr [[PTR2_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8, !nonnull [[META11:![0-9]+]], !align [[META12:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -182,8 +182,8 @@ void unreachable_call() {
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[PTR1]], ptr [[PTR1_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[PTR2]], ptr [[PTR2_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8
|
||||
@ -207,12 +207,12 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47
|
||||
// CHECK1-SAME: (i64 [[AA:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[AA:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -234,8 +234,9 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
|
||||
// CHECK1-SAME: (i64 [[A:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], ptr nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], ptr nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr nonnull align 8 dereferenceable(16) [[D:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[A:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], ptr nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], ptr nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
@ -245,7 +246,7 @@ void unreachable_call() {
|
||||
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
@ -255,15 +256,14 @@ void unreachable_call() {
|
||||
// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META11]], !align [[META13:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -327,19 +327,19 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90
|
||||
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -368,24 +368,24 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108
|
||||
// CHECK1-SAME: (ptr [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], ptr nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], ptr nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META11]], !align [[META14:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -424,7 +424,7 @@ void unreachable_call() {
|
||||
// CHECK1-NEXT: [[F:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4)
|
||||
// CHECK1-NEXT: store i32 [[F1]], ptr [[F]], align 4
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr [[F]], ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
|
||||
@ -454,17 +454,17 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74
|
||||
// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias [[DYN_PTR:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -499,10 +499,10 @@ void unreachable_call() {
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F_ADDR]], align 8, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load double, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]]
|
||||
// CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32
|
||||
@ -531,16 +531,16 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25
|
||||
// CHECK2-SAME: (ptr [[PTR1:%.*]], ptr nonnull align 4 dereferenceable(4) [[PTR2:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr [[PTR1:%.*]], ptr nonnull align 4 dereferenceable(4) [[PTR2:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[PTR1_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[PTR2_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[PTR1]], ptr [[PTR1_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[PTR2]], ptr [[PTR2_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 4, !nonnull [[META11:![0-9]+]], !align [[META12:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9targetBarPiS__l25_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -568,8 +568,8 @@ void unreachable_call() {
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[PTR1]], ptr [[PTR1_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[PTR2]], ptr [[PTR2_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
||||
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 4
|
||||
@ -593,12 +593,12 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47
|
||||
// CHECK2-SAME: (i32 [[AA:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[AA:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l47_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -620,8 +620,9 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53
|
||||
// CHECK2-SAME: (i32 [[A:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], ptr nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], ptr nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr nonnull align 8 dereferenceable(16) [[D:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[A:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], ptr nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr nonnull align 8 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], ptr nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
@ -631,7 +632,7 @@ void unreachable_call() {
|
||||
// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
@ -641,15 +642,14 @@ void unreachable_call() {
|
||||
// CHECK2-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK2-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META11]], !align [[META13:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
||||
// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -713,19 +713,19 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90
|
||||
// CHECK2-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l90_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -754,24 +754,24 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108
|
||||
// CHECK2-SAME: (ptr [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], ptr nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias [[DYN_PTR:%.*]], ptr [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], ptr nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META11]], !align [[META14:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l108_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -810,7 +810,7 @@ void unreachable_call() {
|
||||
// CHECK2-NEXT: [[F:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4)
|
||||
// CHECK2-NEXT: store i32 [[F1]], ptr [[F]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr [[F]], ptr [[TMP2]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
|
||||
@ -840,17 +840,17 @@ void unreachable_call() {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74
|
||||
// CHECK2-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias [[DYN_PTR:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], ptr nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l74_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -885,10 +885,10 @@ void unreachable_call() {
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F_ADDR]], align 4, !nonnull [[META11]], !align [[META12]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META11]], !align [[META13]]
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load double, ptr [[TMP2]], align 8
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]]
|
||||
// CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[ADD]] to i32
|
||||
|
||||
@ -32,9 +32,9 @@ int foo(int n, double *ptr) {
|
||||
b[a] += e.X;
|
||||
}
|
||||
|
||||
// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(ptr addrspace(1) noalias noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[A_IN:%.+]], ptr noalias noundef [[E_IN:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr addrspace(1) noalias noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[A_IN:%.+]], ptr noalias noundef [[E_IN:%.+]])
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK-NOT: alloca [[TTII]],
|
||||
// TCHECK: alloca i{{[0-9]+}},
|
||||
// TCHECK: store i{{[0-9]+}} [[A_IN]], ptr [[A_ADDR]],
|
||||
@ -51,12 +51,12 @@ int foo(int n, double *ptr) {
|
||||
|
||||
// make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the
|
||||
// target region
|
||||
// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}}{{.*}} [[A2_IN:%.+]], ptr{{.*}} [[B_IN:%.+]], ptr{{.*}} [[C_IN:%.+]], ptr{{.*}} [[D_IN:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, i{{[0-9]+}}{{.*}} [[A2_IN:%.+]], ptr{{.*}} [[B_IN:%.+]], ptr{{.*}} [[C_IN:%.+]], ptr{{.*}} [[D_IN:%.+]])
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK: [[A2_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[C_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[D_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK-NOT: alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B_PRIV:%.+]] = alloca [10 x float],
|
||||
// TCHECK: [[C_PRIV:%.+]] = alloca [5 x [10 x double]],
|
||||
@ -90,9 +90,9 @@ int foo(int n, double *ptr) {
|
||||
ptr[0]++;
|
||||
}
|
||||
|
||||
// TCHECK: define weak_odr protected ptx_kernel void @__omp_offloading_{{.+}}(ptr noundef [[PTR_IN:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: [[PTR_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: define weak_odr protected ptx_kernel void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr noundef [[PTR_IN:%.+]])
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[PTR_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK-NOT: alloca ptr,
|
||||
// TCHECK: store ptr [[PTR_IN]], ptr [[PTR_ADDR]],
|
||||
// TCHECK: [[PTR_IN_REF:%.+]] = load ptr, ptr [[PTR_ADDR]],
|
||||
@ -136,11 +136,11 @@ void fconst(const tx t) {
|
||||
{ }
|
||||
}
|
||||
|
||||
// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}}{{.*}} [[A_IN:%.+]], i{{[0-9]+}}{{.*}} [[A3_IN:%.+]], ptr {{.+}} [[B_IN:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, i{{[0-9]+}}{{.*}} [[A_IN:%.+]], i{{[0-9]+}}{{.*}} [[A3_IN:%.+]], ptr {{.+}} [[B_IN:%.+]])
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[A3_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK-NOT: alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}],
|
||||
// TCHECK: store i{{[0-9]+}} [[A_IN]], ptr [[A_ADDR]],
|
||||
@ -173,10 +173,10 @@ struct S1 {
|
||||
return (int)b;
|
||||
}
|
||||
|
||||
// TCHECK: define internal void @__omp_offloading_{{.+}}(ptr noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: define internal void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, ptr noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]])
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK: [[TH_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK-NOT: alloca i{{[0-9]+}},
|
||||
|
||||
// TCHECK: store ptr [[TH]], ptr [[TH_ADDR]],
|
||||
@ -205,10 +205,10 @@ int bar(int n, double *ptr) {
|
||||
|
||||
// template
|
||||
|
||||
// TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], ptr{{.+}} noundef [[B_IN:%.+]], ptr {{[^,]+}})
|
||||
// TCHECK: define internal void @__omp_offloading_{{.+}}(ptr {{[^,]+}}, i{{[0-9]+}} noundef [[A_IN:%.+]], ptr{{.+}} noundef [[B_IN:%.+]])
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B_ADDR:%.+]] = alloca ptr,
|
||||
// TCHECK: [[DYN_PTR_ADDR:%.+]] = alloca ptr
|
||||
// TCHECK-NOT: alloca i{{[0-9]+}},
|
||||
// TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}],
|
||||
// TCHECK: store i{{[0-9]+}} [[A_IN]], ptr [[A_ADDR]],
|
||||
|
||||
@ -52,14 +52,14 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -83,7 +83,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
|
||||
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
|
||||
@ -93,20 +93,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -138,9 +138,9 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
|
||||
@ -157,14 +157,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -188,7 +188,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
|
||||
// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
|
||||
@ -198,20 +198,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META5]], !align [[META7:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -243,9 +243,9 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
|
||||
// CHECK2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
|
||||
|
||||
@ -47,14 +47,14 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -78,7 +78,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
|
||||
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
|
||||
@ -88,22 +88,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -136,9 +136,9 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
|
||||
// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
|
||||
@ -155,14 +155,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -186,7 +186,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
|
||||
// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
|
||||
@ -196,22 +196,22 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META5]], !align [[META7:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -244,9 +244,9 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META5]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
|
||||
// CHECK2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
|
||||
|
||||
@ -81,14 +81,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
|
||||
// CHECK45-64-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-64-NEXT: entry:
|
||||
// CHECK45-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK45-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK45-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK45-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK45-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -125,20 +125,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK45-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36
|
||||
// CHECK45-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-64-NEXT: entry:
|
||||
// CHECK45-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK45-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK45-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK45-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK45-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK45-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK45-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK45-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK45-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -178,7 +178,7 @@ int bar(int n){
|
||||
// CHECK45-64-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK45-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK45-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK45-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
// CHECK45-64-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
@ -223,14 +223,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
|
||||
// CHECK45-32-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-NEXT: entry:
|
||||
// CHECK45-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK45-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK45-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK45-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -267,20 +267,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK45-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36
|
||||
// CHECK45-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-NEXT: entry:
|
||||
// CHECK45-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK45-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK45-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK45-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK45-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -320,7 +320,7 @@ int bar(int n){
|
||||
// CHECK45-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK45-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
// CHECK45-32-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
@ -365,14 +365,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
|
||||
// CHECK45-32-EX-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-EX-NEXT: entry:
|
||||
// CHECK45-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK45-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK45-32-EX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK45-32-EX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -409,20 +409,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK45-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36
|
||||
// CHECK45-32-EX-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK45-32-EX-NEXT: entry:
|
||||
// CHECK45-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-EX-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK45-32-EX-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK45-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK45-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK45-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK45-32-EX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK45-32-EX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -462,7 +462,7 @@ int bar(int n){
|
||||
// CHECK45-32-EX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK45-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
// CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
@ -507,14 +507,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
|
||||
// CHECK-64-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-64-NEXT: entry:
|
||||
// CHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -551,20 +551,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36
|
||||
// CHECK-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-64-NEXT: entry:
|
||||
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
|
||||
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -604,7 +604,7 @@ int bar(int n){
|
||||
// CHECK-64-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
// CHECK-64-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
@ -649,14 +649,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
|
||||
// CHECK-32-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-NEXT: entry:
|
||||
// CHECK-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -693,20 +693,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36
|
||||
// CHECK-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-NEXT: entry:
|
||||
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -746,7 +746,7 @@ int bar(int n){
|
||||
// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
// CHECK-32-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
@ -791,14 +791,14 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
|
||||
// CHECK-32-EX-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-EX-NEXT: entry:
|
||||
// CHECK-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CHECK-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-32-EX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK-32-EX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -835,20 +835,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36
|
||||
// CHECK-32-EX-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-32-EX-NEXT: entry:
|
||||
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-EX-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK-32-EX-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l36_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-32-EX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK-32-EX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -888,7 +888,7 @@ int bar(int n){
|
||||
// CHECK-32-EX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -43,8 +43,8 @@ int bar(int n){
|
||||
// CHECK-HOST: [[TO_VAR:@.+]] ={{.*}} global double 2.000000e+01
|
||||
// CHECK-HOST: [[VAR_DECL_TGT_TO_PTR:@.+]] = weak{{.*}} global ptr [[TO_VAR]]
|
||||
|
||||
// CHECK-HOST: [[OFFLOAD_SIZES:@.+]] = private unnamed_addr constant [3 x i64] [i64 4, i64 8, i64 0]
|
||||
// CHECK-HOST: [[OFFLOAD_MAPTYPES:@.+]] = private unnamed_addr constant [3 x i64] [i64 800, i64 800, i64 288]
|
||||
// CHECK-HOST: [[OFFLOAD_SIZES:@.+]] = private unnamed_addr constant [2 x i64] [i64 4, i64 8]
|
||||
// CHECK-HOST: [[OFFLOAD_MAPTYPES:@.+]] = private unnamed_addr constant [2 x i64] [i64 800, i64 800]
|
||||
|
||||
// CHECK-HOST: [[OMP_OFFLOAD_ENTRY_LINK_VAR_PTR_NAME:@.+]] = internal unnamed_addr constant [21 x i8]
|
||||
// CHECK-HOST: [[OMP_OFFLOAD_ENTRY_LINK_VAR_PTR:@.+]] = weak constant %struct.__tgt_offload_entry { i64 0, i16 1, i16 1, i32 1, ptr [[VAR_DECL_TGT_LINK_PTR]], ptr [[OMP_OFFLOAD_ENTRY_LINK_VAR_PTR_NAME]], i64 8, i64 0, ptr null }, section "llvm_offload_entries"
|
||||
@ -55,24 +55,24 @@ int bar(int n){
|
||||
// CHECK-HOST: [[N_CASTED:%.+]] = alloca i64
|
||||
// CHECK-HOST: [[SUM_CASTED:%.+]] = alloca i64
|
||||
|
||||
// CHECK-HOST: [[OFFLOAD_BASEPTRS:%.+]] = alloca [3 x ptr]
|
||||
// CHECK-HOST: [[OFFLOAD_PTRS:%.+]] = alloca [3 x ptr]
|
||||
// CHECK-HOST: [[OFFLOAD_BASEPTRS:%.+]] = alloca [2 x ptr]
|
||||
// CHECK-HOST: [[OFFLOAD_PTRS:%.+]] = alloca [2 x ptr]
|
||||
|
||||
// CHECK-HOST: [[LOAD1:%.+]] = load i64, ptr [[N_CASTED]]
|
||||
// CHECK-HOST: [[LOAD2:%.+]] = load i64, ptr [[SUM_CASTED]]
|
||||
|
||||
// CHECK-HOST: [[BPTR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: [[BPTR1:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: store i64 [[LOAD1]], ptr [[BPTR1]]
|
||||
// CHECK-HOST: [[BPTR2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: [[BPTR2:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: store i64 [[LOAD1]], ptr [[BPTR2]]
|
||||
|
||||
// CHECK-HOST: [[BPTR3:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK-HOST: [[BPTR3:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK-HOST: store i64 [[LOAD2]], ptr [[BPTR3]]
|
||||
// CHECK-HOST: [[BPTR4:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK-HOST: [[BPTR4:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK-HOST: store i64 [[LOAD2]], ptr [[BPTR4]]
|
||||
|
||||
// CHECK-HOST: [[BPTR7:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: [[BPTR8:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: [[BPTR7:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK-HOST: [[BPTR8:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOAD_PTRS]], i32 0, i32 0
|
||||
|
||||
// CHECK-HOST: call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr %{{.+}})
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -50,15 +50,15 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23
|
||||
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -90,15 +90,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
|
||||
// CHECK1-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -130,15 +130,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
|
||||
// CHECK1-SAME: (i64 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -184,7 +184,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
@ -202,21 +202,21 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i16 1, ptr [[TMP0]], align 2
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23
|
||||
// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -248,15 +248,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28
|
||||
// CHECK2-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -288,15 +288,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33
|
||||
// CHECK2-SAME: (i32 noundef [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -342,7 +342,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
@ -360,7 +360,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i16 1, ptr [[TMP0]], align 2
|
||||
// CHECK2-NEXT: ret void
|
||||
//
|
||||
|
||||
@ -72,21 +72,21 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[L_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -133,7 +133,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -280,7 +280,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -386,18 +386,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META9]], !align [[META11:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -438,7 +438,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META9]], !align [[META11]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -570,7 +570,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META9]], !align [[META11]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -640,15 +640,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -680,7 +680,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -776,7 +776,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -827,18 +827,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -879,7 +879,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -986,7 +986,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -1055,18 +1055,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1111,7 +1111,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -1259,7 +1259,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -1367,20 +1367,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[V_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1424,7 +1424,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1561,7 +1561,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1632,21 +1632,21 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[L_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1693,7 +1693,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1840,7 +1840,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[L]], ptr [[L_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1946,18 +1946,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META9]], !align [[META11:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1998,7 +1998,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META9]], !align [[META11]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2130,7 +2130,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META9]], !align [[META11]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2200,15 +2200,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2240,7 +2240,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -2336,7 +2336,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -2387,18 +2387,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2439,7 +2439,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -2546,7 +2546,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -2615,18 +2615,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2671,7 +2671,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -2818,7 +2818,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -2922,20 +2922,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[V_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2979,7 +2979,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3116,7 +3116,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3187,21 +3187,21 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[L_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3248,7 +3248,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3393,7 +3393,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[L]], ptr [[L_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3494,18 +3494,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META9]], !align [[META11:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3546,7 +3546,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META9]], !align [[META11]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3676,7 +3676,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META9]], !align [[META11]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3742,15 +3742,15 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
|
||||
// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3782,7 +3782,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -3876,7 +3876,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
|
||||
@ -3923,18 +3923,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44
|
||||
// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3975,7 +3975,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -4080,7 +4080,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
|
||||
@ -4144,18 +4144,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -4200,7 +4200,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -4350,7 +4350,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -4459,20 +4459,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[V_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -4516,7 +4516,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -4651,7 +4651,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
|
||||
@ -30,21 +30,21 @@ int main(int argc, char **argv) {
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
|
||||
// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -91,7 +91,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
@ -231,7 +231,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
@ -330,21 +330,21 @@ int main(int argc, char **argv) {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
|
||||
// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -391,7 +391,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
@ -529,7 +529,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -66,18 +66,18 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -118,7 +118,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -250,7 +250,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -320,27 +320,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
// CHECK1: user_code.entry:
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
||||
// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
@ -370,7 +370,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -466,7 +466,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -517,18 +517,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -569,7 +569,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -676,7 +676,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -745,18 +745,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -801,7 +801,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -949,7 +949,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -1057,20 +1057,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
|
||||
// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR4]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[V_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1114,7 +1114,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1251,7 +1251,7 @@ int bar(int n){
|
||||
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1322,18 +1322,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1374,7 +1374,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1506,7 +1506,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -1576,27 +1576,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
// CHECK2: user_code.entry:
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK2-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK2-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK2-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK2-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
||||
// CHECK2-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
@ -1626,7 +1626,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -1722,7 +1722,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -1773,18 +1773,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
|
||||
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[F_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -1825,7 +1825,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -1932,7 +1932,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[F]], ptr [[F_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK2-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
|
||||
@ -2001,18 +2001,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2057,7 +2057,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -2204,7 +2204,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -2308,20 +2308,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
|
||||
// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR4]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[V_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2365,7 +2365,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2502,7 +2502,7 @@ int bar(int n){
|
||||
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2573,18 +2573,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -2625,7 +2625,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2755,7 +2755,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -2821,27 +2821,27 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
|
||||
// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
// CHECK3: user_code.entry:
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
||||
// CHECK3-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK3-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK3-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK3-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
|
||||
// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
||||
// CHECK3-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
@ -2871,7 +2871,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -2965,7 +2965,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
|
||||
@ -3012,18 +3012,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
|
||||
// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR4]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[F_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3064,7 +3064,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
|
||||
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
||||
@ -3169,7 +3169,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[F]], ptr [[F_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
||||
// CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
|
||||
@ -3233,18 +3233,18 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR4]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3289,7 +3289,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -3439,7 +3439,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
@ -3548,20 +3548,20 @@ int bar(int n){
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
|
||||
// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR4]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR4]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[V_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -3605,7 +3605,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
@ -3740,7 +3740,7 @@ int bar(int n){
|
||||
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: store ptr [[V]], ptr [[V_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
||||
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
|
||||
@ -30,21 +30,21 @@ int main(int argc, char **argv) {
|
||||
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
|
||||
// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -54,9 +54,9 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARGC_CASTED]], align 4
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK1-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP5]] to i1
|
||||
// CHECK1-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK1-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
|
||||
// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
||||
// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
@ -90,7 +90,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
@ -163,21 +163,21 @@ int main(int argc, char **argv) {
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
|
||||
// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -187,9 +187,9 @@ int main(int argc, char **argv) {
|
||||
// CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARGC_CASTED]], align 4
|
||||
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_CASTED]], align 4
|
||||
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
|
||||
// CHECK2-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP5]] to i1
|
||||
// CHECK2-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
|
||||
// CHECK2-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
|
||||
// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
|
||||
// CHECK2-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
|
||||
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
||||
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
|
||||
@ -223,7 +223,7 @@ int main(int argc, char **argv) {
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
|
||||
|
||||
@ -28,14 +28,14 @@ int bar(int n){
|
||||
|
||||
#endif
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13
|
||||
// CHECK-SAME: (i64 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
||||
// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
|
||||
// CHECK-NEXT: store i8 [[TMP0]], ptr [[A_CASTED]], align 1
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
||||
|
||||
@ -77,14 +77,14 @@ int main (int argc, char **argv) {
|
||||
#endif // CK2
|
||||
#endif
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
|
||||
// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -112,20 +112,20 @@ int main (int argc, char **argv) {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP0]], align 4
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15
|
||||
// CHECK1-SAME: (ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -153,20 +153,20 @@ int main (int argc, char **argv) {
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23
|
||||
// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -194,20 +194,20 @@ int main (int argc, char **argv) {
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP0]], align 4
|
||||
// CHECK2-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15
|
||||
// CHECK2-SAME: (ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -235,24 +235,24 @@ int main (int argc, char **argv) {
|
||||
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP0]], align 4
|
||||
// CHECK2-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
|
||||
// CHECK3-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK3-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK3-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -280,24 +280,24 @@ int main (int argc, char **argv) {
|
||||
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK3-NEXT: store i32 0, ptr [[TMP0]], align 4
|
||||
// CHECK3-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53
|
||||
// CHECK3-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] {
|
||||
// CHECK3-NEXT: entry:
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
||||
// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK3-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
||||
// CHECK3-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -325,24 +325,24 @@ int main (int argc, char **argv) {
|
||||
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]]
|
||||
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
||||
// CHECK3-NEXT: store ptr null, ptr [[TMP0]], align 8
|
||||
// CHECK3-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
|
||||
// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK4-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK4-NEXT: entry:
|
||||
// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -370,24 +370,24 @@ int main (int argc, char **argv) {
|
||||
// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 0, ptr [[TMP0]], align 4
|
||||
// CHECK4-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53
|
||||
// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
|
||||
// CHECK4-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], ptr noundef [[ARGC:%.*]]) #[[ATTR0]] {
|
||||
// CHECK4-NEXT: entry:
|
||||
// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK4-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
||||
// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK4-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -415,7 +415,7 @@ int main (int argc, char **argv) {
|
||||
// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4, !nonnull [[META5]], !align [[META6]]
|
||||
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 4
|
||||
// CHECK4-NEXT: store ptr null, ptr [[TMP0]], align 4
|
||||
// CHECK4-NEXT: ret void
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -25,7 +25,7 @@ void target_maps_parallel_integer(int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(ptr noundef nonnull align 4 dereferenceable(4){{.*}}, ptr {{[^)]+}})
|
||||
// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(ptr {{[^,]+}}, ptr noundef nonnull align 4 dereferenceable(4){{.*}}
|
||||
|
||||
// CK1: {{.*}}void {{.*}}target_maps_parallel_integer{{.*}} {
|
||||
|
||||
|
||||
@ -12,4 +12,4 @@ void foo(void) {
|
||||
|
||||
// Check presence of foo() and the outlined target region
|
||||
// CHECK: define{{.*}} void [[FOO:@.+]]()
|
||||
// CHECK: define internal void [[OUTLINEDTARGET:@.+]](ptr {{[^)]*}})
|
||||
// CHECK: define internal void [[OUTLINEDTARGET:@.+]]()
|
||||
|
||||
@ -98,28 +98,28 @@ int main()
|
||||
return 0;
|
||||
}
|
||||
//.
|
||||
// CHECK1: @.offload_sizes = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK1: @.offload_maptypes = private unnamed_addr constant [2 x i64] [i64 547, i64 288]
|
||||
// CHECK1: @.offload_sizes.1 = private unnamed_addr constant [2 x i64] [i64 8000, i64 0]
|
||||
// CHECK1: @.offload_maptypes.2 = private unnamed_addr constant [2 x i64] [i64 547, i64 288]
|
||||
// CHECK1: @.offload_sizes = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK1: @.offload_maptypes = private unnamed_addr constant [1 x i64] [i64 547]
|
||||
// CHECK1: @.offload_sizes.1 = private unnamed_addr constant [1 x i64] [i64 8000]
|
||||
// CHECK1: @.offload_maptypes.2 = private unnamed_addr constant [1 x i64] [i64 547]
|
||||
//.
|
||||
// CHECK2: @.offload_sizes = private unnamed_addr constant [6 x i64] [i64 4, i64 4, i64 4, i64 0, i64 4, i64 0]
|
||||
// CHECK2: @.offload_maptypes = private unnamed_addr constant [6 x i64] [i64 800, i64 547, i64 16384, i64 33, i64 16384, i64 288]
|
||||
// CHECK2: @.offload_sizes.1 = private unnamed_addr constant [6 x i64] [i64 4, i64 12, i64 4, i64 0, i64 4, i64 0]
|
||||
// CHECK2: @.offload_maptypes.2 = private unnamed_addr constant [6 x i64] [i64 800, i64 547, i64 16384, i64 33, i64 16384, i64 288]
|
||||
// CHECK2: @.offload_sizes.3 = private unnamed_addr constant [3 x i64] [i64 4, i64 8, i64 0]
|
||||
// CHECK2: @.offload_maptypes.4 = private unnamed_addr constant [3 x i64] [i64 800, i64 547, i64 288]
|
||||
// CHECK2: @.offload_sizes.5 = private unnamed_addr constant [3 x i64] [i64 4, i64 4, i64 0]
|
||||
// CHECK2: @.offload_maptypes.6 = private unnamed_addr constant [3 x i64] [i64 800, i64 547, i64 288]
|
||||
// CHECK2: @.offload_sizes = private unnamed_addr constant [5 x i64] [i64 4, i64 4, i64 4, i64 0, i64 4]
|
||||
// CHECK2: @.offload_maptypes = private unnamed_addr constant [5 x i64] [i64 800, i64 547, i64 16384, i64 33, i64 16384]
|
||||
// CHECK2: @.offload_sizes.1 = private unnamed_addr constant [5 x i64] [i64 4, i64 12, i64 4, i64 0, i64 4]
|
||||
// CHECK2: @.offload_maptypes.2 = private unnamed_addr constant [5 x i64] [i64 800, i64 547, i64 16384, i64 33, i64 16384]
|
||||
// CHECK2: @.offload_sizes.3 = private unnamed_addr constant [2 x i64] [i64 4, i64 8]
|
||||
// CHECK2: @.offload_maptypes.4 = private unnamed_addr constant [2 x i64] [i64 800, i64 547]
|
||||
// CHECK2: @.offload_sizes.5 = private unnamed_addr constant [2 x i64] [i64 4, i64 4]
|
||||
// CHECK2: @.offload_maptypes.6 = private unnamed_addr constant [2 x i64] [i64 800, i64 547]
|
||||
//.
|
||||
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l32
|
||||
// CHECK-SAME: (ptr noundef [[E:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l32_kernel_environment, ptr [[DYN_PTR]])
|
||||
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
|
||||
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
||||
@ -305,14 +305,14 @@ int main()
|
||||
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[O:%.*]] = alloca [5 x [[CLASS_S2:%.*]]], align 4
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x [10 x [10 x double]]], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [2 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
|
||||
// CHECK1-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[CLASS_S2]]], ptr [[O]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_S2]], ptr [[ARRAY_BEGIN]], i64 5
|
||||
@ -325,98 +325,86 @@ int main()
|
||||
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
|
||||
// CHECK1: arrayctor.cont:
|
||||
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x [[CLASS_S2]]], ptr [[O]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[O]], ptr [[TMP0]], align 8
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[ARRAYIDX]], ptr [[TMP1]], align 8
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP8]], align 4
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 2, ptr [[TMP9]], align 4
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP20]], align 4
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l50.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4
|
||||
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP13]], align 8
|
||||
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 4
|
||||
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l50.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK1: omp_offload.failed:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l50(ptr [[O]], ptr null) #[[ATTR6:[0-9]+]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l50(ptr [[O]]) #[[ATTR6:[0-9]+]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK1: omp_offload.cont:
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP23]], align 8
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP24]], align 8
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 1
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 4, ptr [[TMP31]], align 4
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 2, ptr [[TMP32]], align 4
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP35]], align 8
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP36]], align 8
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP39]], align 8
|
||||
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP40]], align 8
|
||||
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP41]], align 4
|
||||
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
|
||||
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP43]], align 4
|
||||
// CHECK1-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55.region_id, ptr [[KERNEL_ARGS4]])
|
||||
// CHECK1-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
||||
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP20]], align 8
|
||||
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP21]], align 8
|
||||
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
||||
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
||||
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
|
||||
// CHECK1-NEXT: store i32 3, ptr [[TMP25]], align 4
|
||||
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
|
||||
// CHECK1-NEXT: store i32 1, ptr [[TMP26]], align 4
|
||||
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
|
||||
// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8
|
||||
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
|
||||
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8
|
||||
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
|
||||
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP29]], align 8
|
||||
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
|
||||
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP30]], align 8
|
||||
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8
|
||||
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
|
||||
// CHECK1-NEXT: store ptr null, ptr [[TMP32]], align 8
|
||||
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP33]], align 8
|
||||
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
|
||||
// CHECK1-NEXT: store i64 0, ptr [[TMP34]], align 8
|
||||
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
|
||||
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP35]], align 4
|
||||
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
|
||||
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP36]], align 4
|
||||
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
|
||||
// CHECK1-NEXT: store i32 0, ptr [[TMP37]], align 4
|
||||
// CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55.region_id, ptr [[KERNEL_ARGS4]])
|
||||
// CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
|
||||
// CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
||||
// CHECK1: omp_offload.failed5:
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55(ptr [[B]], ptr null) #[[ATTR6]]
|
||||
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55(ptr [[B]]) #[[ATTR6]]
|
||||
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
||||
// CHECK1: omp_offload.cont6:
|
||||
// CHECK1-NEXT: ret i32 0
|
||||
@ -433,13 +421,11 @@ int main()
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l50
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(20) [[O:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(20) [[O:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[O_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[O]], ptr [[O_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[O_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[O_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l50.omp_outlined, ptr [[TMP0]])
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -456,7 +442,7 @@ int main()
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[O]], ptr [[O_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[O_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[O_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
|
||||
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x [[CLASS_S2]]], ptr [[TMP0]], i64 0, i64 0
|
||||
// CHECK1-NEXT: call void @_ZN2S2C1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[O1]])
|
||||
// CHECK1-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[TMP0]] to i64
|
||||
@ -476,7 +462,7 @@ int main()
|
||||
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
|
||||
// CHECK1-NEXT: store i32 [[INC]], ptr [[I]], align 4
|
||||
// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
// CHECK1: for.end:
|
||||
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
|
||||
// CHECK1-NEXT: store ptr [[O1]], ptr [[TMP8]], align 8
|
||||
@ -523,13 +509,11 @@ int main()
|
||||
//
|
||||
//
|
||||
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8000) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8000) [[B:%.*]]) #[[ATTR1]] {
|
||||
// CHECK1-NEXT: entry:
|
||||
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META12:![0-9]+]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META7]], !align [[META13:![0-9]+]]
|
||||
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l55.omp_outlined, ptr [[TMP0]])
|
||||
// CHECK1-NEXT: ret void
|
||||
//
|
||||
@ -555,7 +539,7 @@ int main()
|
||||
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
||||
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META12]]
|
||||
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META7]], !align [[META13]]
|
||||
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
||||
// CHECK1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
|
||||
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
||||
@ -842,33 +826,33 @@ int main()
|
||||
// CHECK2-NEXT: [[SIZE_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[OUTPUT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[SIZE_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
||||
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CHECK2-NEXT: [[SIZE_CASTED4:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [6 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [6 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [6 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES10:%.*]] = alloca [6 x i64], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [5 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [5 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [5 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES10:%.*]] = alloca [5 x i64], align 4
|
||||
// CHECK2-NEXT: [[_TMP11:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_13:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[KERNEL_ARGS18:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK2-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
||||
// CHECK2-NEXT: [[SIZE_CASTED21:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK2-NEXT: [[SIZE_CASTED29:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS31:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS32:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS33:%.*]] = alloca [3 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS31:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS32:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS33:%.*]] = alloca [2 x ptr], align 4
|
||||
// CHECK2-NEXT: [[KERNEL_ARGS34:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
||||
// CHECK2-NEXT: store ptr [[INPUT]], ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
@ -887,319 +871,293 @@ int main()
|
||||
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
|
||||
// CHECK2-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
|
||||
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 48, i1 false)
|
||||
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 40, i1 false)
|
||||
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP11]], align 4
|
||||
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP12]], align 4
|
||||
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP13]], align 4
|
||||
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[TMP4]], ptr [[TMP14]], align 4
|
||||
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX]], ptr [[TMP15]], align 4
|
||||
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP16]], align 4
|
||||
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[OUTPUT_ADDR]], ptr [[TMP17]], align 4
|
||||
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX]], ptr [[TMP18]], align 4
|
||||
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP19]], align 4
|
||||
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP6]], ptr [[TMP20]], align 4
|
||||
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX1]], ptr [[TMP21]], align 4
|
||||
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
||||
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store i64 [[TMP10]], ptr [[TMP22]], align 4
|
||||
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP23]], align 4
|
||||
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[INPUT_ADDR]], ptr [[TMP24]], align 4
|
||||
// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX1]], ptr [[TMP25]], align 4
|
||||
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP26]], align 4
|
||||
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP27]], align 4
|
||||
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP28]], align 4
|
||||
// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP29]], align 4
|
||||
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP33]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP34]], 0
|
||||
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP30]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
||||
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP31]], 0
|
||||
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
||||
// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
|
||||
// CHECK2-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4
|
||||
// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP35]], 1
|
||||
// CHECK2-NEXT: [[TMP36:%.*]] = zext i32 [[ADD]] to i64
|
||||
// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 4, ptr [[TMP37]], align 4
|
||||
// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 6, ptr [[TMP38]], align 4
|
||||
// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP30]], ptr [[TMP39]], align 4
|
||||
// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP31]], ptr [[TMP40]], align 4
|
||||
// CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[TMP32]], ptr [[TMP41]], align 4
|
||||
// CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes, ptr [[TMP42]], align 4
|
||||
// CHECK2-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP43]], align 4
|
||||
// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP44]], align 4
|
||||
// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 [[TMP36]], ptr [[TMP45]], align 8
|
||||
// CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP46]], align 8
|
||||
// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
|
||||
// CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4
|
||||
// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP49]], align 4
|
||||
// CHECK2-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l69.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK2-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
|
||||
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP32]], 1
|
||||
// CHECK2-NEXT: [[TMP33:%.*]] = zext i32 [[ADD]] to i64
|
||||
// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 3, ptr [[TMP34]], align 4
|
||||
// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 5, ptr [[TMP35]], align 4
|
||||
// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP27]], ptr [[TMP36]], align 4
|
||||
// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP28]], ptr [[TMP37]], align 4
|
||||
// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[TMP29]], ptr [[TMP38]], align 4
|
||||
// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes, ptr [[TMP39]], align 4
|
||||
// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP40]], align 4
|
||||
// CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP41]], align 4
|
||||
// CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 [[TMP33]], ptr [[TMP42]], align 8
|
||||
// CHECK2-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP43]], align 8
|
||||
// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP44]], align 4
|
||||
// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
|
||||
// CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP46]], align 4
|
||||
// CHECK2-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l69.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CHECK2-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
||||
// CHECK2: omp_offload.failed:
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l69(i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l69(i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]]
|
||||
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
||||
// CHECK2: omp_offload.cont:
|
||||
// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP52]], ptr [[SIZE_CASTED4]], align 4
|
||||
// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[SIZE_CASTED4]], align 4
|
||||
// CHECK2-NEXT: [[TMP49:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP49]], ptr [[SIZE_CASTED4]], align 4
|
||||
// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[SIZE_CASTED4]], align 4
|
||||
// CHECK2-NEXT: [[TMP51:%.*]] = load ptr, ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP52:%.*]] = load ptr, ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP53:%.*]] = load ptr, ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP54:%.*]] = load ptr, ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP54]], i32 0
|
||||
// CHECK2-NEXT: [[TMP55:%.*]] = load ptr, ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP56:%.*]] = load ptr, ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP57:%.*]] = load ptr, ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP57]], i32 0
|
||||
// CHECK2-NEXT: [[TMP58:%.*]] = load ptr, ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP59:%.*]] = load ptr, ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP59]], i32 0
|
||||
// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP60]], 4
|
||||
// CHECK2-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
|
||||
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES10]], ptr align 4 @.offload_sizes.1, i32 48, i1 false)
|
||||
// CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP53]], ptr [[TMP63]], align 4
|
||||
// CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP53]], ptr [[TMP64]], align 4
|
||||
// CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP56:%.*]] = load ptr, ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP56]], i32 0
|
||||
// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP58:%.*]] = mul nuw i32 [[TMP57]], 4
|
||||
// CHECK2-NEXT: [[TMP59:%.*]] = sext i32 [[TMP58]] to i64
|
||||
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES10]], ptr align 4 @.offload_sizes.1, i32 40, i1 false)
|
||||
// CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP50]], ptr [[TMP60]], align 4
|
||||
// CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP50]], ptr [[TMP61]], align 4
|
||||
// CHECK2-NEXT: [[TMP62:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP62]], align 4
|
||||
// CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[TMP53]], ptr [[TMP63]], align 4
|
||||
// CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX5]], ptr [[TMP64]], align 4
|
||||
// CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP65]], align 4
|
||||
// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[TMP56]], ptr [[TMP66]], align 4
|
||||
// CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[OUTPUT_ADDR]], ptr [[TMP66]], align 4
|
||||
// CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX5]], ptr [[TMP67]], align 4
|
||||
// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP68]], align 4
|
||||
// CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[OUTPUT_ADDR]], ptr [[TMP69]], align 4
|
||||
// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX5]], ptr [[TMP70]], align 4
|
||||
// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP71]], align 4
|
||||
// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP58]], ptr [[TMP72]], align 4
|
||||
// CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP73]], align 4
|
||||
// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES10]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store i64 [[TMP62]], ptr [[TMP74]], align 4
|
||||
// CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 3
|
||||
// CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP55]], ptr [[TMP69]], align 4
|
||||
// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP70]], align 4
|
||||
// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES10]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store i64 [[TMP59]], ptr [[TMP71]], align 4
|
||||
// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP72]], align 4
|
||||
// CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[INPUT_ADDR]], ptr [[TMP73]], align 4
|
||||
// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP74]], align 4
|
||||
// CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP75]], align 4
|
||||
// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[INPUT_ADDR]], ptr [[TMP76]], align 4
|
||||
// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX6]], ptr [[TMP77]], align 4
|
||||
// CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP78]], align 4
|
||||
// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP79]], align 4
|
||||
// CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP80]], align 4
|
||||
// CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP81]], align 4
|
||||
// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP83:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES10]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP85]], ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP86]], 0
|
||||
// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES10]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP79]], ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_12]], align 4
|
||||
// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP80]], 0
|
||||
// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1
|
||||
// CHECK2-NEXT: [[SUB16:%.*]] = sub nsw i32 [[DIV15]], 1
|
||||
// CHECK2-NEXT: store i32 [[SUB16]], ptr [[DOTCAPTURE_EXPR_13]], align 4
|
||||
// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4
|
||||
// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP87]], 1
|
||||
// CHECK2-NEXT: [[TMP88:%.*]] = zext i32 [[ADD17]] to i64
|
||||
// CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 4, ptr [[TMP89]], align 4
|
||||
// CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 6, ptr [[TMP90]], align 4
|
||||
// CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP82]], ptr [[TMP91]], align 4
|
||||
// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP83]], ptr [[TMP92]], align 4
|
||||
// CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[TMP84]], ptr [[TMP93]], align 4
|
||||
// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP94]], align 4
|
||||
// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP95]], align 4
|
||||
// CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP96]], align 4
|
||||
// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 [[TMP88]], ptr [[TMP97]], align 8
|
||||
// CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP98]], align 8
|
||||
// CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP99]], align 4
|
||||
// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP100]], align 4
|
||||
// CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP101]], align 4
|
||||
// CHECK2-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l73.region_id, ptr [[KERNEL_ARGS18]])
|
||||
// CHECK2-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
|
||||
// CHECK2-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4
|
||||
// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP81]], 1
|
||||
// CHECK2-NEXT: [[TMP82:%.*]] = zext i32 [[ADD17]] to i64
|
||||
// CHECK2-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 3, ptr [[TMP83]], align 4
|
||||
// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 5, ptr [[TMP84]], align 4
|
||||
// CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP76]], ptr [[TMP85]], align 4
|
||||
// CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP77]], ptr [[TMP86]], align 4
|
||||
// CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr [[TMP78]], ptr [[TMP87]], align 4
|
||||
// CHECK2-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP88]], align 4
|
||||
// CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP89]], align 4
|
||||
// CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP90]], align 4
|
||||
// CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 [[TMP82]], ptr [[TMP91]], align 8
|
||||
// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP92]], align 8
|
||||
// CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP93]], align 4
|
||||
// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP94]], align 4
|
||||
// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS18]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP95]], align 4
|
||||
// CHECK2-NEXT: [[TMP96:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l73.region_id, ptr [[KERNEL_ARGS18]])
|
||||
// CHECK2-NEXT: [[TMP97:%.*]] = icmp ne i32 [[TMP96]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP97]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
|
||||
// CHECK2: omp_offload.failed19:
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l73(i32 [[TMP53]], ptr [[TMP54]], ptr [[TMP55]], ptr null) #[[ATTR2]]
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l73(i32 [[TMP50]], ptr [[TMP51]], ptr [[TMP52]]) #[[ATTR2]]
|
||||
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]]
|
||||
// CHECK2: omp_offload.cont20:
|
||||
// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP104]], ptr [[SIZE_CASTED21]], align 4
|
||||
// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[SIZE_CASTED21]], align 4
|
||||
// CHECK2-NEXT: [[TMP98:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP98]], ptr [[SIZE_CASTED21]], align 4
|
||||
// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[SIZE_CASTED21]], align 4
|
||||
// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds nuw [10 x i32], ptr [[A]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP105]], ptr [[TMP106]], align 4
|
||||
// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP105]], ptr [[TMP107]], align 4
|
||||
// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP108]], align 4
|
||||
// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[TMP109]], align 4
|
||||
// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX22]], ptr [[TMP110]], align 4
|
||||
// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP111]], align 4
|
||||
// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP112]], align 4
|
||||
// CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP113]], align 4
|
||||
// CHECK2-NEXT: [[TMP114:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2
|
||||
// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP99]], ptr [[TMP100]], align 4
|
||||
// CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP99]], ptr [[TMP101]], align 4
|
||||
// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP102]], align 4
|
||||
// CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[TMP103]], align 4
|
||||
// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX22]], ptr [[TMP104]], align 4
|
||||
// CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP105]], align 4
|
||||
// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 3, ptr [[TMP108]], align 4
|
||||
// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 2, ptr [[TMP109]], align 4
|
||||
// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP106]], ptr [[TMP110]], align 4
|
||||
// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP107]], ptr [[TMP111]], align 4
|
||||
// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr @.offload_sizes.3, ptr [[TMP112]], align 4
|
||||
// CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP113]], align 4
|
||||
// CHECK2-NEXT: [[TMP114:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP114]], align 4
|
||||
// CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 4, ptr [[TMP117]], align 4
|
||||
// CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 3, ptr [[TMP118]], align 4
|
||||
// CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 4
|
||||
// CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 4
|
||||
// CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr @.offload_sizes.3, ptr [[TMP121]], align 4
|
||||
// CHECK2-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP122]], align 4
|
||||
// CHECK2-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP123]], align 4
|
||||
// CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP124]], align 4
|
||||
// CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP125]], align 8
|
||||
// CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP126]], align 8
|
||||
// CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP127]], align 4
|
||||
// CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
|
||||
// CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP129]], align 4
|
||||
// CHECK2-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l78.region_id, ptr [[KERNEL_ARGS26]])
|
||||
// CHECK2-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
|
||||
// CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP115]], align 4
|
||||
// CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP116]], align 8
|
||||
// CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP117]], align 8
|
||||
// CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP118]], align 4
|
||||
// CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP119]], align 4
|
||||
// CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP120]], align 4
|
||||
// CHECK2-NEXT: [[TMP121:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l78.region_id, ptr [[KERNEL_ARGS26]])
|
||||
// CHECK2-NEXT: [[TMP122:%.*]] = icmp ne i32 [[TMP121]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP122]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
|
||||
// CHECK2: omp_offload.failed27:
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l78(i32 [[TMP105]], ptr [[A]], ptr null) #[[ATTR2]]
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l78(i32 [[TMP99]], ptr [[A]]) #[[ATTR2]]
|
||||
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT28]]
|
||||
// CHECK2: omp_offload.cont28:
|
||||
// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP132]], ptr [[SIZE_CASTED29]], align 4
|
||||
// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[SIZE_CASTED29]], align 4
|
||||
// CHECK2-NEXT: [[TMP123:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP123]], ptr [[SIZE_CASTED29]], align 4
|
||||
// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[SIZE_CASTED29]], align 4
|
||||
// CHECK2-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 3
|
||||
// CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP133]], ptr [[TMP134]], align 4
|
||||
// CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP133]], ptr [[TMP135]], align 4
|
||||
// CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS33]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP136]], align 4
|
||||
// CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[TMP137]], align 4
|
||||
// CHECK2-NEXT: [[TMP138:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX30]], ptr [[TMP138]], align 4
|
||||
// CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS33]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP124]], ptr [[TMP125]], align 4
|
||||
// CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 [[TMP124]], ptr [[TMP126]], align 4
|
||||
// CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS33]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP127]], align 4
|
||||
// CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[TMP128]], align 4
|
||||
// CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr [[ARRAYIDX30]], ptr [[TMP129]], align 4
|
||||
// CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS33]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP130]], align 4
|
||||
// CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP132:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 3, ptr [[TMP133]], align 4
|
||||
// CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 2, ptr [[TMP134]], align 4
|
||||
// CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP131]], ptr [[TMP135]], align 4
|
||||
// CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP132]], ptr [[TMP136]], align 4
|
||||
// CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr @.offload_sizes.5, ptr [[TMP137]], align 4
|
||||
// CHECK2-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP138]], align 4
|
||||
// CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP139]], align 4
|
||||
// CHECK2-NEXT: [[TMP140:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 2
|
||||
// CHECK2-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP140]], align 4
|
||||
// CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP141]], align 4
|
||||
// CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS33]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP142]], align 4
|
||||
// CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store i32 4, ptr [[TMP145]], align 4
|
||||
// CHECK2-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 1
|
||||
// CHECK2-NEXT: store i32 3, ptr [[TMP146]], align 4
|
||||
// CHECK2-NEXT: [[TMP147:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 2
|
||||
// CHECK2-NEXT: store ptr [[TMP143]], ptr [[TMP147]], align 4
|
||||
// CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 4
|
||||
// CHECK2-NEXT: [[TMP149:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 4
|
||||
// CHECK2-NEXT: store ptr @.offload_sizes.5, ptr [[TMP149]], align 4
|
||||
// CHECK2-NEXT: [[TMP150:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 5
|
||||
// CHECK2-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP150]], align 4
|
||||
// CHECK2-NEXT: [[TMP151:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 6
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP151]], align 4
|
||||
// CHECK2-NEXT: [[TMP152:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 7
|
||||
// CHECK2-NEXT: store ptr null, ptr [[TMP152]], align 4
|
||||
// CHECK2-NEXT: [[TMP153:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP153]], align 8
|
||||
// CHECK2-NEXT: [[TMP154:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP154]], align 8
|
||||
// CHECK2-NEXT: [[TMP155:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP155]], align 4
|
||||
// CHECK2-NEXT: [[TMP156:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP156]], align 4
|
||||
// CHECK2-NEXT: [[TMP157:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP157]], align 4
|
||||
// CHECK2-NEXT: [[TMP158:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l81.region_id, ptr [[KERNEL_ARGS34]])
|
||||
// CHECK2-NEXT: [[TMP159:%.*]] = icmp ne i32 [[TMP158]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP159]], label [[OMP_OFFLOAD_FAILED35:%.*]], label [[OMP_OFFLOAD_CONT36:%.*]]
|
||||
// CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 8
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP141]], align 8
|
||||
// CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 9
|
||||
// CHECK2-NEXT: store i64 0, ptr [[TMP142]], align 8
|
||||
// CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 10
|
||||
// CHECK2-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP143]], align 4
|
||||
// CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 11
|
||||
// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP144]], align 4
|
||||
// CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS34]], i32 0, i32 12
|
||||
// CHECK2-NEXT: store i32 0, ptr [[TMP145]], align 4
|
||||
// CHECK2-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l81.region_id, ptr [[KERNEL_ARGS34]])
|
||||
// CHECK2-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
|
||||
// CHECK2-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED35:%.*]], label [[OMP_OFFLOAD_CONT36:%.*]]
|
||||
// CHECK2: omp_offload.failed35:
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l81(i32 [[TMP133]], ptr [[A]], ptr null) #[[ATTR2]]
|
||||
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l81(i32 [[TMP124]], ptr [[A]]) #[[ATTR2]]
|
||||
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT36]]
|
||||
// CHECK2: omp_offload.cont36:
|
||||
// CHECK2-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l69
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef [[OUTPUT:%.*]], ptr noundef [[INPUT:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef [[OUTPUT:%.*]], ptr noundef [[INPUT:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[SIZE_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[OUTPUT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[INPUT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[SIZE_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[OUTPUT]], ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[INPUT]], ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP0]], ptr [[SIZE_CASTED]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE_CASTED]], align 4
|
||||
@ -1515,17 +1473,15 @@ int main()
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l73
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef [[OUTPUT:%.*]], ptr noundef [[INPUT:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef [[OUTPUT:%.*]], ptr noundef [[INPUT:%.*]]) #[[ATTR1]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[SIZE_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[OUTPUT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[INPUT_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[SIZE_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[OUTPUT]], ptr [[OUTPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[INPUT]], ptr [[INPUT_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP0]], ptr [[SIZE_CASTED]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE_CASTED]], align 4
|
||||
@ -1931,16 +1887,14 @@ int main()
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l78
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR1]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[SIZE_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[SIZE_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META13:![0-9]+]], !align [[META14:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[SIZE_CASTED]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIZE_CASTED]], align 4
|
||||
@ -1962,7 +1916,7 @@ int main()
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META13]], !align [[META14]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META14]], !align [[META15]]
|
||||
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [10 x i32], ptr [[TMP0]], i32 0, i32 0
|
||||
// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [10 x i32], ptr [[TMP0]], i32 0, i32 1
|
||||
// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x i32], ptr [[A2]], i32 0, i32 0
|
||||
@ -1994,7 +1948,7 @@ int main()
|
||||
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
|
||||
// CHECK2-NEXT: store i32 [[INC]], ptr [[I]], align 4
|
||||
// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
|
||||
// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
|
||||
// CHECK2: for.end:
|
||||
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr [[A2]], ptr [[TMP10]], align 4
|
||||
@ -2074,16 +2028,14 @@ int main()
|
||||
//
|
||||
//
|
||||
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3sumPiiS__l81
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR1]] {
|
||||
// CHECK2-SAME: (i32 noundef [[SIZE:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR1]] {
|
||||
// CHECK2-NEXT: entry:
|
||||
// CHECK2-NEXT: [[SIZE_ADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CHECK2-NEXT: [[SIZE_CASTED:%.*]] = alloca i32, align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META13]], !align [[META14]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META14]], !align [[META15]]
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[SIZE_CASTED]], align 4
|
||||
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIZE_CASTED]], align 4
|
||||
@ -2105,7 +2057,7 @@ int main()
|
||||
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
||||
// CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4
|
||||
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META13]], !align [[META14]]
|
||||
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META14]], !align [[META15]]
|
||||
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 3
|
||||
// CHECK2-NEXT: store i32 0, ptr [[A1]], align 4
|
||||
// CHECK2-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[TMP0]] to i32
|
||||
@ -2126,7 +2078,7 @@ int main()
|
||||
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
|
||||
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
|
||||
// CHECK2-NEXT: store i32 [[INC]], ptr [[I]], align 4
|
||||
// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
|
||||
// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
|
||||
// CHECK2: for.end:
|
||||
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0
|
||||
// CHECK2-NEXT: store ptr [[A1]], ptr [[TMP9]], align 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -4,7 +4,7 @@
|
||||
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple spirv64-intel -fopenmp-targets=spirv64-intel -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-host.bc -DTEAMS -o - | FileCheck %s
|
||||
// expected-no-diagnostics
|
||||
|
||||
// CHECK: define weak_odr protected spir_kernel void @__omp_offloading_{{.*}}(ptr addrspace(1) noundef align 4 dereferenceable(128) %{{.*}}, ptr addrspace(1) noalias noundef %{{.*}})
|
||||
// CHECK: define weak_odr protected spir_kernel void @__omp_offloading_{{.*}}(ptr addrspace(1) noalias noundef %{{.*}}, ptr addrspace(1) noundef align 4 dereferenceable(128) %{{.*}})
|
||||
|
||||
int main() {
|
||||
int x[32] = {0};
|
||||
|
||||
@ -69,30 +69,30 @@
|
||||
// CHECK-DAG: [[S2:%.+]] = type { i32, i32, i32 }
|
||||
// CHECK-DAG: [[ENTTY:%.+]] = type { i64, i16, i16, i32, ptr, ptr, i64, i64, ptr }
|
||||
// CHECK-DAG: [[ANON_T:%.+]] = type { ptr, i32, i32 }
|
||||
// CHECK-32-DAG: [[KMP_PRIVATES_T]] = type { [3 x i64], ptr, i32, [3 x ptr], [3 x ptr] }
|
||||
// CHECK-64-DAG: [[KMP_PRIVATES_T]] = type { ptr, [3 x ptr], [3 x ptr], [3 x i64], i32 }
|
||||
// CHECK-32-DAG: [[KMP_PRIVATES_T]] = type { [2 x i64], ptr, i32, [2 x ptr], [2 x ptr] }
|
||||
// CHECK-64-DAG: [[KMP_PRIVATES_T]] = type { ptr, [2 x ptr], [2 x ptr], [2 x i64], i32 }
|
||||
|
||||
// TCHECK: [[ENTTY:%.+]] = type { i64, i16, i16, i32, ptr, ptr, i64, i64, ptr }
|
||||
|
||||
// We have 9 target regions, but only 8 that actually will generate offloading
|
||||
// code and have mapped arguments, and only 6 have all-constant map sizes.
|
||||
|
||||
// CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [3 x i64] [i64 0, i64 4, i64 0]
|
||||
// CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [3 x i64] [i64 544, i64 800, i64 288]
|
||||
// CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [2 x i{{32|64}}] [i64 2, i64 0]
|
||||
// CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [3 x i64] [i64 4, i64 2, i64 0]
|
||||
// CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [3 x i64] [i64 800, i64 800, i64 288]
|
||||
// CHECK-DAG: [[SIZET4:@.+]] = private unnamed_addr constant [10 x i64] [i64 4, i64 40, i64 {{4|8}}, i64 0, i64 400, i64 {{4|8}}, i64 {{4|8}}, i64 0, i64 {{12|16}}, i64 0]
|
||||
// CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [10 x i64] [i64 800, i64 547, i64 800, i64 547, i64 547, i64 800, i64 800, i64 547, i64 547, i64 288]
|
||||
// CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [4 x i64] [i64 4, i64 2, i64 40, i64 0]
|
||||
// CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [4 x i64] [i64 800, i64 800, i64 547, i64 288]
|
||||
// CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [5 x i64] [i64 4, i64 2, i64 1, i64 40, i64 0]
|
||||
// CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [5 x i64] [i64 800, i64 800, i64 800, i64 547, i64 288]
|
||||
// CHECK-DAG: [[SIZET7:@.+]] = private unnamed_addr constant [6 x i64] [i64 8, i64 4, i64 {{4|8}}, i64 {{4|8}}, i64 0, i64 0]
|
||||
// CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [6 x i64] [i64 547, i64 800, i64 800, i64 800, i64 547, i64 288]
|
||||
// CHECK-DAG: [[SIZET9:@.+]] = private unnamed_addr constant [2 x i64] [i64 12, i64 0]
|
||||
// CHECK-DAG: [[MAPT10:@.+]] = private unnamed_addr constant [2 x i64] [i64 35, i64 288]
|
||||
// CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [2 x i64] [i64 0, i64 4]
|
||||
// CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [2 x i64] [i64 544, i64 800]
|
||||
// CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [1 x i{{32|64}}] [i64 2]
|
||||
// CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i64] [i64 4, i64 2]
|
||||
// CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i64] [i64 800, i64 800]
|
||||
// CHECK-DAG: [[SIZET4:@.+]] = private unnamed_addr constant [9 x i64] [i64 4, i64 40, i64 {{4|8}}, i64 0, i64 400, i64 {{4|8}}, i64 {{4|8}}, i64 0, i64 {{12|16}}]
|
||||
// CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [9 x i64] [i64 800, i64 547, i64 800, i64 547, i64 547, i64 800, i64 800, i64 547, i64 547]
|
||||
// CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i64] [i64 4, i64 2, i64 40]
|
||||
// CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i64] [i64 800, i64 800, i64 547]
|
||||
// CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [4 x i64] [i64 4, i64 2, i64 1, i64 40]
|
||||
// CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [4 x i64] [i64 800, i64 800, i64 800, i64 547]
|
||||
// CHECK-DAG: [[SIZET7:@.+]] = private unnamed_addr constant [5 x i64] [i64 8, i64 4, i64 {{4|8}}, i64 {{4|8}}, i64 0]
|
||||
// CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [5 x i64] [i64 547, i64 800, i64 800, i64 800, i64 547]
|
||||
// CHECK-DAG: [[SIZET9:@.+]] = private unnamed_addr constant [1 x i64] [i64 12]
|
||||
// CHECK-DAG: [[MAPT10:@.+]] = private unnamed_addr constant [1 x i64] [i64 35]
|
||||
// CHECK-DAG: @{{.*}} = weak constant i8 0
|
||||
// CHECK-DAG: @{{.*}} = weak constant i8 0
|
||||
// CHECK-DAG: @{{.*}} = weak constant i8 0
|
||||
@ -125,9 +125,9 @@ extern int global;
|
||||
|
||||
// CHECK: define {{.*}}[[FOO:@.+]](
|
||||
int foo(int n) {
|
||||
// CHECK: [[OFFLOADBPTR:%.+]] = alloca [3 x ptr], align
|
||||
// CHECK: [[OFFLOADPTR:%.+]] = alloca [3 x ptr], align
|
||||
// CHECK: [[OFFLOADMAPPER:%.+]] = alloca [3 x ptr], align
|
||||
// CHECK: [[OFFLOADBPTR:%.+]] = alloca [2 x ptr], align
|
||||
// CHECK: [[OFFLOADPTR:%.+]] = alloca [2 x ptr], align
|
||||
// CHECK: [[OFFLOADMAPPER:%.+]] = alloca [2 x ptr], align
|
||||
int a = 0;
|
||||
short aa = 0;
|
||||
float b[10];
|
||||
@ -145,33 +145,33 @@ int foo(int n) {
|
||||
// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT0:@.+]](ptr null)
|
||||
// CHECK: call void [[HVT0:@.+]]()
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
#pragma omp target device(global + a)
|
||||
{
|
||||
}
|
||||
|
||||
// CHECK: [[BPRGEP:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOADBPTR]], i32 0, i32 0
|
||||
// CHECK: [[PRGEP:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOADPTR]], i32 0, i32 0
|
||||
// CHECK: [[BPRGEP:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOADBPTR]], i32 0, i32 0
|
||||
// CHECK: [[PRGEP:%.+]] = getelementptr inbounds [3 x ptr], ptr [[OFFLOADPTR]], i32 0, i32 0
|
||||
// CHECK: [[BPRGEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOADBPTR]], i32 0, i32 0
|
||||
// CHECK: [[PRGEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOADPTR]], i32 0, i32 0
|
||||
// CHECK: [[BPRGEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOADBPTR]], i32 0, i32 0
|
||||
// CHECK: [[PRGEP:%.+]] = getelementptr inbounds [2 x ptr], ptr [[OFFLOADPTR]], i32 0, i32 0
|
||||
// CHECK: [[DEVICE:%.+]] = sext i32 {{%.+}} to i64
|
||||
// CHECK-32: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{.+}}, i32 %0, i32 1, i32 76, i32 12, ptr [[OMP_TASK_ENTRY:@.+]], i64 [[DEVICE]])
|
||||
// CHECK-64: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{.+}}, i32 %0, i32 1, i64 128, i64 16, ptr [[OMP_TASK_ENTRY:@.+]], i64 [[DEVICE]])
|
||||
// CHECK-32: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{.+}}, i32 %0, i32 1, i32 60, i32 12, ptr [[OMP_TASK_ENTRY:@.+]], i64 [[DEVICE]])
|
||||
// CHECK-64: [[TASK:%.+]] = call ptr @__kmpc_omp_target_task_alloc(ptr {{.+}}, i32 %0, i32 1, i64 104, i64 16, ptr [[OMP_TASK_ENTRY:@.+]], i64 [[DEVICE]])
|
||||
// CHECK: [[TASK_WITH_PRIVATES_GEP:%.+]] = getelementptr inbounds nuw [[KMP_TASK_T_WITH_PRIVATES]], ptr [[TASK]], i32 0, i32 1
|
||||
// CHECK-32: [[SIZEGEP:%.+]] = getelementptr inbounds nuw [[KMP_PRIVATES_T]], ptr [[TASK_WITH_PRIVATES_GEP]], i32 0, i32 0
|
||||
// CHECK-32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SIZEGEP]], ptr align 4 [[SIZET]], i32 24, i1 false)
|
||||
// CHECK-32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SIZEGEP]], ptr align 4 [[SIZET]], i32 16, i1 false)
|
||||
// CHECK-32: [[FPBPRGEP:%.+]] = getelementptr inbounds nuw [[KMP_PRIVATES_T]], ptr [[TASK_WITH_PRIVATES_GEP]], i32 0, i32 3
|
||||
// CHECK-32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[FPBPRGEP]], ptr align 4 [[BPRGEP]], i32 12, i1 false)
|
||||
// CHECK-32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[FPBPRGEP]], ptr align 4 [[BPRGEP]], i32 8, i1 false)
|
||||
// CHECK-32: [[FPPRGEP:%.+]] = getelementptr inbounds nuw [[KMP_PRIVATES_T]], ptr [[TASK_WITH_PRIVATES_GEP]], i32 0, i32 4
|
||||
// CHECK-32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[FPPRGEP]], ptr align 4 [[PRGEP]], i32 12, i1 false)
|
||||
// CHECK-32: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[FPPRGEP]], ptr align 4 [[PRGEP]], i32 8, i1 false)
|
||||
// CHECK-64: [[FPBPRGEP:%.+]] = getelementptr inbounds nuw [[KMP_PRIVATES_T]], ptr [[TASK_WITH_PRIVATES_GEP]], i32 0, i32 1
|
||||
// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPRGEP]], ptr align 8 [[BPRGEP]], i64 24, i1 false)
|
||||
// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPRGEP]], ptr align 8 [[BPRGEP]], i64 16, i1 false)
|
||||
// CHECK-64: [[FPPRGEP:%.+]] = getelementptr inbounds nuw [[KMP_PRIVATES_T]], ptr [[TASK_WITH_PRIVATES_GEP]], i32 0, i32 2
|
||||
// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPRGEP]], ptr align 8 [[PRGEP]], i64 24, i1 false)
|
||||
// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPRGEP]], ptr align 8 [[PRGEP]], i64 16, i1 false)
|
||||
// CHECK-64: [[SIZEGEP:%.+]] = getelementptr inbounds nuw [[KMP_PRIVATES_T]], ptr [[TASK_WITH_PRIVATES_GEP]], i32 0, i32 3
|
||||
// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[SIZEGEP]], ptr align 8 [[SIZET]], i64 24, i1 false)
|
||||
// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[SIZEGEP]], ptr align 8 [[SIZET]], i64 16, i1 false)
|
||||
// CHECK: call i32 @__kmpc_omp_task(ptr {{.+}}, i32 {{.+}}, ptr [[TASK]])
|
||||
#pragma omp target device(global + a) nowait
|
||||
{
|
||||
@ -180,7 +180,7 @@ int foo(int n) {
|
||||
local1 = global;
|
||||
}
|
||||
|
||||
// CHECK: call void [[HVT1:@.+]](i[[SZ:32|64]] {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT1:@.+]](i[[SZ:32|64]] {{[^,]+}})
|
||||
#pragma omp target if(0) firstprivate(global)
|
||||
{
|
||||
global += 1;
|
||||
@ -191,17 +191,17 @@ int foo(int n) {
|
||||
// CHECK-DAG: store ptr [[BP:%.+]], ptr [[BPARG]]
|
||||
// CHECK-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[P:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[BP]] = getelementptr inbounds [2 x ptr], ptr [[BPR:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[P]] = getelementptr inbounds [2 x ptr], ptr [[PR:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BPR]], i32 0, i32 [[IDX0:[0-9]+]]
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[PR]], i32 0, i32 [[IDX0]]
|
||||
// CHECK-DAG: [[BP]] = getelementptr inbounds [1 x ptr], ptr [[BPR:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[P]] = getelementptr inbounds [1 x ptr], ptr [[PR:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [1 x ptr], ptr [[BPR]], i32 0, i32 [[IDX0:[0-9]+]]
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [1 x ptr], ptr [[PR]], i32 0, i32 [[IDX0]]
|
||||
// CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], ptr [[BPADDR0]]
|
||||
// CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], ptr [[PADDR0]]
|
||||
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
#pragma omp target if (1)
|
||||
@ -217,27 +217,27 @@ int foo(int n) {
|
||||
// CHECK-DAG: store ptr [[BPR:%.+]], ptr [[BPARG]]
|
||||
// CHECK-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[PR:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [3 x ptr], ptr [[BP:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [3 x ptr], ptr [[P:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [2 x ptr], ptr [[BP:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [2 x ptr], ptr [[P:%[^,]+]], i32 0, i32 0
|
||||
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], ptr [[BPADDR0]]
|
||||
// CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], ptr [[PADDR0]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BP]], i32 0, i32 1
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[P]], i32 0, i32 1
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BP]], i32 0, i32 1
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x ptr], ptr [[P]], i32 0, i32 1
|
||||
// CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], ptr [[BPADDR1]]
|
||||
// CHECK-DAG: store i[[SZ]] [[P1:%[^,]+]], ptr [[PADDR1]]
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
// CHECK-NEXT: br label %[[IFEND:.+]]
|
||||
// CHECK: [[IFELSE]]
|
||||
// CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[IFEND]]
|
||||
|
||||
// CHECK: [[IFEND]]
|
||||
@ -274,30 +274,30 @@ int foo(int n) {
|
||||
// CHECK-DAG: store ptr [[PR:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[SARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZ4:%.+]], ptr [[SARG]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [10 x ptr], ptr [[BP:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [10 x ptr], ptr [[P:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZ4]] = getelementptr inbounds [10 x i64], ptr [[PSZ:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [9 x ptr], ptr [[BP:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [9 x ptr], ptr [[P:%[^,]+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZ4]] = getelementptr inbounds [9 x i64], ptr [[PSZ:%[^,]+]], i32 0, i32 0
|
||||
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX0:0]]
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX0]]
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX1:1]]
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX1]]
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX2:2]]
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX2]]
|
||||
// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX3:3]]
|
||||
// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX3]]
|
||||
// CHECK-DAG: [[PSZ3:%.+]] = getelementptr inbounds [10 x i64], ptr [[PSZ]], i32 0, i32 [[IDX3]]
|
||||
// CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX4:4]]
|
||||
// CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX4]]
|
||||
// CHECK-DAG: [[BPADDR5:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX5:5]]
|
||||
// CHECK-DAG: [[PADDR5:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX5]]
|
||||
// CHECK-DAG: [[BPADDR6:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX6:6]]
|
||||
// CHECK-DAG: [[PADDR6:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX6]]
|
||||
// CHECK-DAG: [[BPADDR7:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX7:7]]
|
||||
// CHECK-DAG: [[PADDR7:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX7]]
|
||||
// CHECK-DAG: [[PSZ7:%.+]] = getelementptr inbounds [10 x i64], ptr [[PSZ]], i32 0, i32 [[IDX7]]
|
||||
// CHECK-DAG: [[BPADDR8:%.+]] = getelementptr inbounds [10 x ptr], ptr [[BP]], i32 0, i32 [[IDX8:8]]
|
||||
// CHECK-DAG: [[PADDR8:%.+]] = getelementptr inbounds [10 x ptr], ptr [[P]], i32 0, i32 [[IDX8]]
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX0:0]]
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX0]]
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX1:1]]
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX1]]
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX2:2]]
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX2]]
|
||||
// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX3:3]]
|
||||
// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX3]]
|
||||
// CHECK-DAG: [[PSZ3:%.+]] = getelementptr inbounds [9 x i64], ptr [[PSZ]], i32 0, i32 [[IDX3]]
|
||||
// CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX4:4]]
|
||||
// CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX4]]
|
||||
// CHECK-DAG: [[BPADDR5:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX5:5]]
|
||||
// CHECK-DAG: [[PADDR5:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX5]]
|
||||
// CHECK-DAG: [[BPADDR6:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX6:6]]
|
||||
// CHECK-DAG: [[PADDR6:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX6]]
|
||||
// CHECK-DAG: [[BPADDR7:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX7:7]]
|
||||
// CHECK-DAG: [[PADDR7:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX7]]
|
||||
// CHECK-DAG: [[PSZ7:%.+]] = getelementptr inbounds [9 x i64], ptr [[PSZ]], i32 0, i32 [[IDX7]]
|
||||
// CHECK-DAG: [[BPADDR8:%.+]] = getelementptr inbounds [9 x ptr], ptr [[BP]], i32 0, i32 [[IDX8:8]]
|
||||
// CHECK-DAG: [[PADDR8:%.+]] = getelementptr inbounds [9 x ptr], ptr [[P]], i32 0, i32 [[IDX8]]
|
||||
|
||||
// The names below are not necessarily consistent with the names used for the
|
||||
// addresses above as some are repeated.
|
||||
@ -333,12 +333,12 @@ int foo(int n) {
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
// CHECK-NEXT: br label %[[IFEND:.+]]
|
||||
// CHECK: [[IFELSE]]
|
||||
// CHECK: call void [[HVT4]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT4]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[IFEND]]
|
||||
|
||||
// CHECK: [[IFEND]]
|
||||
@ -359,9 +359,9 @@ int foo(int n) {
|
||||
// Check that the offloading functions are emitted and that the arguments are
|
||||
// correct and loaded correctly for the target regions in foo().
|
||||
|
||||
// CHECK: define internal void [[HVT0]](ptr {{[^)]*}})
|
||||
// CHECK: define internal void [[HVT0]]()
|
||||
|
||||
// CHECK: define internal void [[HVT0_:@.+]](ptr noundef {{%[^,]+}}, i[[SZ]] noundef {{%[^,]+}}, ptr {{[^)]*}})
|
||||
// CHECK: define internal void [[HVT0_:@.+]](ptr noundef {{%[^,]+}}, i[[SZ]] noundef {{%[^,]+}})
|
||||
// CHECK: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, ptr noalias noundef %1)
|
||||
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:%.+]], i32 {{.+}}, i32 {{.+}}, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
|
||||
@ -387,18 +387,18 @@ int foo(int n) {
|
||||
// CHECK-32: store i32 [[GLOBAL]], ptr [[GLOBALCAST:%.+]], align
|
||||
// CHECK-64: store i32 [[GLOBAL]], ptr [[GLOBALCAST:%.+]], align
|
||||
// CHECK: [[GLOBAL:%.+]] = load i[[SZ]], ptr [[GLOBALCAST]], align
|
||||
// CHECK: call void [[HVT0_]](ptr [[PLOCAL]], i[[SZ]] [[GLOBAL]], ptr null)
|
||||
// CHECK: call void [[HVT0_]](ptr [[PLOCAL]], i[[SZ]] [[GLOBAL]])
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
|
||||
// CHECK: define internal void [[HVT1]](i[[SZ]] noundef %{{.+}}, ptr {{[^)]*}})
|
||||
// CHECK: define internal void [[HVT1]](i[[SZ]] noundef %{{.+}})
|
||||
// Create stack storage and store argument in there.
|
||||
// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align
|
||||
// CHECK: store i[[SZ]] %{{.+}}, ptr [[AA_ADDR]], align
|
||||
// CHECK-64: load i32, ptr [[AA_ADDR]], align
|
||||
// CHECK-32: load i32, ptr [[AA_ADDR]], align
|
||||
|
||||
// CHECK: define internal void [[HVT2]](i[[SZ]] noundef %{{.+}}, ptr {{[^)]*}})
|
||||
// CHECK: define internal void [[HVT2]](i[[SZ]] noundef %{{.+}})
|
||||
// Create stack storage and store argument in there.
|
||||
// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align
|
||||
// CHECK: store i[[SZ]] %{{.+}}, ptr [[AA_ADDR]], align
|
||||
@ -551,20 +551,20 @@ int bar(int n){
|
||||
// CHECK-DAG: store ptr [[PR:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[SARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
|
||||
// CHECK-DAG: store ptr [[SZ7:%.+]], ptr [[SARG]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [6 x ptr], ptr [[BP:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [6 x ptr], ptr [[P:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZ7]] = getelementptr inbounds [6 x i64], ptr [[PSZ:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BP]], i32 0, i32 [[IDX0:0]]
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [6 x ptr], ptr [[P]], i32 0, i32 [[IDX0]]
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BP]], i32 0, i32 [[IDX1:1]]
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [6 x ptr], ptr [[P]], i32 0, i32 [[IDX1]]
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BP]], i32 0, i32 [[IDX2:2]]
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [6 x ptr], ptr [[P]], i32 0, i32 [[IDX2]]
|
||||
// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BP]], i32 0, i32 [[IDX3:3]]
|
||||
// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [6 x ptr], ptr [[P]], i32 0, i32 [[IDX3]]
|
||||
// CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [6 x ptr], ptr [[BP]], i32 0, i32 [[IDX4:4]]
|
||||
// CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [6 x ptr], ptr [[P]], i32 0, i32 [[IDX4]]
|
||||
// CHECK-DAG: [[PSZ4:%.+]] = getelementptr inbounds [6 x i64], ptr [[PSZ:%.+]], i32 0, i32 [[IDX4]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [5 x ptr], ptr [[BP:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [5 x ptr], ptr [[P:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[SZ7]] = getelementptr inbounds [5 x i64], ptr [[PSZ:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 [[IDX0:0]]
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 [[IDX0]]
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 [[IDX1:1]]
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 [[IDX1]]
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 [[IDX2:2]]
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 [[IDX2]]
|
||||
// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 [[IDX3:3]]
|
||||
// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 [[IDX3]]
|
||||
// CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 [[IDX4:4]]
|
||||
// CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 [[IDX4]]
|
||||
// CHECK-DAG: [[PSZ4:%.+]] = getelementptr inbounds [5 x i64], ptr [[PSZ:%.+]], i32 0, i32 [[IDX4]]
|
||||
|
||||
// The names below are not necessarily consistent with the names used for the
|
||||
// addresses above as some are repeated.
|
||||
@ -587,12 +587,12 @@ int bar(int n){
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
// CHECK-NEXT: br label %[[IFEND:.+]]
|
||||
// CHECK: [[IFELSE]]
|
||||
// CHECK: call void [[HVT7]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT7]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[IFEND]]
|
||||
|
||||
// CHECK: [[IFEND]]
|
||||
@ -608,53 +608,6 @@ int bar(int n){
|
||||
// CHECK-DAG: store ptr [[BPR:%.+]], ptr [[BPARG]]
|
||||
// CHECK-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[PR:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [5 x ptr], ptr [[BP:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [5 x ptr], ptr [[P:%.+]], i32 0, i32 0
|
||||
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL0:%[^,]+]], ptr [[BPADDR0]]
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL0]], ptr [[PADDR0]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 1
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 1
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL1:%[^,]+]], ptr [[BPADDR1]]
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL1]], ptr [[PADDR1]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 2
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 2
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL2:%[^,]+]], ptr [[BPADDR2]]
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL2]], ptr [[PADDR2]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [5 x ptr], ptr [[BP]], i32 0, i32 3
|
||||
// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [5 x ptr], ptr [[P]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[VAL3:%[^,]+]], ptr [[BPADDR3]]
|
||||
// CHECK-DAG: store ptr [[VAL3]], ptr [[PADDR3]]
|
||||
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
// CHECK-NEXT: br label %[[IFEND:.+]]
|
||||
// CHECK: [[IFELSE]]
|
||||
// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK-NEXT: br label %[[IFEND]]
|
||||
|
||||
// CHECK: [[IFEND]]
|
||||
|
||||
//
|
||||
// CHECK: define {{.*}}[[FTEMPLATE]]
|
||||
//
|
||||
// CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40
|
||||
// CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]]
|
||||
// CHECK: [[IFTHEN]]
|
||||
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 {{.+}}, i32 {{.+}}, i32 {{.+}}, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
|
||||
// CHECK-DAG: store ptr [[BPR:%.+]], ptr [[BPARG]]
|
||||
// CHECK-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[PR:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [4 x ptr], ptr [[BP:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [4 x ptr], ptr [[P:%.+]], i32 0, i32 0
|
||||
|
||||
@ -670,18 +623,65 @@ int bar(int n){
|
||||
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BP]], i32 0, i32 2
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [4 x ptr], ptr [[P]], i32 0, i32 2
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL2:%[^,]+]], ptr [[BPADDR2]]
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL2]], ptr [[PADDR2]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [4 x ptr], ptr [[BP]], i32 0, i32 3
|
||||
// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [4 x ptr], ptr [[P]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[VAL3:%[^,]+]], ptr [[BPADDR3]]
|
||||
// CHECK-DAG: store ptr [[VAL3]], ptr [[PADDR3]]
|
||||
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
// CHECK-NEXT: br label %[[IFEND:.+]]
|
||||
// CHECK: [[IFELSE]]
|
||||
// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[IFEND]]
|
||||
|
||||
// CHECK: [[IFEND]]
|
||||
|
||||
//
|
||||
// CHECK: define {{.*}}[[FTEMPLATE]]
|
||||
//
|
||||
// CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40
|
||||
// CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]]
|
||||
// CHECK: [[IFTHEN]]
|
||||
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 {{.+}}, i32 {{.+}}, i32 {{.+}}, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// CHECK-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
|
||||
// CHECK-DAG: store ptr [[BPR:%.+]], ptr [[BPARG]]
|
||||
// CHECK-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
|
||||
// CHECK-DAG: store ptr [[PR:%.+]], ptr [[PARG]]
|
||||
// CHECK-DAG: [[BPR]] = getelementptr inbounds [3 x ptr], ptr [[BP:%.+]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PR]] = getelementptr inbounds [3 x ptr], ptr [[P:%.+]], i32 0, i32 0
|
||||
|
||||
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL0:%[^,]+]], ptr [[BPADDR0]]
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL0]], ptr [[PADDR0]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BP]], i32 0, i32 1
|
||||
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x ptr], ptr [[P]], i32 0, i32 1
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL1:%[^,]+]], ptr [[BPADDR1]]
|
||||
// CHECK-DAG: store i[[SZ]] [[VAL1]], ptr [[PADDR1]]
|
||||
|
||||
// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[BP]], i32 0, i32 2
|
||||
// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [3 x ptr], ptr [[P]], i32 0, i32 2
|
||||
// CHECK-DAG: store ptr [[VAL2:%[^,]+]], ptr [[BPADDR2]]
|
||||
// CHECK-DAG: store ptr [[VAL2]], ptr [[PADDR2]]
|
||||
|
||||
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
|
||||
// CHECK: [[FAIL]]
|
||||
// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[END]]
|
||||
// CHECK: [[END]]
|
||||
// CHECK-NEXT: br label %[[IFEND:.+]]
|
||||
// CHECK: [[IFELSE]]
|
||||
// CHECK: call void [[HVT5]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, ptr null)
|
||||
// CHECK: call void [[HVT5]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
|
||||
// CHECK-NEXT: br label %[[IFEND]]
|
||||
|
||||
// CHECK: [[IFEND]]
|
||||
@ -691,26 +691,26 @@ int bar(int n){
|
||||
// OMP45: define {{.*}}@{{.*}}zee{{.*}}
|
||||
|
||||
// OMP45: [[LOCAL_THIS:%.+]] = alloca ptr
|
||||
// OMP45: [[BP:%.+]] = alloca [2 x ptr]
|
||||
// OMP45: [[P:%.+]] = alloca [2 x ptr]
|
||||
// OMP45: [[BP:%.+]] = alloca [1 x ptr]
|
||||
// OMP45: [[P:%.+]] = alloca [1 x ptr]
|
||||
// OMP45: [[LOCAL_THIS1:%.+]] = load ptr, ptr [[LOCAL_THIS]]
|
||||
|
||||
// OMP45: call void @__kmpc_critical(
|
||||
// OMP45: [[ARR_IDX:%.+]] = getelementptr inbounds [[S2]], ptr [[LOCAL_THIS1]], i[[SZ]] 0
|
||||
// OMP45: [[ARR_IDX2:%.+]] = getelementptr inbounds [[S2]], ptr [[LOCAL_THIS1]], i[[SZ]] 0
|
||||
|
||||
// OMP45-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP45-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP45-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [1 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP45-DAG: [[PADDR0:%.+]] = getelementptr inbounds [1 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP45-DAG: store ptr [[ARR_IDX]], ptr [[BPADDR0]]
|
||||
// OMP45-DAG: store ptr [[ARR_IDX2]], ptr [[PADDR0]]
|
||||
|
||||
// OMP45: [[BPR:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP45: [[PR:%.+]] = getelementptr inbounds [2 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP45: [[BPR:%.+]] = getelementptr inbounds [1 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP45: [[PR:%.+]] = getelementptr inbounds [1 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP45: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 {{.+}}, i32 {{.+}}, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// OMP45-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// OMP45-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
|
||||
// OMP45: [[FAIL]]
|
||||
// OMP45: call void [[HVT0:@.+]](ptr [[LOCAL_THIS1]], ptr null)
|
||||
// OMP45: call void [[HVT0:@.+]](ptr [[LOCAL_THIS1]])
|
||||
// OMP45-NEXT: br label %[[END]]
|
||||
// OMP45: [[END]]
|
||||
// OMP45: call void @__kmpc_end_critical(
|
||||
@ -782,24 +782,24 @@ int bar(int n){
|
||||
// OMP50: define {{.*}}@{{.*}}zee{{.*}}
|
||||
|
||||
// OMP50: [[LOCAL_THIS:%.+]] = alloca ptr
|
||||
// OMP50: [[BP:%.+]] = alloca [2 x ptr]
|
||||
// OMP50: [[P:%.+]] = alloca [2 x ptr]
|
||||
// OMP50: [[BP:%.+]] = alloca [1 x ptr]
|
||||
// OMP50: [[P:%.+]] = alloca [1 x ptr]
|
||||
// OMP50: [[LOCAL_THIS1:%.+]] = load ptr, ptr [[LOCAL_THIS]]
|
||||
// OMP50: [[ARR_IDX:%.+]] = getelementptr inbounds [[S2]], ptr [[LOCAL_THIS1]], i[[SZ]] 0
|
||||
// OMP50: [[ARR_IDX2:%.+]] = getelementptr inbounds [[S2]], ptr [[LOCAL_THIS1]], i[[SZ]] 0
|
||||
|
||||
// OMP50-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP50-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP50-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [1 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP50-DAG: [[PADDR0:%.+]] = getelementptr inbounds [1 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP50-DAG: store ptr [[ARR_IDX]], ptr [[BPADDR0]]
|
||||
// OMP50-DAG: store ptr [[ARR_IDX2]], ptr [[PADDR0]]
|
||||
|
||||
// OMP50: [[BPR:%.+]] = getelementptr inbounds [2 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP50: [[PR:%.+]] = getelementptr inbounds [2 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP50: [[BPR:%.+]] = getelementptr inbounds [1 x ptr], ptr [[BP]], i32 0, i32 0
|
||||
// OMP50: [[PR:%.+]] = getelementptr inbounds [1 x ptr], ptr [[P]], i32 0, i32 0
|
||||
// OMP50: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 -1, i32 {{.+}}, i32 {{.+}}, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
|
||||
// OMP50-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
|
||||
// OMP50-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
|
||||
// OMP50: [[FAIL]]
|
||||
// OMP50: call void [[HVT0:@.+]](ptr [[LOCAL_THIS1]], ptr null)
|
||||
// OMP50: call void [[HVT0:@.+]](ptr [[LOCAL_THIS1]])
|
||||
// OMP50-NEXT: br label %[[END]]
|
||||
// OMP50: [[END]]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -79,41 +79,41 @@
|
||||
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// TCHECK-NOT: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
// CHECK-DAG: {{@.+}} = weak{{.*}} constant i8 0
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 4, i64 0]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [2 x i64] [i64 800, i64 288]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 4]
|
||||
// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i64] [i64 800]
|
||||
|
||||
// CHECK-NTARGET-NOT: weak constant i8 0
|
||||
// CHECK-NTARGET-NOT: private unnamed_addr constant [1 x i
|
||||
|
||||
@ -25,8 +25,8 @@
|
||||
#ifndef HEADER
|
||||
#define HEADER
|
||||
|
||||
// CHECK-DAG: [[SIZES:@.+]] = private unnamed_addr constant [2 x i64] [i64 {{8|4}}, i64 0]
|
||||
// CHECK-DAG: [[MAPTYPES:@.+]] = private unnamed_addr constant [2 x i64] [i64 3, i64 288]
|
||||
// CHECK-DAG: [[SIZES:@.+]] = private unnamed_addr constant [1 x i64] [i64 {{8|4}}]
|
||||
// CHECK-DAG: [[MAPTYPES:@.+]] = private unnamed_addr constant [1 x i64] [i64 3]
|
||||
struct S {
|
||||
double *p;
|
||||
};
|
||||
|
||||
@ -20,8 +20,8 @@
|
||||
|
||||
// CK1: [[MYSIZE00:@.+]] = {{.*}}constant [2 x i64] [i64 4, i64 {{8|4}}]
|
||||
// CK1: [[MTYPE00:@.+]] = {{.*}}constant [2 x i64] [i64 67, i64 16384]
|
||||
// CK1: [[MTYPE01:@.+]] = {{.*}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK1: [[MTYPE02:@.+]] = {{.*}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK1: [[MTYPE01:@.+]] = {{.*}}constant [1 x i64] [i64 288]
|
||||
// CK1: [[MTYPE02:@.+]] = {{.*}}constant [1 x i64] [i64 288]
|
||||
|
||||
void add_one(float *b, int dm)
|
||||
{
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -24,9 +24,9 @@
|
||||
|
||||
// CK1-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double_complex{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK1-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK1-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 544
|
||||
// CK1-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 544, i64 288]
|
||||
// CK1-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 544]
|
||||
|
||||
// CK1-LABEL: implicit_maps_double_complex{{.*}}(
|
||||
void implicit_maps_double_complex (int a){
|
||||
@ -44,7 +44,7 @@ void implicit_maps_double_complex (int a){
|
||||
// CK1-DAG: store ptr [[PTR:%[^,]+]], ptr [[BP1]]
|
||||
// CK1-DAG: store ptr [[PTR]], ptr [[P1]]
|
||||
|
||||
// CK1: call void [[KERNEL:@.+]](ptr [[PTR]], ptr null)
|
||||
// CK1: call void [[KERNEL:@.+]](ptr [[PTR]])
|
||||
#ifdef OMP6
|
||||
// 'storage' is an alias for 'alloc' in OpenMP 6.0
|
||||
#pragma omp target defaultmap(storage : scalar)
|
||||
@ -56,7 +56,7 @@ void implicit_maps_double_complex (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK1: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK1: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]])
|
||||
// CK1: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK1: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK1: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -81,9 +81,9 @@ void implicit_maps_double_complex (int a){
|
||||
|
||||
// CK2-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double_complex{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK2-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK2-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 545
|
||||
// CK2-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 545, i64 288]
|
||||
// CK2-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 545]
|
||||
|
||||
// CK2-LABEL: implicit_maps_double_complex{{.*}}(
|
||||
void implicit_maps_double_complex (int a){
|
||||
@ -101,7 +101,7 @@ void implicit_maps_double_complex (int a){
|
||||
// CK2-DAG: store ptr [[PTR:%[^,]+]], ptr [[BP1]]
|
||||
// CK2-DAG: store ptr [[PTR]], ptr [[P1]]
|
||||
|
||||
// CK2: call void [[KERNEL:@.+]](ptr [[PTR]], ptr null)
|
||||
// CK2: call void [[KERNEL:@.+]](ptr [[PTR]])
|
||||
#pragma omp target defaultmap(to \
|
||||
: scalar)
|
||||
{
|
||||
@ -109,7 +109,7 @@ void implicit_maps_double_complex (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK2: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK2: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]])
|
||||
// CK2: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK2: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK2: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -134,9 +134,9 @@ void implicit_maps_double_complex (int a){
|
||||
|
||||
// CK3-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double_complex{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK3-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK3-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 546
|
||||
// CK3-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 546, i64 288]
|
||||
// CK3-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 546]
|
||||
|
||||
// CK3-LABEL: implicit_maps_double_complex{{.*}}(
|
||||
void implicit_maps_double_complex (int a){
|
||||
@ -154,7 +154,7 @@ void implicit_maps_double_complex (int a){
|
||||
// CK3-DAG: store ptr [[PTR:%[^,]+]], ptr [[BP1]]
|
||||
// CK3-DAG: store ptr [[PTR]], ptr [[P1]]
|
||||
|
||||
// CK3: call void [[KERNEL:@.+]](ptr [[PTR]], ptr null)
|
||||
// CK3: call void [[KERNEL:@.+]](ptr [[PTR]])
|
||||
#pragma omp target defaultmap(from \
|
||||
: scalar)
|
||||
{
|
||||
@ -162,7 +162,7 @@ void implicit_maps_double_complex (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK3: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK3: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]])
|
||||
// CK3: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK3: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK3: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -190,11 +190,11 @@ void implicit_maps_double_complex (int a){
|
||||
|
||||
// CK4-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK4-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 8, i64 0]
|
||||
// CK4-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// Map types: OMP_MAP_PRIVATE_VAL | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 800
|
||||
// CK4-64-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 800, i64 288]
|
||||
// CK4-64-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 800]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_PRIVATE | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 673
|
||||
// CK4-32-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 673, i64 288]
|
||||
// CK4-32-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 673]
|
||||
|
||||
// CK4-LABEL: implicit_maps_double{{.*}}(
|
||||
void implicit_maps_double (int a){
|
||||
@ -218,8 +218,8 @@ void implicit_maps_double (int a){
|
||||
// CK4-32-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK4-32-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK4-64: call void [[KERNEL:@.+]](i[[sz]] [[VAL]], ptr null)
|
||||
// CK4-32: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK4-64: call void [[KERNEL:@.+]](i[[sz]] [[VAL]])
|
||||
// CK4-32: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(firstprivate \
|
||||
: scalar)
|
||||
{
|
||||
@ -227,12 +227,12 @@ void implicit_maps_double (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK4-64: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK4-64: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]])
|
||||
// CK4-64: [[ADDR:%.+]] = alloca i[[sz]],
|
||||
// CK4-64: store i[[sz]] [[ARG]], ptr [[ADDR]],
|
||||
// CK4-64: {{.+}} = load double, ptr [[ADDR]],
|
||||
|
||||
// CK4-32: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK4-32: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK4-32: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK4-32: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK4-32: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -260,9 +260,9 @@ void implicit_maps_double (int a){
|
||||
|
||||
// CK5-LABEL: @.__omp_offloading_{{.*}}implicit_maps_array{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK5-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK5-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 544
|
||||
// CK5-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 544, i64 288]
|
||||
// CK5-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 544]
|
||||
|
||||
// CK5-LABEL: implicit_maps_array{{.*}}(
|
||||
void implicit_maps_array (int a){
|
||||
@ -280,7 +280,7 @@ void implicit_maps_array (int a){
|
||||
// CK5-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK5-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK5: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK5: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(alloc \
|
||||
: aggregate)
|
||||
{
|
||||
@ -289,7 +289,7 @@ void implicit_maps_array (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK5: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK5: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK5: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK5: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK5: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -314,9 +314,9 @@ void implicit_maps_array (int a){
|
||||
|
||||
// CK6-LABEL: @.__omp_offloading_{{.*}}implicit_maps_array{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK6-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK6-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 545
|
||||
// CK6-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 545, i64 288]
|
||||
// CK6-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 545]
|
||||
|
||||
// CK6-LABEL: implicit_maps_array{{.*}}(
|
||||
void implicit_maps_array (int a){
|
||||
@ -334,7 +334,7 @@ void implicit_maps_array (int a){
|
||||
// CK6-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK6-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK6: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK6: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(to)
|
||||
{
|
||||
darr[0] += 1.0;
|
||||
@ -342,7 +342,7 @@ void implicit_maps_array (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK6: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK6: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK6: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK6: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK6: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -367,9 +367,9 @@ void implicit_maps_array (int a){
|
||||
|
||||
// CK7-LABEL: @.__omp_offloading_{{.*}}implicit_maps_array{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK7-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK7-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 546
|
||||
// CK7-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 546, i64 288]
|
||||
// CK7-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 546]
|
||||
|
||||
// CK7-LABEL: implicit_maps_array{{.*}}(
|
||||
void implicit_maps_array (int a){
|
||||
@ -387,7 +387,7 @@ void implicit_maps_array (int a){
|
||||
// CK7-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK7-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK7: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK7: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(from \
|
||||
: aggregate)
|
||||
{
|
||||
@ -396,7 +396,7 @@ void implicit_maps_array (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK7: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK7: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK7: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK7: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK7: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -421,9 +421,9 @@ void implicit_maps_array (int a){
|
||||
|
||||
// CK8-LABEL: @.__omp_offloading_{{.*}}implicit_maps_array{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK8-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK8-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 547
|
||||
// CK8-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 547, i64 288]
|
||||
// CK8-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 547]
|
||||
|
||||
// CK8-LABEL: implicit_maps_array{{.*}}(
|
||||
void implicit_maps_array (int a){
|
||||
@ -441,7 +441,7 @@ void implicit_maps_array (int a){
|
||||
// CK8-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK8-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK8: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK8: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(tofrom)
|
||||
{
|
||||
darr[0] += 1.0;
|
||||
@ -449,7 +449,7 @@ void implicit_maps_array (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK8: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK8: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK8: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK8: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK8: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -476,8 +476,8 @@ void implicit_maps_array (int a){
|
||||
|
||||
|
||||
// CK9-LABEL: @.__omp_offloading_{{.*}}zero_size_section_and_private_maps{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK9: [[SIZE09:@.+]] = private {{.*}}constant [2 x i64] [i64 40, i64 0]
|
||||
// CK9: [[MTYPE09:@.+]] = private {{.*}}constant [2 x i64] [i64 673, i64 288]
|
||||
// CK9: [[SIZE09:@.+]] = private {{.*}}constant [1 x i64] [i64 40]
|
||||
// CK9: [[MTYPE09:@.+]] = private {{.*}}constant [1 x i64] [i64 673]
|
||||
|
||||
|
||||
// CK9-LABEL: zero_size_section_and_private_maps{{.*}}(
|
||||
@ -498,7 +498,7 @@ void zero_size_section_and_private_maps (int ii){
|
||||
// CK9-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK9-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK9: call void [[CALL09:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK9: call void [[CALL09:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target defaultmap(firstprivate \
|
||||
: aggregate)
|
||||
{
|
||||
@ -529,9 +529,9 @@ void zero_size_section_and_private_maps (int ii){
|
||||
|
||||
// CK10-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK10: [[SIZE:@.+]] = private {{.*}}constant [2 x i64] [i64 {{8|4}}, i64 0]
|
||||
// CK10: [[SIZE:@.+]] = private {{.*}}constant [1 x i64] [i64 {{8|4}}]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 544
|
||||
// CK10: [[MTYPE:@.+]] = private {{.*}}constant [2 x i64] [i64 544, i64 288]
|
||||
// CK10: [[MTYPE:@.+]] = private {{.*}}constant [1 x i64] [i64 544]
|
||||
|
||||
// CK10-LABEL: explicit_maps_single{{.*}}(
|
||||
void explicit_maps_single (){
|
||||
@ -550,7 +550,7 @@ void explicit_maps_single (){
|
||||
// CK10-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK10-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK10: call void [[CALL:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK10: call void [[CALL:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target defaultmap(alloc \
|
||||
: pointer)
|
||||
{
|
||||
@ -580,9 +580,9 @@ void explicit_maps_single (){
|
||||
|
||||
// CK11-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK11: [[SIZE09:@.+]] = private {{.*}}constant [2 x i64] [i64 {{8|4}}, i64 0]
|
||||
// CK11: [[SIZE09:@.+]] = private {{.*}}constant [1 x i64] [i64 {{8|4}}]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 545
|
||||
// CK11: [[MTYPE09:@.+]] = private {{.*}}constant [2 x i64] [i64 545, i64 288]
|
||||
// CK11: [[MTYPE09:@.+]] = private {{.*}}constant [1 x i64] [i64 545]
|
||||
|
||||
// CK11-LABEL: explicit_maps_single{{.*}}(
|
||||
void explicit_maps_single (){
|
||||
@ -601,7 +601,7 @@ void explicit_maps_single (){
|
||||
// CK11-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK11-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK11: call void [[CALL09:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK11: call void [[CALL09:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target defaultmap(to \
|
||||
: pointer)
|
||||
{
|
||||
@ -631,9 +631,9 @@ void explicit_maps_single (){
|
||||
|
||||
// CK12-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK12: [[SIZE09:@.+]] = private {{.*}}constant [2 x i64] [i64 {{8|4}}, i64 0]
|
||||
// CK12: [[SIZE09:@.+]] = private {{.*}}constant [1 x i64] [i64 {{8|4}}]
|
||||
// Map types: OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 546
|
||||
// CK12: [[MTYPE09:@.+]] = private {{.*}}constant [2 x i64] [i64 546, i64 288]
|
||||
// CK12: [[MTYPE09:@.+]] = private {{.*}}constant [1 x i64] [i64 546]
|
||||
|
||||
// CK12-LABEL: explicit_maps_single{{.*}}(
|
||||
void explicit_maps_single (){
|
||||
@ -652,7 +652,7 @@ void explicit_maps_single (){
|
||||
// CK12-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK12-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK12: call void [[CALL09:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK12: call void [[CALL09:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target defaultmap(from \
|
||||
: pointer)
|
||||
{
|
||||
@ -682,9 +682,9 @@ void explicit_maps_single (){
|
||||
|
||||
// CK13-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK13: [[SIZE09:@.+]] = private {{.*}}constant [2 x i64] [i64 {{8|4}}, i64 0]
|
||||
// CK13: [[SIZE09:@.+]] = private {{.*}}constant [1 x i64] [i64 {{8|4}}]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 547
|
||||
// CK13: [[MTYPE09:@.+]] = private {{.*}}constant [2 x i64] [i64 547, i64 288]
|
||||
// CK13: [[MTYPE09:@.+]] = private {{.*}}constant [1 x i64] [i64 547]
|
||||
|
||||
// CK13-LABEL: explicit_maps_single{{.*}}(
|
||||
void explicit_maps_single (){
|
||||
@ -703,7 +703,7 @@ void explicit_maps_single (){
|
||||
// CK13-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK13-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK13: call void [[CALL09:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK13: call void [[CALL09:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target defaultmap(tofrom \
|
||||
: pointer)
|
||||
{
|
||||
@ -733,9 +733,9 @@ void explicit_maps_single (){
|
||||
|
||||
// CK14-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK14: [[SIZE09:@.+]] = private {{.*}}constant [2 x i64] zeroinitializer
|
||||
// CK14: [[SIZE09:@.+]] = private {{.*}}constant [1 x i64] zeroinitializer
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_LITERAL | OMP_MAP_IMPLICIT = 800
|
||||
// CK14: [[MTYPE09:@.+]] = private {{.*}}constant [2 x i64] [i64 800, i64 288]
|
||||
// CK14: [[MTYPE09:@.+]] = private {{.*}}constant [1 x i64] [i64 800]
|
||||
|
||||
// CK14-LABEL: explicit_maps_single{{.*}}(
|
||||
void explicit_maps_single (){
|
||||
@ -754,7 +754,7 @@ void explicit_maps_single (){
|
||||
// CK14-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK14-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK14: call void [[CALL09:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK14: call void [[CALL09:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target defaultmap(firstprivate \
|
||||
: pointer)
|
||||
{
|
||||
@ -783,12 +783,12 @@ void explicit_maps_single (){
|
||||
|
||||
// CK15-LABEL: @.__omp_offloading_{{.*}}implicit_maps_variable_length_array{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK15-DAG: [[SIZES:@.+]] = {{.+}}constant [4 x i64] [i64 {{4|8}}, i64 {{4|8}}, i64 0, i64 0]
|
||||
// CK15-DAG: [[SIZES:@.+]] = {{.+}}constant [3 x i64] [i64 {{4|8}}, i64 {{4|8}}, i64 0]
|
||||
// Map types:
|
||||
// - OMP_MAP_LITERAL + OMP_MAP_TARGET_PARAM + OMP_MAP_IMPLICIT = 800 (vla size)
|
||||
// - OMP_MAP_LITERAL + OMP_MAP_TARGET_PARAM + OMP_MAP_IMPLICIT = 800 (vla size)
|
||||
// - OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 544
|
||||
// CK15-DAG: [[TYPES:@.+]] = {{.+}}constant [4 x i64] [i64 800, i64 800, i64 544, i64 288]
|
||||
// CK15-DAG: [[TYPES:@.+]] = {{.+}}constant [3 x i64] [i64 800, i64 800, i64 544]
|
||||
|
||||
// CK15-LABEL: implicit_maps_variable_length_array{{.*}}(
|
||||
void implicit_maps_variable_length_array (int a){
|
||||
@ -823,7 +823,7 @@ void implicit_maps_variable_length_array (int a){
|
||||
// CK15-DAG: store i64 [[VALS2:%.+]], ptr [[S2]],
|
||||
// CK15-DAG: [[VALS2]] = {{mul nuw i64 %.+, 8|sext i32 %.+ to i64}}
|
||||
|
||||
// CK15: call void [[KERNEL:@.+]](i[[sz]] {{.+}}, i[[sz]] {{.+}}, ptr [[DECL]], ptr null)
|
||||
// CK15: call void [[KERNEL:@.+]](i[[sz]] {{.+}}, i[[sz]] {{.+}}, ptr [[DECL]])
|
||||
#pragma omp target defaultmap(alloc \
|
||||
: aggregate)
|
||||
{
|
||||
@ -831,7 +831,7 @@ void implicit_maps_variable_length_array (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK15: define internal void [[KERNEL]](i[[sz]] [[VLA0:%.+]], i[[sz]] [[VLA1:%.+]], ptr {{.*}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK15: define internal void [[KERNEL]](i[[sz]] [[VLA0:%.+]], i[[sz]] [[VLA1:%.+]], ptr {{.*}}[[ARG:%.+]])
|
||||
// CK15: [[ADDR0:%.+]] = alloca i[[sz]],
|
||||
// CK15: [[ADDR1:%.+]] = alloca i[[sz]],
|
||||
// CK15: [[ADDR2:%.+]] = alloca ptr,
|
||||
@ -862,9 +862,9 @@ void implicit_maps_variable_length_array (int a){
|
||||
|
||||
// CK16-DAG: [[ST:%.+]] = type { i32, double }
|
||||
// CK16-LABEL: @.__omp_offloading_{{.*}}implicit_maps_struct{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK16-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 {{16|12}}, i64 0]
|
||||
// CK16-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 {{16|12}}]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 544
|
||||
// CK16-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 544, i64 288]
|
||||
// CK16-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 544]
|
||||
|
||||
class SSS {
|
||||
public:
|
||||
@ -888,7 +888,7 @@ void implicit_maps_struct (int a){
|
||||
// CK16-DAG: store ptr [[DECL:%.+]], ptr [[BP1]]
|
||||
// CK16-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK16: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK16: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(alloc \
|
||||
: aggregate)
|
||||
{
|
||||
@ -897,7 +897,7 @@ void implicit_maps_struct (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK16: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK16: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK16: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK16: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK16: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -922,9 +922,9 @@ void implicit_maps_struct (int a){
|
||||
|
||||
// CK17-DAG: [[ST:%.+]] = type { i32, double }
|
||||
// CK17-LABEL: @.__omp_offloading_{{.*}}implicit_maps_struct{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK17-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 {{16|12}}, i64 0]
|
||||
// CK17-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 {{16|12}}]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 545
|
||||
// CK17-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 545, i64 288]
|
||||
// CK17-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 545]
|
||||
|
||||
class SSS {
|
||||
public:
|
||||
@ -948,7 +948,7 @@ void implicit_maps_struct (int a){
|
||||
// CK17-DAG: store ptr [[DECL:%.+]], ptr [[BP1]]
|
||||
// CK17-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK17: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK17: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(to \
|
||||
: aggregate)
|
||||
{
|
||||
@ -957,7 +957,7 @@ void implicit_maps_struct (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK17: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK17: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK17: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK17: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK17: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -982,9 +982,9 @@ void implicit_maps_struct (int a){
|
||||
|
||||
// CK18-DAG: [[ST:%.+]] = type { i32, double }
|
||||
// CK18-LABEL: @.__omp_offloading_{{.*}}implicit_maps_struct{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK18-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 {{16|12}}, i64 0]
|
||||
// CK18-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 {{16|12}}]
|
||||
// Map types: OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 546
|
||||
// CK18-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 546, i64 288]
|
||||
// CK18-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 546]
|
||||
|
||||
class SSS {
|
||||
public:
|
||||
@ -1008,7 +1008,7 @@ void implicit_maps_struct (int a){
|
||||
// CK18-DAG: store ptr [[DECL:%.+]], ptr [[BP1]]
|
||||
// CK18-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK18: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK18: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(from \
|
||||
: aggregate)
|
||||
{
|
||||
@ -1017,7 +1017,7 @@ void implicit_maps_struct (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK18: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK18: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK18: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK18: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK18: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -1042,9 +1042,9 @@ void implicit_maps_struct (int a){
|
||||
|
||||
// CK19-DAG: [[ST:%.+]] = type { i32, double }
|
||||
// CK19-LABEL: @.__omp_offloading_{{.*}}implicit_maps_struct{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK19-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 {{16|12}}, i64 0]
|
||||
// CK19-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 {{16|12}}]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_FROM | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 547
|
||||
// CK19-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 547, i64 288]
|
||||
// CK19-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 547]
|
||||
|
||||
class SSS {
|
||||
public:
|
||||
@ -1068,7 +1068,7 @@ void implicit_maps_struct (int a){
|
||||
// CK19-DAG: store ptr [[DECL:%.+]], ptr [[BP1]]
|
||||
// CK19-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK19: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK19: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(tofrom \
|
||||
: aggregate)
|
||||
{
|
||||
@ -1077,7 +1077,7 @@ void implicit_maps_struct (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK19: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK19: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK19: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK19: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK19: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -1105,11 +1105,11 @@ void implicit_maps_struct (int a){
|
||||
|
||||
// CK20-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK20-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 8, i64 0]
|
||||
// CK20-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 8]
|
||||
// Map types: OMP_MAP_LITERAL | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 800
|
||||
// CK20-64-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 800, i64 288]
|
||||
// CK20-64-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 800]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_PRIVATE | OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 673
|
||||
// CK20-32-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 673, i64 288]
|
||||
// CK20-32-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 673]
|
||||
|
||||
// CK20-LABEL: implicit_maps_double{{.*}}(
|
||||
void implicit_maps_double (int a){
|
||||
@ -1133,8 +1133,8 @@ void implicit_maps_double (int a){
|
||||
// CK20-32-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK20-32-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK20-64: call void [[KERNEL:@.+]](i[[sz]] [[VAL]], ptr null)
|
||||
// CK20-32: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK20-64: call void [[KERNEL:@.+]](i[[sz]] [[VAL]])
|
||||
// CK20-32: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(default \
|
||||
: scalar)
|
||||
{
|
||||
@ -1142,12 +1142,12 @@ void implicit_maps_double (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK20-64: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK20-64: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]])
|
||||
// CK20-64: [[ADDR:%.+]] = alloca i[[sz]],
|
||||
// CK20-64: store i[[sz]] [[ARG]], ptr [[ADDR]],
|
||||
// CK20-64: {{.+}} = load double, ptr [[ADDR]],
|
||||
|
||||
// CK20-32: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK20-32: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK20-32: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK20-32: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK20-32: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -1173,9 +1173,9 @@ void implicit_maps_double (int a){
|
||||
|
||||
// CK21-DAG: [[ST:%.+]] = type { i32, double }
|
||||
// CK21-LABEL: @.__omp_offloading_{{.*}}implicit_maps_struct{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK21-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 {{16|12}}, i64 0]
|
||||
// CK21-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 {{16|12}}]
|
||||
// Map types: OMP_MAP_TO + OMP_MAP_FROM + OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 547
|
||||
// CK21-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 547, i64 288]
|
||||
// CK21-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 547]
|
||||
|
||||
class SSS {
|
||||
public:
|
||||
@ -1199,7 +1199,7 @@ void implicit_maps_struct (int a){
|
||||
// CK21-DAG: store ptr [[DECL:%.+]], ptr [[BP1]]
|
||||
// CK21-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK21: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK21: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(default \
|
||||
: aggregate)
|
||||
{
|
||||
@ -1208,7 +1208,7 @@ void implicit_maps_struct (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK21: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK21: define internal void [[KERNEL]](ptr {{.+}}[[ARG:%.+]])
|
||||
// CK21: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK21: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK21: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -1233,9 +1233,9 @@ void implicit_maps_struct (int a){
|
||||
|
||||
// CK22-LABEL: @.__omp_offloading_{{.*}}implicit_maps_pointer{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
|
||||
// CK22-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] zeroinitializer
|
||||
// CK22-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] zeroinitializer
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT = 544
|
||||
// CK22-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 544, i64 288]
|
||||
// CK22-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 544]
|
||||
|
||||
// CK22-LABEL: implicit_maps_pointer{{.*}}(
|
||||
void implicit_maps_pointer (){
|
||||
@ -1253,7 +1253,7 @@ void implicit_maps_pointer (){
|
||||
// CK22-DAG: store ptr [[PTR:%[^,]+]], ptr [[BP1]]
|
||||
// CK22-DAG: store ptr [[PTR]], ptr [[P1]]
|
||||
|
||||
// CK22: call void [[KERNEL:@.+]](ptr [[PTR]], ptr null)
|
||||
// CK22: call void [[KERNEL:@.+]](ptr [[PTR]])
|
||||
#pragma omp target defaultmap(default \
|
||||
: pointer)
|
||||
{
|
||||
@ -1262,7 +1262,7 @@ void implicit_maps_pointer (){
|
||||
}
|
||||
}
|
||||
|
||||
// CK22: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK22: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]])
|
||||
// CK22: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK22: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK22: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
@ -1289,26 +1289,26 @@ void implicit_maps_pointer (){
|
||||
double *g;
|
||||
|
||||
// CK23: @g ={{.*}} global ptr
|
||||
// CK23: [[SIZES00:@.+]] = {{.+}}constant [2 x i[[sz:64|32]]] [i{{64|32}} {{8|4}}, i[[sz:64|32]] 0]
|
||||
// CK23: [[TYPES00:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK23: [[SIZES00:@.+]] = {{.+}}constant [1 x i[[sz:64|32]]] [i{{64|32}} {{8|4}}]
|
||||
// CK23: [[TYPES00:@.+]] = {{.+}}constant [1 x i64] [i64 288]
|
||||
|
||||
// CK23: [[SIZES01:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] 0]
|
||||
// CK23: [[TYPES01:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK23: [[SIZES01:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
|
||||
// CK23: [[TYPES01:@.+]] = {{.+}}constant [1 x i64] [i64 288]
|
||||
|
||||
// CK23: [[SIZES02:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] 0]
|
||||
// CK23: [[TYPES02:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK23: [[SIZES02:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
|
||||
// CK23: [[TYPES02:@.+]] = {{.+}}constant [1 x i64] [i64 288]
|
||||
|
||||
// CK23: [[SIZES03:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] 0]
|
||||
// CK23: [[TYPES03:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK23: [[SIZES03:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
|
||||
// CK23: [[TYPES03:@.+]] = {{.+}}constant [1 x i64] [i64 288]
|
||||
|
||||
// CK23: [[SIZES04:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] 0]
|
||||
// CK23: [[TYPES04:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK23: [[SIZES04:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
|
||||
// CK23: [[TYPES04:@.+]] = {{.+}}constant [1 x i64] [i64 288]
|
||||
|
||||
// CK23: [[SIZES05:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] 0]
|
||||
// CK23: [[TYPES05:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
// CK23: [[SIZES05:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
|
||||
// CK23: [[TYPES05:@.+]] = {{.+}}constant [1 x i64] [i64 288]
|
||||
|
||||
// CK23: [[SIZES06:@.+]] = {{.+}}constant [3 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] {{8|4}}, i[[sz]] 0]
|
||||
// CK23: [[TYPES06:@.+]] = {{.+}}constant [3 x i64] [i64 288, i64 288, i64 288]
|
||||
// CK23: [[SIZES06:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] {{8|4}}]
|
||||
// CK23: [[TYPES06:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
|
||||
|
||||
// CK23-LABEL: @_Z3foo{{.*}}(
|
||||
template<typename T>
|
||||
@ -1329,7 +1329,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: store ptr [[VAL]], ptr [[P1]]
|
||||
// CK23-DAG: [[VAL]] = load ptr, ptr [[ADDR:@g]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]])
|
||||
#pragma omp target is_device_ptr(g) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1349,7 +1349,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: store ptr [[VAL]], ptr [[P1]]
|
||||
// CK23-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]])
|
||||
#pragma omp target is_device_ptr(l) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1369,7 +1369,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: store ptr [[VAL]], ptr [[P1]]
|
||||
// CK23-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]])
|
||||
#pragma omp target is_device_ptr(t) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1390,7 +1390,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
|
||||
// CK23-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]])
|
||||
#pragma omp target is_device_ptr(lr) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1411,7 +1411,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
|
||||
// CK23-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]])
|
||||
#pragma omp target is_device_ptr(tr) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1432,7 +1432,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
|
||||
// CK23-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]])
|
||||
#pragma omp target is_device_ptr(tr, lr) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1460,7 +1460,7 @@ void foo(float *&lr, T *&tr) {
|
||||
// CK23-DAG: [[_VAL]] = load ptr, ptr [[_ADDR:%.+]],
|
||||
// CK23-DAG: [[_ADDR]] = load ptr, ptr [[_ADDR2:%.+]],
|
||||
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr [[_VAL]], ptr null)
|
||||
// CK23: call void [[KERNEL:@.+]](ptr [[VAL]], ptr [[_VAL]])
|
||||
#pragma omp target is_device_ptr(tr, lr) defaultmap(none \
|
||||
: pointer)
|
||||
{
|
||||
@ -1491,12 +1491,12 @@ void bar(float *&a, int *&b) {
|
||||
#ifdef CK24
|
||||
|
||||
// CK24-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK24: [[SIZE00:@.+]] = private {{.*}}constant [2 x i[[Z:64|32]]] [i[[Z:64|32]] 4, i[[Z:64|32]] 0]
|
||||
// CK24: [[MTYPE00:@.+]] = private {{.*}}constant [2 x i64] [i64 1059, i64 288]
|
||||
// CK24: [[SIZE00:@.+]] = private {{.*}}constant [1 x i[[Z:64|32]]] [i[[Z:64|32]] 4]
|
||||
// CK24: [[MTYPE00:@.+]] = private {{.*}}constant [1 x i64] [i64 1059]
|
||||
|
||||
// CK24-LABEL: @.__omp_offloading_{{.*}}explicit_maps_single{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0
|
||||
// CK24: [[SIZE01:@.+]] = private {{.*}}constant [2 x i[[Z:64|32]]] [i[[Z:64|32]] 4, i[[Z:64|32]] 0]
|
||||
// CK24: [[MTYPE01:@.+]] = private {{.*}}constant [2 x i64] [i64 1063, i64 288]
|
||||
// CK24: [[SIZE01:@.+]] = private {{.*}}constant [1 x i[[Z:64|32]]] [i[[Z:64|32]] 4]
|
||||
// CK24: [[MTYPE01:@.+]] = private {{.*}}constant [1 x i64] [i64 1063]
|
||||
|
||||
// CK24-LABEL: explicit_maps_single{{.*}}(
|
||||
void explicit_maps_single (int ii){
|
||||
@ -1518,7 +1518,7 @@ void explicit_maps_single (int ii){
|
||||
// CK24-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK24-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK24: call void [[CALL00:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK24: call void [[CALL00:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target map(close, tofrom \
|
||||
: a) defaultmap(none \
|
||||
: scalar)
|
||||
@ -1541,7 +1541,7 @@ void explicit_maps_single (int ii){
|
||||
// CK24-DAG: store ptr [[VAR0:%.+]], ptr [[BP0]]
|
||||
// CK24-DAG: store ptr [[VAR0]], ptr [[P0]]
|
||||
|
||||
// CK24: call void [[CALL01:@.+]](ptr {{[^,]+}}, ptr null)
|
||||
// CK24: call void [[CALL01:@.+]](ptr {{[^,]+}})
|
||||
#pragma omp target map(always close tofrom \
|
||||
: a) defaultmap(none \
|
||||
: scalar)
|
||||
@ -1605,9 +1605,9 @@ void declare_target_to()
|
||||
// SIMD-ONLY18-NOT: {{__kmpc|__tgt}}
|
||||
#ifdef CK26
|
||||
|
||||
// CK26-DAG: [[SIZES:@.+]] = {{.+}}constant [4 x i64] [i64 4, i64 4096, i64 {{.+}}, i64 0]
|
||||
// CK26-DAG: [[SIZES:@.+]] = {{.+}}constant [3 x i64] [i64 4, i64 4096, i64 {{.+}}]
|
||||
// Map types: OMP_MAP_TO | OMP_MAP_FROM | OMP_MAP_PTR_AND_OBJ | OMP_MAP_IMPLICIT = 531
|
||||
// CK26-DAG: [[TYPES:@.+]] = {{.+}}constant [4 x i64] [i64 531, i64 531, i64 531, i64 288]
|
||||
// CK26-DAG: [[TYPES:@.+]] = {{.+}}constant [3 x i64] [i64 531, i64 531, i64 531]
|
||||
|
||||
float Vector[1024];
|
||||
#pragma omp declare target link(Vector)
|
||||
|
||||
@ -21,9 +21,9 @@
|
||||
|
||||
// CK1-LABEL: @.__omp_offloading_{{.*}}implicit_present_scalar{{.*}}_l{{[0-9]+}}.region_id = weak constant i8 0
|
||||
|
||||
// CK1-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 4, i64 0]
|
||||
// CK1-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 4]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT | OMP_MAP_PRESENT = 4640
|
||||
// CK1-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 4640, i64 288]
|
||||
// CK1-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 4640]
|
||||
|
||||
// CK1-LABEL: implicit_present_scalar{{.*}}(
|
||||
void implicit_present_scalar(int a) {
|
||||
@ -66,9 +66,9 @@ void implicit_present_scalar(int a) {
|
||||
|
||||
// CK2-LABEL: @.__omp_offloading_{{.*}}implicit_present_aggregate{{.*}}_l{{[0-9]+}}.region_id = weak constant i8 0
|
||||
|
||||
// CK2-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK2-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT | OMP_MAP_PRESENT = 4640
|
||||
// CK2-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 4640, i64 288]
|
||||
// CK2-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 4640]
|
||||
|
||||
// CK2-LABEL: implicit_present_aggregate{{.*}}(
|
||||
void implicit_present_aggregate(int a) {
|
||||
@ -86,7 +86,7 @@ void implicit_present_aggregate(int a) {
|
||||
// CK2-DAG: store ptr [[DECL:%[^,]+]], ptr [[BP1]]
|
||||
// CK2-DAG: store ptr [[DECL]], ptr [[P1]]
|
||||
|
||||
// CK2: call void [[KERNEL:@.+]](ptr [[DECL]], ptr null)
|
||||
// CK2: call void [[KERNEL:@.+]](ptr [[DECL]])
|
||||
#pragma omp target defaultmap(present \
|
||||
: aggregate)
|
||||
{
|
||||
@ -117,9 +117,9 @@ void implicit_present_aggregate(int a) {
|
||||
|
||||
// CK3-LABEL: @.__omp_offloading_{{.*}}explicit_present_pointer{{.*}}_l{{[0-9]+}}.region_id = weak constant i8 0
|
||||
|
||||
// CK3: [[SIZE:@.+]] = private {{.*}}constant [2 x i64] [i64 {{8|4}}, i64 0]
|
||||
// CK3: [[SIZE:@.+]] = private {{.*}}constant [1 x i64] [i64 {{8|4}}]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT | OMP_MAP_PRESENT = 4640
|
||||
// CK3: [[MTYPE:@.+]] = private {{.*}}constant [2 x i64] [i64 4640, i64 288]
|
||||
// CK3: [[MTYPE:@.+]] = private {{.*}}constant [1 x i64] [i64 4640]
|
||||
|
||||
// CK3-LABEL: explicit_present_pointer{{.*}}(
|
||||
void explicit_present_pointer() {
|
||||
@ -165,9 +165,9 @@ void explicit_present_pointer() {
|
||||
|
||||
// CK4-LABEL: @.__omp_offloading_{{.*}}implicit_present_double_complex{{.*}}.region_id = weak constant i8 0
|
||||
|
||||
// CK4-DAG: [[SIZES:@.+]] = {{.+}}constant [2 x i64] [i64 16, i64 0]
|
||||
// CK4-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i64] [i64 16]
|
||||
// Map types: OMP_MAP_TARGET_PARAM | OMP_MAP_IMPLICIT | OMP_MAP_PRESENT = 4640
|
||||
// CK4-DAG: [[TYPES:@.+]] = {{.+}}constant [2 x i64] [i64 4640, i64 288]
|
||||
// CK4-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 4640]
|
||||
|
||||
// CK4-LABEL: implicit_present_double_complex{{.*}}(
|
||||
void implicit_present_double_complex (int a){
|
||||
@ -185,7 +185,7 @@ void implicit_present_double_complex (int a){
|
||||
// CK4-DAG: store ptr [[PTR:%[^,]+]], ptr [[BP1]]
|
||||
// CK4-DAG: store ptr [[PTR]], ptr [[P1]]
|
||||
|
||||
// CK4: call void [[KERNEL:@.+]](ptr [[PTR]], ptr null)
|
||||
// CK4: call void [[KERNEL:@.+]](ptr [[PTR]])
|
||||
#pragma omp target defaultmap(present \
|
||||
: scalar)
|
||||
{
|
||||
@ -193,7 +193,7 @@ void implicit_present_double_complex (int a){
|
||||
}
|
||||
}
|
||||
|
||||
// CK4: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]], ptr {{[^)]*}})
|
||||
// CK4: define internal void [[KERNEL]](ptr {{.*}}[[ARG:%.+]])
|
||||
// CK4: [[ADDR:%.+]] = alloca ptr,
|
||||
// CK4: store ptr [[ARG]], ptr [[ADDR]],
|
||||
// CK4: [[REF:%.+]] = load ptr, ptr [[ADDR]],
|
||||
|
||||
@ -114,9 +114,9 @@ void foo4(){
|
||||
// CK1-64-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CK1-64-NEXT: [[D:%.*]] = alloca double, align 8
|
||||
// CK1-64-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
|
||||
// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK1-64-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CK1-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
@ -125,64 +125,56 @@ void foo4(){
|
||||
// CK1-64-NEXT: [[TMP1:%.*]] = load double, ptr [[D]], align 8
|
||||
// CK1-64-NEXT: store double [[TMP1]], ptr [[D_CASTED]], align 8
|
||||
// CK1-64-NEXT: [[TMP2:%.*]] = load i64, ptr [[D_CASTED]], align 8
|
||||
// CK1-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: store i64 [[TMP2]], ptr [[TMP3]], align 8
|
||||
// CK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: store i64 [[TMP2]], ptr [[TMP4]], align 8
|
||||
// CK1-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK1-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CK1-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CK1-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP8]], align 8
|
||||
// CK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: store i32 4, ptr [[TMP11]], align 4
|
||||
// CK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK1-64-NEXT: store i32 2, ptr [[TMP12]], align 4
|
||||
// CK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK1-64-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8
|
||||
// CK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK1-64-NEXT: store ptr [[TMP10]], ptr [[TMP14]], align 8
|
||||
// CK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK1-64-NEXT: store ptr @.offload_sizes, ptr [[TMP15]], align 8
|
||||
// CK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK1-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP16]], align 8
|
||||
// CK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP18]], align 8
|
||||
// CK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK1-64-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK1-64-NEXT: store i64 0, ptr [[TMP20]], align 8
|
||||
// CK1-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP21]], align 4
|
||||
// CK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP22]], align 4
|
||||
// CK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK1-64-NEXT: store i32 0, ptr [[TMP23]], align 4
|
||||
// CK1-64-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK1-64-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
|
||||
// CK1-64-NEXT: br i1 [[TMP25]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK1-64-NEXT: store i32 3, ptr [[TMP8]], align 4
|
||||
// CK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK1-64-NEXT: store i32 1, ptr [[TMP9]], align 4
|
||||
// CK1-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK1-64-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8
|
||||
// CK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK1-64-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8
|
||||
// CK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK1-64-NEXT: store ptr @.offload_sizes, ptr [[TMP12]], align 8
|
||||
// CK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK1-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP13]], align 8
|
||||
// CK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP14]], align 8
|
||||
// CK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK1-64-NEXT: store ptr null, ptr [[TMP15]], align 8
|
||||
// CK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK1-64-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK1-64-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4
|
||||
// CK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK1-64-NEXT: store i32 0, ptr [[TMP20]], align 4
|
||||
// CK1-64-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK1-64-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
|
||||
// CK1-64-NEXT: br i1 [[TMP22]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK1-64: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24(i64 [[TMP2]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24(i64 [[TMP2]]) #[[ATTR2:[0-9]+]]
|
||||
// CK1-64-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK1-64: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK1-64-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK1-64-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24(
|
||||
// CK1-64-SAME: i64 [[D:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK1-64-SAME: i64 [[D:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK1-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK1-64-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
|
||||
// CK1-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CK1-64-NEXT: [[D1:%.*]] = alloca double, align 8
|
||||
// CK1-64-NEXT: store i64 [[D]], ptr [[D_ADDR]], align 8
|
||||
// CK1-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CK1-64-NEXT: [[TMP0:%.*]] = load double, ptr [[D1]], align 8
|
||||
// CK1-64-NEXT: [[ADD:%.*]] = fadd double [[TMP0]], 1.000000e+00
|
||||
// CK1-64-NEXT: store double [[ADD]], ptr [[D1]], align 8
|
||||
@ -194,73 +186,65 @@ void foo4(){
|
||||
// CK1-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK1-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
||||
// CK1-32-NEXT: [[D:%.*]] = alloca double, align 8
|
||||
// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK1-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK1-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK1-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK1-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
||||
// CK1-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
||||
// CK1-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double
|
||||
// CK1-32-NEXT: store double [[CONV]], ptr [[D]], align 8
|
||||
// CK1-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: store ptr [[D]], ptr [[TMP1]], align 4
|
||||
// CK1-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: store ptr [[D]], ptr [[TMP2]], align 4
|
||||
// CK1-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CK1-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CK1-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CK1-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CK1-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: store i32 4, ptr [[TMP9]], align 4
|
||||
// CK1-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK1-32-NEXT: store i32 2, ptr [[TMP10]], align 4
|
||||
// CK1-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK1-32-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 4
|
||||
// CK1-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK1-32-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4
|
||||
// CK1-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK1-32-NEXT: store ptr @.offload_sizes, ptr [[TMP13]], align 4
|
||||
// CK1-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK1-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP14]], align 4
|
||||
// CK1-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP15]], align 4
|
||||
// CK1-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP16]], align 4
|
||||
// CK1-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK1-32-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CK1-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK1-32-NEXT: store i64 0, ptr [[TMP18]], align 8
|
||||
// CK1-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP19]], align 4
|
||||
// CK1-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CK1-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK1-32-NEXT: store i32 0, ptr [[TMP21]], align 4
|
||||
// CK1-32-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK1-32-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
||||
// CK1-32-NEXT: br i1 [[TMP23]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK1-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK1-32-NEXT: store i32 3, ptr [[TMP6]], align 4
|
||||
// CK1-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK1-32-NEXT: store i32 1, ptr [[TMP7]], align 4
|
||||
// CK1-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK1-32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CK1-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK1-32-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
|
||||
// CK1-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK1-32-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
|
||||
// CK1-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK1-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
|
||||
// CK1-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CK1-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK1-32-NEXT: store ptr null, ptr [[TMP13]], align 4
|
||||
// CK1-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK1-32-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CK1-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK1-32-NEXT: store i64 0, ptr [[TMP15]], align 8
|
||||
// CK1-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
|
||||
// CK1-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CK1-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK1-32-NEXT: store i32 0, ptr [[TMP18]], align 4
|
||||
// CK1-32-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK1-32-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
|
||||
// CK1-32-NEXT: br i1 [[TMP20]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK1-32: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24(ptr [[D]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24(ptr [[D]]) #[[ATTR2:[0-9]+]]
|
||||
// CK1-32-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK1-32: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK1-32-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK1-32-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo1i_l24(
|
||||
// CK1-32-SAME: ptr nonnull align 4 dereferenceable(8) [[D:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK1-32-SAME: ptr nonnull align 4 dereferenceable(8) [[D:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK1-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK1-32-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK1-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK1-32-NEXT: [[D1:%.*]] = alloca double, align 8
|
||||
// CK1-32-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
||||
// CK1-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CK1-32-NEXT: [[TMP1:%.*]] = load double, ptr [[D1]], align 8
|
||||
// CK1-32-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], 1.000000e+00
|
||||
// CK1-32-NEXT: store double [[ADD]], ptr [[D1]], align 8
|
||||
@ -303,69 +287,61 @@ void foo4(){
|
||||
// CK2-64-SAME: ) #[[ATTR0:[0-9]+]] {
|
||||
// CK2-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK2-64-NEXT: [[PVTARR:%.*]] = alloca [10 x i32], align 4
|
||||
// CK2-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK2-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK2-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK2-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK2-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK2-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK2-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK2-64-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: store ptr [[PVTARR]], ptr [[TMP0]], align 8
|
||||
// CK2-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: store ptr [[PVTARR]], ptr [[TMP1]], align 8
|
||||
// CK2-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK2-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP2]], align 8
|
||||
// CK2-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CK2-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CK2-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CK2-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: store i32 4, ptr [[TMP8]], align 4
|
||||
// CK2-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK2-64-NEXT: store i32 2, ptr [[TMP9]], align 4
|
||||
// CK2-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK2-64-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8
|
||||
// CK2-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK2-64-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8
|
||||
// CK2-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK2-64-NEXT: store ptr @.offload_sizes, ptr [[TMP12]], align 8
|
||||
// CK2-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK2-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP13]], align 8
|
||||
// CK2-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP14]], align 8
|
||||
// CK2-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP15]], align 8
|
||||
// CK2-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK2-64-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CK2-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK2-64-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CK2-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK2-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CK2-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK2-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4
|
||||
// CK2-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK2-64-NEXT: store i32 0, ptr [[TMP20]], align 4
|
||||
// CK2-64-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK2-64-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
|
||||
// CK2-64-NEXT: br i1 [[TMP22]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK2-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK2-64-NEXT: store i32 3, ptr [[TMP5]], align 4
|
||||
// CK2-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK2-64-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CK2-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK2-64-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
|
||||
// CK2-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK2-64-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CK2-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK2-64-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
|
||||
// CK2-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK2-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
|
||||
// CK2-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP11]], align 8
|
||||
// CK2-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK2-64-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CK2-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK2-64-NEXT: store i64 0, ptr [[TMP13]], align 8
|
||||
// CK2-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK2-64-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CK2-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK2-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
|
||||
// CK2-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK2-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CK2-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK2-64-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CK2-64-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK2-64-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CK2-64-NEXT: br i1 [[TMP19]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK2-64: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK2-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50(ptr [[PVTARR]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK2-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50(ptr [[PVTARR]]) #[[ATTR2:[0-9]+]]
|
||||
// CK2-64-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK2-64: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK2-64-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK2-64-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50(
|
||||
// CK2-64-SAME: ptr nonnull align 4 dereferenceable(40) [[PVTARR:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK2-64-SAME: ptr nonnull align 4 dereferenceable(40) [[PVTARR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK2-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK2-64-NEXT: [[PVTARR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CK2-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CK2-64-NEXT: [[PVTARR1:%.*]] = alloca [10 x i32], align 4
|
||||
// CK2-64-NEXT: store ptr [[PVTARR]], ptr [[PVTARR_ADDR]], align 8
|
||||
// CK2-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVTARR_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]]
|
||||
// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVTARR_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CK2-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[PVTARR1]], i64 0, i64 5
|
||||
// CK2-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
// CK2-64-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
@ -377,69 +353,61 @@ void foo4(){
|
||||
// CK2-32-SAME: ) #[[ATTR0:[0-9]+]] {
|
||||
// CK2-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK2-32-NEXT: [[PVTARR:%.*]] = alloca [10 x i32], align 4
|
||||
// CK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK2-32-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: store ptr [[PVTARR]], ptr [[TMP0]], align 4
|
||||
// CK2-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: store ptr [[PVTARR]], ptr [[TMP1]], align 4
|
||||
// CK2-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP2]], align 4
|
||||
// CK2-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CK2-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: store i32 4, ptr [[TMP8]], align 4
|
||||
// CK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK2-32-NEXT: store i32 2, ptr [[TMP9]], align 4
|
||||
// CK2-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK2-32-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4
|
||||
// CK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK2-32-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 4
|
||||
// CK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK2-32-NEXT: store ptr @.offload_sizes, ptr [[TMP12]], align 4
|
||||
// CK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK2-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP13]], align 4
|
||||
// CK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP14]], align 4
|
||||
// CK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP15]], align 4
|
||||
// CK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK2-32-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK2-32-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP18]], align 4
|
||||
// CK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK2-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4
|
||||
// CK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK2-32-NEXT: store i32 0, ptr [[TMP20]], align 4
|
||||
// CK2-32-NEXT: [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK2-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
|
||||
// CK2-32-NEXT: br i1 [[TMP22]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK2-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK2-32-NEXT: store i32 3, ptr [[TMP5]], align 4
|
||||
// CK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK2-32-NEXT: store i32 1, ptr [[TMP6]], align 4
|
||||
// CK2-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK2-32-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
|
||||
// CK2-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK2-32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK2-32-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
|
||||
// CK2-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK2-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
|
||||
// CK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP11]], align 4
|
||||
// CK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK2-32-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK2-32-NEXT: store i64 0, ptr [[TMP13]], align 8
|
||||
// CK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK2-32-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
|
||||
// CK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK2-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
||||
// CK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK2-32-NEXT: store i32 0, ptr [[TMP17]], align 4
|
||||
// CK2-32-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK2-32-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
||||
// CK2-32-NEXT: br i1 [[TMP19]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK2-32: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50(ptr [[PVTARR]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50(ptr [[PVTARR]]) #[[ATTR2:[0-9]+]]
|
||||
// CK2-32-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK2-32: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK2-32-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK2-32-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l50(
|
||||
// CK2-32-SAME: ptr nonnull align 4 dereferenceable(40) [[PVTARR:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK2-32-SAME: ptr nonnull align 4 dereferenceable(40) [[PVTARR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK2-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK2-32-NEXT: [[PVTARR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK2-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK2-32-NEXT: [[PVTARR1:%.*]] = alloca [10 x i32], align 4
|
||||
// CK2-32-NEXT: store ptr [[PVTARR]], ptr [[PVTARR_ADDR]], align 4
|
||||
// CK2-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVTARR_ADDR]], align 4, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
|
||||
// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVTARR_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
|
||||
// CK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[PVTARR1]], i32 0, i32 5
|
||||
// CK2-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
// CK2-32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
|
||||
@ -475,69 +443,61 @@ void foo4(){
|
||||
// CK3-64-SAME: ) #[[ATTR0:[0-9]+]] {
|
||||
// CK3-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK3-64-NEXT: [[PA:%.*]] = alloca ptr, align 8
|
||||
// CK3-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK3-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK3-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK3-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK3-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK3-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK3-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK3-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PA]], align 8
|
||||
// CK3-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
|
||||
// CK3-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
|
||||
// CK3-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK3-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP3]], align 8
|
||||
// CK3-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CK3-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CK3-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CK3-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: store i32 4, ptr [[TMP9]], align 4
|
||||
// CK3-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK3-64-NEXT: store i32 2, ptr [[TMP10]], align 4
|
||||
// CK3-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK3-64-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 8
|
||||
// CK3-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK3-64-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 8
|
||||
// CK3-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK3-64-NEXT: store ptr @.offload_sizes, ptr [[TMP13]], align 8
|
||||
// CK3-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK3-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP14]], align 8
|
||||
// CK3-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP15]], align 8
|
||||
// CK3-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP16]], align 8
|
||||
// CK3-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK3-64-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CK3-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK3-64-NEXT: store i64 0, ptr [[TMP18]], align 8
|
||||
// CK3-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK3-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP19]], align 4
|
||||
// CK3-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK3-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CK3-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK3-64-NEXT: store i32 0, ptr [[TMP21]], align 4
|
||||
// CK3-64-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK3-64-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
||||
// CK3-64-NEXT: br i1 [[TMP23]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK3-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK3-64-NEXT: store i32 3, ptr [[TMP6]], align 4
|
||||
// CK3-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK3-64-NEXT: store i32 1, ptr [[TMP7]], align 4
|
||||
// CK3-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK3-64-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
|
||||
// CK3-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK3-64-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
|
||||
// CK3-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK3-64-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
|
||||
// CK3-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK3-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
|
||||
// CK3-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP12]], align 8
|
||||
// CK3-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK3-64-NEXT: store ptr null, ptr [[TMP13]], align 8
|
||||
// CK3-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK3-64-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CK3-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK3-64-NEXT: store i64 0, ptr [[TMP15]], align 8
|
||||
// CK3-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK3-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
|
||||
// CK3-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK3-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CK3-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK3-64-NEXT: store i32 0, ptr [[TMP18]], align 4
|
||||
// CK3-64-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK3-64-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
|
||||
// CK3-64-NEXT: br i1 [[TMP20]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK3-64: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK3-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75(ptr [[TMP0]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK3-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
|
||||
// CK3-64-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK3-64: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK3-64-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK3-64-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75(
|
||||
// CK3-64-SAME: ptr [[PA:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK3-64-SAME: ptr [[PA:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK3-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK3-64-NEXT: [[PA_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CK3-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CK3-64-NEXT: [[PA1:%.*]] = alloca ptr, align 8
|
||||
// CK3-64-NEXT: store ptr [[PA]], ptr [[PA_ADDR]], align 8
|
||||
// CK3-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CK3-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PA1]], align 8
|
||||
// CK3-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 50
|
||||
// CK3-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
@ -550,69 +510,61 @@ void foo4(){
|
||||
// CK3-32-SAME: ) #[[ATTR0:[0-9]+]] {
|
||||
// CK3-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK3-32-NEXT: [[PA:%.*]] = alloca ptr, align 4
|
||||
// CK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK3-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PA]], align 4
|
||||
// CK3-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
|
||||
// CK3-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
|
||||
// CK3-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP3]], align 4
|
||||
// CK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CK3-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CK3-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: store i32 4, ptr [[TMP9]], align 4
|
||||
// CK3-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK3-32-NEXT: store i32 2, ptr [[TMP10]], align 4
|
||||
// CK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK3-32-NEXT: store ptr [[TMP7]], ptr [[TMP11]], align 4
|
||||
// CK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK3-32-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4
|
||||
// CK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK3-32-NEXT: store ptr @.offload_sizes, ptr [[TMP13]], align 4
|
||||
// CK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK3-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP14]], align 4
|
||||
// CK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP15]], align 4
|
||||
// CK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP16]], align 4
|
||||
// CK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK3-32-NEXT: store i64 0, ptr [[TMP17]], align 8
|
||||
// CK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK3-32-NEXT: store i64 0, ptr [[TMP18]], align 8
|
||||
// CK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP19]], align 4
|
||||
// CK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK3-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP20]], align 4
|
||||
// CK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK3-32-NEXT: store i32 0, ptr [[TMP21]], align 4
|
||||
// CK3-32-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK3-32-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
||||
// CK3-32-NEXT: br i1 [[TMP23]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK3-32-NEXT: store i32 3, ptr [[TMP6]], align 4
|
||||
// CK3-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK3-32-NEXT: store i32 1, ptr [[TMP7]], align 4
|
||||
// CK3-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK3-32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
|
||||
// CK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK3-32-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
|
||||
// CK3-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK3-32-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
|
||||
// CK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK3-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
|
||||
// CK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP12]], align 4
|
||||
// CK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK3-32-NEXT: store ptr null, ptr [[TMP13]], align 4
|
||||
// CK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK3-32-NEXT: store i64 0, ptr [[TMP14]], align 8
|
||||
// CK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK3-32-NEXT: store i64 0, ptr [[TMP15]], align 8
|
||||
// CK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
|
||||
// CK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK3-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
|
||||
// CK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK3-32-NEXT: store i32 0, ptr [[TMP18]], align 4
|
||||
// CK3-32-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK3-32-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
|
||||
// CK3-32-NEXT: br i1 [[TMP20]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK3-32: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75(ptr [[TMP0]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
|
||||
// CK3-32-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK3-32: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK3-32-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK3-32-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l75(
|
||||
// CK3-32-SAME: ptr [[PA:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK3-32-SAME: ptr [[PA:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK3-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK3-32-NEXT: [[PA_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK3-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK3-32-NEXT: [[PA1:%.*]] = alloca ptr, align 4
|
||||
// CK3-32-NEXT: store ptr [[PA]], ptr [[PA_ADDR]], align 4
|
||||
// CK3-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CK3-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PA1]], align 4
|
||||
// CK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 50
|
||||
// CK3-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
||||
@ -652,70 +604,62 @@ void foo4(){
|
||||
// CK4-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK4-64-NEXT: [[P:%.*]] = alloca i32, align 4
|
||||
// CK4-64-NEXT: [[P_CASTED:%.*]] = alloca i64, align 8
|
||||
// CK4-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK4-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK4-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
||||
// CK4-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK4-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK4-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
|
||||
// CK4-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK4-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 4
|
||||
// CK4-64-NEXT: store i32 [[TMP0]], ptr [[P_CASTED]], align 4
|
||||
// CK4-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[P_CASTED]], align 8
|
||||
// CK4-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8
|
||||
// CK4-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8
|
||||
// CK4-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK4-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP4]], align 8
|
||||
// CK4-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP5]], align 8
|
||||
// CK4-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP6]], align 8
|
||||
// CK4-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP7]], align 8
|
||||
// CK4-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: store i32 4, ptr [[TMP10]], align 4
|
||||
// CK4-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK4-64-NEXT: store i32 2, ptr [[TMP11]], align 4
|
||||
// CK4-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK4-64-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 8
|
||||
// CK4-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK4-64-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8
|
||||
// CK4-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK4-64-NEXT: store ptr @.offload_sizes, ptr [[TMP14]], align 8
|
||||
// CK4-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK4-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP15]], align 8
|
||||
// CK4-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP16]], align 8
|
||||
// CK4-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP17]], align 8
|
||||
// CK4-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK4-64-NEXT: store i64 0, ptr [[TMP18]], align 8
|
||||
// CK4-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK4-64-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CK4-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK4-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 4
|
||||
// CK4-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK4-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4
|
||||
// CK4-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK4-64-NEXT: store i32 0, ptr [[TMP22]], align 4
|
||||
// CK4-64-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK4-64-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
|
||||
// CK4-64-NEXT: br i1 [[TMP24]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK4-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK4-64-NEXT: store i32 3, ptr [[TMP7]], align 4
|
||||
// CK4-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK4-64-NEXT: store i32 1, ptr [[TMP8]], align 4
|
||||
// CK4-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK4-64-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
|
||||
// CK4-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK4-64-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8
|
||||
// CK4-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK4-64-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8
|
||||
// CK4-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK4-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8
|
||||
// CK4-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP13]], align 8
|
||||
// CK4-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK4-64-NEXT: store ptr null, ptr [[TMP14]], align 8
|
||||
// CK4-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK4-64-NEXT: store i64 0, ptr [[TMP15]], align 8
|
||||
// CK4-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK4-64-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CK4-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK4-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP17]], align 4
|
||||
// CK4-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK4-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
|
||||
// CK4-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK4-64-NEXT: store i32 0, ptr [[TMP19]], align 4
|
||||
// CK4-64-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK4-64-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
||||
// CK4-64-NEXT: br i1 [[TMP21]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK4-64: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK4-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103(i64 [[TMP1]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK4-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
||||
// CK4-64-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK4-64: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK4-64-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK4-64-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103(
|
||||
// CK4-64-SAME: i64 [[P:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK4-64-SAME: i64 [[P:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK4-64-NEXT: [[ENTRY:.*:]]
|
||||
// CK4-64-NEXT: [[P_ADDR:%.*]] = alloca i64, align 8
|
||||
// CK4-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
|
||||
// CK4-64-NEXT: store i64 [[P]], ptr [[P_ADDR]], align 8
|
||||
// CK4-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
|
||||
// CK4-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[P_ADDR]], align 4
|
||||
// CK4-64-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1
|
||||
// CK4-64-NEXT: store i32 [[INC]], ptr [[P_ADDR]], align 4
|
||||
@ -727,70 +671,62 @@ void foo4(){
|
||||
// CK4-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK4-32-NEXT: [[P:%.*]] = alloca i32, align 4
|
||||
// CK4-32-NEXT: [[P_CASTED:%.*]] = alloca i32, align 4
|
||||
// CK4-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK4-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK4-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4
|
||||
// CK4-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK4-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK4-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
|
||||
// CK4-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
||||
// CK4-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 4
|
||||
// CK4-32-NEXT: store i32 [[TMP0]], ptr [[P_CASTED]], align 4
|
||||
// CK4-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[P_CASTED]], align 4
|
||||
// CK4-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4
|
||||
// CK4-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4
|
||||
// CK4-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP4]], align 4
|
||||
// CK4-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP5]], align 4
|
||||
// CK4-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP6]], align 4
|
||||
// CK4-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP7]], align 4
|
||||
// CK4-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: store i32 4, ptr [[TMP10]], align 4
|
||||
// CK4-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK4-32-NEXT: store i32 2, ptr [[TMP11]], align 4
|
||||
// CK4-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK4-32-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4
|
||||
// CK4-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK4-32-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 4
|
||||
// CK4-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK4-32-NEXT: store ptr @.offload_sizes, ptr [[TMP14]], align 4
|
||||
// CK4-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK4-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP15]], align 4
|
||||
// CK4-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP16]], align 4
|
||||
// CK4-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP17]], align 4
|
||||
// CK4-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK4-32-NEXT: store i64 0, ptr [[TMP18]], align 8
|
||||
// CK4-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK4-32-NEXT: store i64 0, ptr [[TMP19]], align 8
|
||||
// CK4-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK4-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 4
|
||||
// CK4-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK4-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4
|
||||
// CK4-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK4-32-NEXT: store i32 0, ptr [[TMP22]], align 4
|
||||
// CK4-32-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK4-32-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
|
||||
// CK4-32-NEXT: br i1 [[TMP24]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK4-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
||||
// CK4-32-NEXT: store i32 3, ptr [[TMP7]], align 4
|
||||
// CK4-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
||||
// CK4-32-NEXT: store i32 1, ptr [[TMP8]], align 4
|
||||
// CK4-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
||||
// CK4-32-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
|
||||
// CK4-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
||||
// CK4-32-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4
|
||||
// CK4-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
||||
// CK4-32-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4
|
||||
// CK4-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
||||
// CK4-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4
|
||||
// CK4-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP13]], align 4
|
||||
// CK4-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
||||
// CK4-32-NEXT: store ptr null, ptr [[TMP14]], align 4
|
||||
// CK4-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
||||
// CK4-32-NEXT: store i64 0, ptr [[TMP15]], align 8
|
||||
// CK4-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
||||
// CK4-32-NEXT: store i64 0, ptr [[TMP16]], align 8
|
||||
// CK4-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
||||
// CK4-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP17]], align 4
|
||||
// CK4-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
||||
// CK4-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
|
||||
// CK4-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
||||
// CK4-32-NEXT: store i32 0, ptr [[TMP19]], align 4
|
||||
// CK4-32-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103.region_id, ptr [[KERNEL_ARGS]])
|
||||
// CK4-32-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
||||
// CK4-32-NEXT: br i1 [[TMP21]], label %[[OMP_OFFLOAD_FAILED:.*]], label %[[OMP_OFFLOAD_CONT:.*]]
|
||||
// CK4-32: [[OMP_OFFLOAD_FAILED]]:
|
||||
// CK4-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103(i32 [[TMP1]], ptr null) #[[ATTR2:[0-9]+]]
|
||||
// CK4-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
|
||||
// CK4-32-NEXT: br label %[[OMP_OFFLOAD_CONT]]
|
||||
// CK4-32: [[OMP_OFFLOAD_CONT]]:
|
||||
// CK4-32-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CK4-32-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l103(
|
||||
// CK4-32-SAME: i32 [[P:%.*]], ptr noalias [[DYN_PTR:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK4-32-SAME: i32 [[P:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
// CK4-32-NEXT: [[ENTRY:.*:]]
|
||||
// CK4-32-NEXT: [[P_ADDR:%.*]] = alloca i32, align 4
|
||||
// CK4-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
|
||||
// CK4-32-NEXT: store i32 [[P]], ptr [[P_ADDR]], align 4
|
||||
// CK4-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
|
||||
// CK4-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[P_ADDR]], align 4
|
||||
// CK4-32-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1
|
||||
// CK4-32-NEXT: store i32 [[INC]], ptr [[P_ADDR]], align 4
|
||||
@ -817,12 +753,12 @@ void foo4(){
|
||||
// SIMD-ONLY4-32-NEXT: ret void
|
||||
//
|
||||
//.
|
||||
// CK1-32: [[META5]] = !{}
|
||||
// CK1-32: [[META6]] = !{i64 4}
|
||||
// CK1-32: [[META6]] = !{}
|
||||
// CK1-32: [[META7]] = !{i64 4}
|
||||
//.
|
||||
// CK2-64: [[META4]] = !{}
|
||||
// CK2-64: [[META5]] = !{i64 4}
|
||||
// CK2-64: [[META5]] = !{}
|
||||
// CK2-64: [[META6]] = !{i64 4}
|
||||
//.
|
||||
// CK2-32: [[META5]] = !{}
|
||||
// CK2-32: [[META6]] = !{i64 4}
|
||||
// CK2-32: [[META6]] = !{}
|
||||
// CK2-32: [[META7]] = !{i64 4}
|
||||
//.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user