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Revert "[OpenMP][clang] 6.0: num_threads strict (part 3: codegen)" (#155809)

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Reverts llvm/llvm-project#146405
This commit is contained in:
Robert Imschweiler 2025-08-28 12:12:53 +02:00 committed by GitHub
parent 608b51e167
commit 9d7e436d86
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GPG Key ID: B5690EEEBB952194
30 changed files with 463 additions and 17061 deletions
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59
clang/include/clang/AST/OpenMPClause.h
View File

@ -1865,43 +1865,62 @@ public:
/// \endcode
/// In this example directive '#pragma omp error' has simple
/// 'message' clause with user error message of "GNU compiler required.".
class OMPMessageClause final
: public OMPOneStmtClause<llvm::omp::OMPC_message, OMPClause>,
public OMPClauseWithPreInit {
class OMPMessageClause final : public OMPClause {
friend class OMPClauseReader;
/// Location of '('
SourceLocation LParenLoc;
// Expression of the 'message' clause.
Stmt *MessageString = nullptr;
/// Set message string of the clause.
void setMessageString(Expr *MS) { setStmt(MS); }
void setMessageString(Expr *MS) { MessageString = MS; }
/// Sets the location of '('.
void setLParenLoc(SourceLocation Loc) { LParenLoc = Loc; }
public:
/// Build 'message' clause with message string argument
///
/// \param MS Argument of the clause (message string).
/// \param HelperMS Helper statement for the construct.
/// \param CaptureRegion Innermost OpenMP region where expressions in this
/// clause must be captured.
/// \param StartLoc Starting location of the clause.
/// \param LParenLoc Location of '('.
/// \param EndLoc Ending location of the clause.
OMPMessageClause(Expr *MS, Stmt *HelperMS, OpenMPDirectiveKind CaptureRegion,
SourceLocation StartLoc, SourceLocation LParenLoc,
OMPMessageClause(Expr *MS, SourceLocation StartLoc, SourceLocation LParenLoc,
SourceLocation EndLoc)
: OMPOneStmtClause(MS, StartLoc, LParenLoc, EndLoc),
OMPClauseWithPreInit(this) {
setPreInitStmt(HelperMS, CaptureRegion);
}
: OMPClause(llvm::omp::OMPC_message, StartLoc, EndLoc),
LParenLoc(LParenLoc), MessageString(MS) {}
/// Build an empty clause.
OMPMessageClause() : OMPOneStmtClause(), OMPClauseWithPreInit(this) {}
OMPMessageClause()
: OMPClause(llvm::omp::OMPC_message, SourceLocation(), SourceLocation()) {
}
/// Returns the locaiton of '('.
SourceLocation getLParenLoc() const { return LParenLoc; }
/// Returns message string of the clause.
Expr *getMessageString() const { return getStmtAs<Expr>(); }
Expr *getMessageString() const { return cast_or_null<Expr>(MessageString); }
/// Try to evaluate the message string at compile time.
std::optional<std::string> tryEvaluateString(ASTContext &Ctx) const {
if (Expr *MessageExpr = getMessageString())
return MessageExpr->tryEvaluateString(Ctx);
return std::nullopt;
child_range children() {
return child_range(&MessageString, &MessageString + 1);
}
const_child_range children() const {
return const_child_range(&MessageString, &MessageString + 1);
}
child_range used_children() {
return child_range(child_iterator(), child_iterator());
}
const_child_range used_children() const {
return const_child_range(const_child_iterator(), const_child_iterator());
}
static bool classof(const OMPClause *T) {
return T->getClauseKind() == llvm::omp::OMPC_message;
}
};

4
clang/include/clang/Basic/DiagnosticParseKinds.td
View File

@ -1506,10 +1506,8 @@ def err_omp_unexpected_directive : Error<
"unexpected OpenMP directive %select{|'#pragma omp %1'}0">;
def err_omp_expected_punc : Error<
"expected ',' or ')' in '%0' %select{clause|directive}1">;
def warn_clause_expected_string_literal : Warning<
def warn_clause_expected_string : Warning<
"expected string literal in 'clause %0' - ignoring">, InGroup<IgnoredPragmas>;
def warn_clause_expected_string: Warning<
"expected string in 'clause %0' - ignoring">, InGroup<IgnoredPragmas>;
def err_omp_unexpected_clause : Error<
"unexpected OpenMP clause '%0' in directive '#pragma omp %1'">;
def err_omp_unexpected_clause_extension_only : Error<

9
clang/lib/AST/OpenMPClause.cpp
View File

@ -104,8 +104,6 @@ const OMPClauseWithPreInit *OMPClauseWithPreInit::get(const OMPClause *C) {
return static_cast<const OMPFilterClause *>(C);
case OMPC_ompx_dyn_cgroup_mem:
return static_cast<const OMPXDynCGroupMemClause *>(C);
case OMPC_message:
return static_cast<const OMPMessageClause *>(C);
case OMPC_default:
case OMPC_proc_bind:
case OMPC_safelen:
@ -160,6 +158,7 @@ const OMPClauseWithPreInit *OMPClauseWithPreInit::get(const OMPClause *C) {
case OMPC_self_maps:
case OMPC_at:
case OMPC_severity:
case OMPC_message:
case OMPC_device_type:
case OMPC_match:
case OMPC_nontemporal:
@ -1964,10 +1963,8 @@ void OMPClausePrinter::VisitOMPSeverityClause(OMPSeverityClause *Node) {
}
void OMPClausePrinter::VisitOMPMessageClause(OMPMessageClause *Node) {
OS << "message(";
if (Expr *E = Node->getMessageString())
E->printPretty(OS, nullptr, Policy);
OS << ")";
OS << "message(\""
<< cast<StringLiteral>(Node->getMessageString())->getString() << "\")";
}
void OMPClausePrinter::VisitOMPScheduleClause(OMPScheduleClause *Node) {

87
clang/lib/CodeGen/CGOpenMPRuntime.cpp
View File

@ -1845,11 +1845,11 @@ void CGOpenMPRuntime::emitIfClause(CodeGenFunction &CGF, const Expr *Cond,
CGF.EmitBlock(ContBlock, /*IsFinished=*/true);
}
void CGOpenMPRuntime::emitParallelCall(
CodeGenFunction &CGF, SourceLocation Loc, llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars, const Expr *IfCond,
llvm::Value *NumThreads, OpenMPNumThreadsClauseModifier NumThreadsModifier,
OpenMPSeverityClauseKind Severity, const Expr *Message) {
void CGOpenMPRuntime::emitParallelCall(CodeGenFunction &CGF, SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars,
const Expr *IfCond,
llvm::Value *NumThreads) {
if (!CGF.HaveInsertPoint())
return;
llvm::Value *RTLoc = emitUpdateLocation(CGF, Loc);
@ -2372,8 +2372,9 @@ void CGOpenMPRuntime::emitBarrierCall(CodeGenFunction &CGF, SourceLocation Loc,
void CGOpenMPRuntime::emitErrorCall(CodeGenFunction &CGF, SourceLocation Loc,
Expr *ME, bool IsFatal) {
llvm::Value *MVL = ME ? CGF.EmitScalarExpr(ME)
: llvm::ConstantPointerNull::get(CGF.VoidPtrTy);
llvm::Value *MVL =
ME ? CGF.EmitStringLiteralLValue(cast<StringLiteral>(ME)).getPointer(CGF)
: llvm::ConstantPointerNull::get(CGF.VoidPtrTy);
// Build call void __kmpc_error(ident_t *loc, int severity, const char
// *message)
llvm::Value *Args[] = {
@ -2698,54 +2699,18 @@ llvm::Value *CGOpenMPRuntime::emitForNext(CodeGenFunction &CGF,
CGF.getContext().BoolTy, Loc);
}
llvm::Value *CGOpenMPRuntime::emitMessageClause(CodeGenFunction &CGF,
const Expr *Message) {
if (!Message)
return llvm::ConstantPointerNull::get(CGF.VoidPtrTy);
return CGF.EmitScalarExpr(Message);
}
llvm::Value *
CGOpenMPRuntime::emitMessageClause(CodeGenFunction &CGF,
const OMPMessageClause *MessageClause) {
return emitMessageClause(
CGF, MessageClause ? MessageClause->getMessageString() : nullptr);
}
llvm::Value *
CGOpenMPRuntime::emitSeverityClause(OpenMPSeverityClauseKind Severity) {
// OpenMP 6.0, 10.4: "If no severity clause is specified then the effect is
// as if sev-level is fatal."
return llvm::ConstantInt::get(CGM.Int32Ty,
Severity == OMPC_SEVERITY_warning ? 1 : 2);
}
llvm::Value *
CGOpenMPRuntime::emitSeverityClause(const OMPSeverityClause *SeverityClause) {
return emitSeverityClause(SeverityClause ? SeverityClause->getSeverityKind()
: OMPC_SEVERITY_unknown);
}
void CGOpenMPRuntime::emitNumThreadsClause(
CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc,
OpenMPNumThreadsClauseModifier Modifier, OpenMPSeverityClauseKind Severity,
const Expr *Message) {
void CGOpenMPRuntime::emitNumThreadsClause(CodeGenFunction &CGF,
llvm::Value *NumThreads,
SourceLocation Loc) {
if (!CGF.HaveInsertPoint())
return;
llvm::SmallVector<llvm::Value *, 4> Args(
{emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc),
CGF.Builder.CreateIntCast(NumThreads, CGF.Int32Ty, /*isSigned*/ true)});
// Build call __kmpc_push_num_threads(&loc, global_tid, num_threads)
// or __kmpc_push_num_threads_strict(&loc, global_tid, num_threads, severity,
// messsage) if strict modifier is used.
RuntimeFunction FnID = OMPRTL___kmpc_push_num_threads;
if (Modifier == OMPC_NUMTHREADS_strict) {
FnID = OMPRTL___kmpc_push_num_threads_strict;
Args.push_back(emitSeverityClause(Severity));
Args.push_back(emitMessageClause(CGF, Message));
}
CGF.EmitRuntimeCall(
OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), FnID), Args);
llvm::Value *Args[] = {
emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc),
CGF.Builder.CreateIntCast(NumThreads, CGF.Int32Ty, /*isSigned*/ true)};
CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction(
CGM.getModule(), OMPRTL___kmpc_push_num_threads),
Args);
}
void CGOpenMPRuntime::emitProcBindClause(CodeGenFunction &CGF,
@ -12149,11 +12114,12 @@ llvm::Function *CGOpenMPSIMDRuntime::emitTaskOutlinedFunction(
llvm_unreachable("Not supported in SIMD-only mode");
}
void CGOpenMPSIMDRuntime::emitParallelCall(
CodeGenFunction &CGF, SourceLocation Loc, llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars, const Expr *IfCond,
llvm::Value *NumThreads, OpenMPNumThreadsClauseModifier NumThreadsModifier,
OpenMPSeverityClauseKind Severity, const Expr *Message) {
void CGOpenMPSIMDRuntime::emitParallelCall(CodeGenFunction &CGF,
SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars,
const Expr *IfCond,
llvm::Value *NumThreads) {
llvm_unreachable("Not supported in SIMD-only mode");
}
@ -12256,10 +12222,9 @@ llvm::Value *CGOpenMPSIMDRuntime::emitForNext(CodeGenFunction &CGF,
llvm_unreachable("Not supported in SIMD-only mode");
}
void CGOpenMPSIMDRuntime::emitNumThreadsClause(
CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc,
OpenMPNumThreadsClauseModifier Modifier, OpenMPSeverityClauseKind Severity,
const Expr *Message) {
void CGOpenMPSIMDRuntime::emitNumThreadsClause(CodeGenFunction &CGF,
llvm::Value *NumThreads,
SourceLocation Loc) {
llvm_unreachable("Not supported in SIMD-only mode");
}

63
clang/lib/CodeGen/CGOpenMPRuntime.h
View File

@ -777,22 +777,11 @@ public:
/// specified, nullptr otherwise.
/// \param NumThreads The value corresponding to the num_threads clause, if
/// any, or nullptr.
/// \param NumThreadsModifier The modifier of the num_threads clause, if
/// any, ignored otherwise.
/// \param Severity The severity corresponding to the num_threads clause, if
/// any, ignored otherwise.
/// \param Message The message string corresponding to the num_threads clause,
/// if any, or nullptr.
///
virtual void
emitParallelCall(CodeGenFunction &CGF, SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars, const Expr *IfCond,
llvm::Value *NumThreads,
OpenMPNumThreadsClauseModifier NumThreadsModifier =
OMPC_NUMTHREADS_unknown,
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal,
const Expr *Message = nullptr);
virtual void emitParallelCall(CodeGenFunction &CGF, SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars,
const Expr *IfCond, llvm::Value *NumThreads);
/// Emits a critical region.
/// \param CriticalName Name of the critical region.
@ -1048,28 +1037,13 @@ public:
Address IL, Address LB,
Address UB, Address ST);
virtual llvm::Value *emitMessageClause(CodeGenFunction &CGF,
const Expr *Message);
virtual llvm::Value *emitMessageClause(CodeGenFunction &CGF,
const OMPMessageClause *MessageClause);
virtual llvm::Value *emitSeverityClause(OpenMPSeverityClauseKind Severity);
virtual llvm::Value *
emitSeverityClause(const OMPSeverityClause *SeverityClause);
/// Emits call to void __kmpc_push_num_threads(ident_t *loc, kmp_int32
/// global_tid, kmp_int32 num_threads) to generate code for 'num_threads'
/// clause.
/// If the modifier 'strict' is given:
/// Emits call to void __kmpc_push_num_threads_strict(ident_t *loc, kmp_int32
/// global_tid, kmp_int32 num_threads, int severity, const char *message) to
/// generate code for 'num_threads' clause with 'strict' modifier.
/// \param NumThreads An integer value of threads.
virtual void emitNumThreadsClause(
CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc,
OpenMPNumThreadsClauseModifier Modifier = OMPC_NUMTHREADS_unknown,
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal,
const Expr *Message = nullptr);
virtual void emitNumThreadsClause(CodeGenFunction &CGF,
llvm::Value *NumThreads,
SourceLocation Loc);
/// Emit call to void __kmpc_push_proc_bind(ident_t *loc, kmp_int32
/// global_tid, int proc_bind) to generate code for 'proc_bind' clause.
@ -1763,21 +1737,11 @@ public:
/// specified, nullptr otherwise.
/// \param NumThreads The value corresponding to the num_threads clause, if
/// any, or nullptr.
/// \param NumThreadsModifier The modifier of the num_threads clause, if
/// any, ignored otherwise.
/// \param Severity The severity corresponding to the num_threads clause, if
/// any, ignored otherwise.
/// \param Message The message string corresponding to the num_threads clause,
/// if any, or nullptr.
///
void emitParallelCall(CodeGenFunction &CGF, SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars,
const Expr *IfCond, llvm::Value *NumThreads,
OpenMPNumThreadsClauseModifier NumThreadsModifier =
OMPC_NUMTHREADS_unknown,
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal,
const Expr *Message = nullptr) override;
const Expr *IfCond, llvm::Value *NumThreads) override;
/// Emits a critical region.
/// \param CriticalName Name of the critical region.
@ -1947,16 +1911,9 @@ public:
/// Emits call to void __kmpc_push_num_threads(ident_t *loc, kmp_int32
/// global_tid, kmp_int32 num_threads) to generate code for 'num_threads'
/// clause.
/// If the modifier 'strict' is given:
/// Emits call to void __kmpc_push_num_threads_strict(ident_t *loc, kmp_int32
/// global_tid, kmp_int32 num_threads, int severity, const char *message) to
/// generate code for 'num_threads' clause with 'strict' modifier.
/// \param NumThreads An integer value of threads.
void emitNumThreadsClause(
CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc,
OpenMPNumThreadsClauseModifier Modifier = OMPC_NUMTHREADS_unknown,
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal,
const Expr *Message = nullptr) override;
void emitNumThreadsClause(CodeGenFunction &CGF, llvm::Value *NumThreads,
SourceLocation Loc) override;
/// Emit call to void __kmpc_push_proc_bind(ident_t *loc, kmp_int32
/// global_tid, int proc_bind) to generate code for 'proc_bind' clause.

53
clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
View File

@ -899,10 +899,9 @@ void CGOpenMPRuntimeGPU::emitProcBindClause(CodeGenFunction &CGF,
// Nothing to do.
}
void CGOpenMPRuntimeGPU::emitNumThreadsClause(
CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc,
OpenMPNumThreadsClauseModifier Modifier, OpenMPSeverityClauseKind Severity,
const Expr *Message) {
void CGOpenMPRuntimeGPU::emitNumThreadsClause(CodeGenFunction &CGF,
llvm::Value *NumThreads,
SourceLocation Loc) {
// Nothing to do.
}
@ -1202,17 +1201,18 @@ void CGOpenMPRuntimeGPU::emitTeamsCall(CodeGenFunction &CGF,
emitOutlinedFunctionCall(CGF, Loc, OutlinedFn, OutlinedFnArgs);
}
void CGOpenMPRuntimeGPU::emitParallelCall(
CodeGenFunction &CGF, SourceLocation Loc, llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars, const Expr *IfCond,
llvm::Value *NumThreads, OpenMPNumThreadsClauseModifier NumThreadsModifier,
OpenMPSeverityClauseKind Severity, const Expr *Message) {
void CGOpenMPRuntimeGPU::emitParallelCall(CodeGenFunction &CGF,
SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars,
const Expr *IfCond,
llvm::Value *NumThreads) {
if (!CGF.HaveInsertPoint())
return;
auto &&ParallelGen = [this, Loc, OutlinedFn, CapturedVars, IfCond, NumThreads,
NumThreadsModifier, Severity, Message](
CodeGenFunction &CGF, PrePostActionTy &Action) {
auto &&ParallelGen = [this, Loc, OutlinedFn, CapturedVars, IfCond,
NumThreads](CodeGenFunction &CGF,
PrePostActionTy &Action) {
CGBuilderTy &Bld = CGF.Builder;
llvm::Value *NumThreadsVal = NumThreads;
llvm::Function *WFn = WrapperFunctionsMap[OutlinedFn];
@ -1260,22 +1260,21 @@ void CGOpenMPRuntimeGPU::emitParallelCall(
NumThreadsVal = Bld.CreateZExtOrTrunc(NumThreadsVal, CGF.Int32Ty);
assert(IfCondVal && "Expected a value");
RuntimeFunction FnID = OMPRTL___kmpc_parallel_51;
llvm::Value *RTLoc = emitUpdateLocation(CGF, Loc);
llvm::SmallVector<llvm::Value *, 10> Args(
{RTLoc, getThreadID(CGF, Loc), IfCondVal, NumThreadsVal,
llvm::ConstantInt::get(CGF.Int32Ty, -1), FnPtr, ID,
Bld.CreateBitOrPointerCast(CapturedVarsAddrs.emitRawPointer(CGF),
CGF.VoidPtrPtrTy),
llvm::ConstantInt::get(CGM.SizeTy, CapturedVars.size())});
if (NumThreadsModifier == OMPC_NUMTHREADS_strict) {
FnID = OMPRTL___kmpc_parallel_60;
Args.append({llvm::ConstantInt::get(CGM.Int32Ty, true),
emitSeverityClause(Severity),
emitMessageClause(CGF, Message)});
}
CGF.EmitRuntimeCall(
OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), FnID), Args);
llvm::Value *Args[] = {
RTLoc,
getThreadID(CGF, Loc),
IfCondVal,
NumThreadsVal,
llvm::ConstantInt::get(CGF.Int32Ty, -1),
FnPtr,
ID,
Bld.CreateBitOrPointerCast(CapturedVarsAddrs.emitRawPointer(CGF),
CGF.VoidPtrPtrTy),
llvm::ConstantInt::get(CGM.SizeTy, CapturedVars.size())};
CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction(
CGM.getModule(), OMPRTL___kmpc_parallel_51),
Args);
};
RegionCodeGenTy RCG(ParallelGen);

26
clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
View File

@ -165,16 +165,9 @@ public:
/// Emits call to void __kmpc_push_num_threads(ident_t *loc, kmp_int32
/// global_tid, kmp_int32 num_threads) to generate code for 'num_threads'
/// clause.
/// If the modifier 'strict' is given:
/// Emits call to void __kmpc_push_num_threads_strict(ident_t *loc, kmp_int32
/// global_tid, kmp_int32 num_threads, int severity, const char *message) to
/// generate code for 'num_threads' clause with 'strict' modifier.
/// \param NumThreads An integer value of threads.
void emitNumThreadsClause(
CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc,
OpenMPNumThreadsClauseModifier Modifier = OMPC_NUMTHREADS_unknown,
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal,
const Expr *Message = nullptr) override;
void emitNumThreadsClause(CodeGenFunction &CGF, llvm::Value *NumThreads,
SourceLocation Loc) override;
/// This function ought to emit, in the general case, a call to
// the openmp runtime kmpc_push_num_teams. In NVPTX backend it is not needed
@ -236,21 +229,12 @@ public:
/// \param IfCond Condition in the associated 'if' clause, if it was
/// specified, nullptr otherwise.
/// \param NumThreads The value corresponding to the num_threads clause, if
/// any, or nullptr.
/// \param NumThreadsModifier The modifier of the num_threads clause, if
/// any, ignored otherwise.
/// \param Severity The severity corresponding to the num_threads clause, if
/// any, ignored otherwise.
/// \param Message The message string corresponding to the num_threads clause,
/// if any, or nullptr.
/// any,
/// or nullptr.
void emitParallelCall(CodeGenFunction &CGF, SourceLocation Loc,
llvm::Function *OutlinedFn,
ArrayRef<llvm::Value *> CapturedVars,
const Expr *IfCond, llvm::Value *NumThreads,
OpenMPNumThreadsClauseModifier NumThreadsModifier =
OMPC_NUMTHREADS_unknown,
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal,
const Expr *Message = nullptr) override;
const Expr *IfCond, llvm::Value *NumThreads) override;
/// Emit an implicit/explicit barrier for OpenMP threads.
/// \param Kind Directive for which this implicit barrier call must be

16
clang/lib/CodeGen/CGStmtOpenMP.cpp
View File

@ -1608,11 +1608,6 @@ static void emitCommonOMPParallelDirective(
const CodeGenBoundParametersTy &CodeGenBoundParameters) {
const CapturedStmt *CS = S.getCapturedStmt(OMPD_parallel);
llvm::Value *NumThreads = nullptr;
OpenMPNumThreadsClauseModifier Modifier = OMPC_NUMTHREADS_unknown;
// OpenMP 6.0, 10.4: "If no severity clause is specified then the effect is as
// if sev-level is fatal."
OpenMPSeverityClauseKind Severity = OMPC_SEVERITY_fatal;
clang::Expr *Message = nullptr;
llvm::Function *OutlinedFn =
CGF.CGM.getOpenMPRuntime().emitParallelOutlinedFunction(
CGF, S, *CS->getCapturedDecl()->param_begin(), InnermostKind,
@ -1621,14 +1616,8 @@ static void emitCommonOMPParallelDirective(
CodeGenFunction::RunCleanupsScope NumThreadsScope(CGF);
NumThreads = CGF.EmitScalarExpr(NumThreadsClause->getNumThreads(),
/*IgnoreResultAssign=*/true);
Modifier = NumThreadsClause->getModifier();
if (const auto *MessageClause = S.getSingleClause<OMPMessageClause>())
Message = MessageClause->getMessageString();
if (const auto *SeverityClause = S.getSingleClause<OMPSeverityClause>())
Severity = SeverityClause->getSeverityKind();
CGF.CGM.getOpenMPRuntime().emitNumThreadsClause(
CGF, NumThreads, NumThreadsClause->getBeginLoc(), Modifier, Severity,
Message);
CGF, NumThreads, NumThreadsClause->getBeginLoc());
}
if (const auto *ProcBindClause = S.getSingleClause<OMPProcBindClause>()) {
CodeGenFunction::RunCleanupsScope ProcBindScope(CGF);
@ -1653,8 +1642,7 @@ static void emitCommonOMPParallelDirective(
CodeGenBoundParameters(CGF, S, CapturedVars);
CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars);
CGF.CGM.getOpenMPRuntime().emitParallelCall(CGF, S.getBeginLoc(), OutlinedFn,
CapturedVars, IfCond, NumThreads,
Modifier, Severity, Message);
CapturedVars, IfCond, NumThreads);
}
static bool isAllocatableDecl(const VarDecl *VD) {

48
clang/lib/Sema/SemaOpenMP.cpp
View File

@ -11097,27 +11097,22 @@ StmtResult SemaOpenMP::ActOnOpenMPErrorDirective(ArrayRef<OMPClause *> Clauses,
return StmtError();
}
if (!AtC || AtC->getAtKind() == OMPC_AT_compilation) {
const OMPSeverityClause *SeverityC =
OMPExecutableDirective::getSingleClause<OMPSeverityClause>(Clauses);
const OMPMessageClause *MessageC =
OMPExecutableDirective::getSingleClause<OMPMessageClause>(Clauses);
std::optional<std::string> SL =
MessageC ? MessageC->tryEvaluateString(getASTContext()) : std::nullopt;
const OMPSeverityClause *SeverityC =
OMPExecutableDirective::getSingleClause<OMPSeverityClause>(Clauses);
const OMPMessageClause *MessageC =
OMPExecutableDirective::getSingleClause<OMPMessageClause>(Clauses);
Expr *ME = MessageC ? MessageC->getMessageString() : nullptr;
if (MessageC && !SL)
Diag(MessageC->getMessageString()->getBeginLoc(),
diag::warn_clause_expected_string_literal)
<< getOpenMPClauseNameForDiag(OMPC_message);
if (!AtC || AtC->getAtKind() == OMPC_AT_compilation) {
if (SeverityC && SeverityC->getSeverityKind() == OMPC_SEVERITY_warning)
Diag(SeverityC->getSeverityKindKwLoc(), diag::warn_diagnose_if_succeeded)
<< SL.value_or("WARNING");
<< (ME ? cast<StringLiteral>(ME)->getString() : "WARNING");
else
Diag(StartLoc, diag::err_diagnose_if_succeeded) << SL.value_or("ERROR");
Diag(StartLoc, diag::err_diagnose_if_succeeded)
<< (ME ? cast<StringLiteral>(ME)->getString() : "ERROR");
if (!SeverityC || SeverityC->getSeverityKind() != OMPC_SEVERITY_warning)
return StmtError();
}
return OMPErrorDirective::Create(getASTContext(), StartLoc, EndLoc, Clauses);
}
@ -16469,32 +16464,13 @@ OMPClause *SemaOpenMP::ActOnOpenMPMessageClause(Expr *ME,
SourceLocation LParenLoc,
SourceLocation EndLoc) {
assert(ME && "NULL expr in Message clause");
QualType Type = ME->getType();
if ((!Type->isPointerType() && !Type->isArrayType()) ||
!Type->getPointeeOrArrayElementType()->isAnyCharacterType()) {
if (!isa<StringLiteral>(ME)) {
Diag(ME->getBeginLoc(), diag::warn_clause_expected_string)
<< getOpenMPClauseNameForDiag(OMPC_message);
return nullptr;
}
Stmt *HelperValStmt = nullptr;
OpenMPDirectiveKind DKind = DSAStack->getCurrentDirective();
OpenMPDirectiveKind CaptureRegion = getOpenMPCaptureRegionForClause(
DKind, OMPC_message, getLangOpts().OpenMP);
if (CaptureRegion != OMPD_unknown &&
!SemaRef.CurContext->isDependentContext()) {
ME = SemaRef.MakeFullExpr(ME).get();
llvm::MapVector<const Expr *, DeclRefExpr *> Captures;
ME = tryBuildCapture(SemaRef, ME, Captures).get();
HelperValStmt = buildPreInits(getASTContext(), Captures);
}
// Convert array type to pointer type if needed.
ME = SemaRef.DefaultFunctionArrayLvalueConversion(ME).get();
return new (getASTContext()) OMPMessageClause(
ME, HelperValStmt, CaptureRegion, StartLoc, LParenLoc, EndLoc);
return new (getASTContext())
OMPMessageClause(ME, StartLoc, LParenLoc, EndLoc);
}
OMPClause *SemaOpenMP::ActOnOpenMPOrderClause(

3
clang/lib/Sema/TreeTransform.h
View File

@ -10953,7 +10953,8 @@ TreeTransform<Derived>::TransformOMPMessageClause(OMPMessageClause *C) {
if (E.isInvalid())
return nullptr;
return getDerived().RebuildOMPMessageClause(
E.get(), C->getBeginLoc(), C->getLParenLoc(), C->getEndLoc());
C->getMessageString(), C->getBeginLoc(), C->getLParenLoc(),
C->getEndLoc());
}
template <typename Derived>

1
clang/lib/Serialization/ASTReader.cpp
View File

@ -11842,7 +11842,6 @@ void OMPClauseReader::VisitOMPSeverityClause(OMPSeverityClause *C) {
}
void OMPClauseReader::VisitOMPMessageClause(OMPMessageClause *C) {
VisitOMPClauseWithPreInit(C);
C->setMessageString(Record.readSubExpr());
C->setLParenLoc(Record.readSourceLocation());
}

1
clang/lib/Serialization/ASTWriter.cpp
View File

@ -8547,7 +8547,6 @@ void OMPClauseWriter::VisitOMPSeverityClause(OMPSeverityClause *C) {
}
void OMPClauseWriter::VisitOMPMessageClause(OMPMessageClause *C) {
VisitOMPClauseWithPreInit(C);
Record.AddStmt(C->getMessageString());
Record.AddSourceLocation(C->getLParenLoc());
}

1095
clang/test/OpenMP/amdgcn_target_parallel_num_threads_codegen.cpp
View File

File diff suppressed because it is too large Load Diff

2880
clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
View File

File diff suppressed because it is too large Load Diff

3541
clang/test/OpenMP/distribute_parallel_for_simd_num_threads_strict_codegen.cpp
View File

File diff suppressed because it is too large Load Diff

734
clang/test/OpenMP/error_codegen.cpp
View File

@ -1,9 +1,8 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 5
// RUN: %clang_cc1 -std=c++11 -fopenmp -fopenmp-version=51 -triple x86_64 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix OMP51 %s
// RUN: -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -std=c++11 -fopenmp -fopenmp-version=60 -triple x86_64 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix OMP60 %s
// RUN: -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -std=c++11 -fopenmp-simd -fopenmp-version=51 \
// RUN: -debug-info-kind=limited -triple x86_64 -emit-llvm -o - %s | \
@ -13,6 +12,20 @@
// RUN: -debug-info-kind=limited -triple x86_64 -emit-llvm -o - %s | \
// RUN: FileCheck --check-prefix SIMD %s
//CHECK: @.str = private unnamed_addr constant [23 x i8] c"GPU compiler required.\00", align 1
//CHECK: @0 = private unnamed_addr constant {{.*}}error_codegen.cpp;main;59;1;;\00", align 1
//CHECK: @1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{.*}}, ptr @0 }, align 8
//CHECK: @.str.1 = private unnamed_addr constant [27 x i8] c"Note this is functioncall.\00", align 1
//CHECK: @2 = private unnamed_addr constant {{.*}}error_codegen.cpp;main;61;1;;\00", align 1
//CHECK: @3 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{.*}}, ptr @2 }, align 8
//CHECK: @.str.2 = private unnamed_addr constant [23 x i8] c"GNU compiler required.\00", align 1
//CHECK: @4 = private unnamed_addr constant {{.*}}error_codegen.cpp;tmain;36;1;;\00", align 1
//CHECK: @5 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{.*}}, ptr @4 }, align 8
//CHECK: @.str.3 = private unnamed_addr constant [22 x i8] c"Notice: add for loop.\00", align 1
//CHECK: @6 = private unnamed_addr constant {{.*}}error_codegen.cpp;tmain;39;1;;\00", align 1
//CHECK: @7 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{.*}}, ptr @6 }, align 8
//CHECK: @8 = private unnamed_addr constant {{.*}}error_codegen.cpp;tmain;45;1;;\00", align 1
//CHECK: @9 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{.*}}, ptr @8 }, align 8
void foo() {}
@ -20,723 +33,42 @@ template <typename T, int N>
int tmain(T argc, char **argv) {
T b = argc, c, d, e, f, g;
static int a;
const char str1[] = "msg";
const char *str2 = "msg";
char str3[] = "msg";
char *str4 = str3;
char * const str5 = str3;
#pragma omp error at(execution) severity(fatal) message("GNU compiler required.")
#pragma omp error at(execution) severity(fatal) message(str1)
#pragma omp error at(execution) severity(fatal) message(str2)
#pragma omp error at(execution) severity(fatal) message(str3)
#pragma omp error at(execution) severity(fatal) message(str4)
#pragma omp error at(execution) severity(fatal) message(str5)
a = argv[0][0];
++a;
#pragma omp error at(execution) severity(warning) message("Notice: add for loop.")
#pragma omp error at(execution) severity(warning) message(str1)
#pragma omp error at(execution) severity(warning) message(str2)
#pragma omp error at(execution) severity(warning) message(str3)
#pragma omp error at(execution) severity(warning) message(str4)
#pragma omp error at(execution) severity(warning) message(str5)
{
int b = 10;
T c = 100;
a = b + c;
}
#pragma omp error at(execution) severity(fatal) message("GPU compiler required.")
#pragma omp error at(execution) severity(fatal) message(str1)
#pragma omp error at(execution) severity(fatal) message(str2)
#pragma omp error at(execution) severity(fatal) message(str3)
#pragma omp error at(execution) severity(fatal) message(str4)
#pragma omp error at(execution) severity(fatal) message(str5)
#pragma omp error at(execution) severity(fatal) message("GPU compiler required.")
foo();
return N;
}
// CHECK-LABEL: @main(
// SIMD-LABEL: @main(
// CHECK: call void @__kmpc_error(ptr @1, i32 2, ptr @.str)
// SIMD-NOT: call void @__kmpc_error(ptr @1, i32 2, ptr @.str)
// CHECK: call void @__kmpc_error(ptr @3, i32 1, ptr @.str.1)
// SIMD-NOT: call void @__kmpc_error(ptr @3, i32 1, ptr @.str.1)
//
int main (int argc, char **argv) {
int b = argc, c, d, e, f, g;
static int a;
const char str1[] = "msg";
const char *str2 = "msg";
char str3[] = "msg";
char *str4 = str3;
char * const str5 = str3;
#pragma omp error at(execution) severity(fatal) message("GPU compiler required.")
#pragma omp error at(execution) severity(fatal) message(str1)
#pragma omp error at(execution) severity(fatal) message(str2)
#pragma omp error at(execution) severity(fatal) message(str3)
#pragma omp error at(execution) severity(fatal) message(str4)
#pragma omp error at(execution) severity(fatal) message(str5)
a=2;
#pragma omp error at(execution) severity(warning) message("Note this is functioncall.")
#pragma omp error at(execution) severity(warning) message(str1)
#pragma omp error at(execution) severity(warning) message(str2)
#pragma omp error at(execution) severity(warning) message(str3)
#pragma omp error at(execution) severity(warning) message(str4)
#pragma omp error at(execution) severity(warning) message(str5)
foo();
tmain<int, 10>(argc, argv);
}
// CHECK-LABEL: define dso_local void @_Z3foov(
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: ret void
// CHECK-LABEL: define dso_local noundef i32 @main(
// CHECK-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[E:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[F:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[G:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// CHECK-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// CHECK-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK-NEXT: store i32 [[TMP0]], ptr [[B]], align 4
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const.main.str1, i64 4, i1 false)
// CHECK-NEXT: store ptr @.str, ptr [[STR2]], align 8
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const.main.str3, i64 4, i1 false)
// CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8
// CHECK-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.str.1)
// CHECK-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB3:[0-9]+]], i32 2, ptr [[ARRAYDECAY2]])
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[STR2]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB5:[0-9]+]], i32 2, ptr [[TMP1]])
// CHECK-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB7:[0-9]+]], i32 2, ptr [[ARRAYDECAY3]])
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[STR4]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB9:[0-9]+]], i32 2, ptr [[TMP2]])
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB11:[0-9]+]], i32 2, ptr [[TMP3]])
// CHECK-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB13:[0-9]+]], i32 1, ptr @.str.2)
// CHECK-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB15:[0-9]+]], i32 1, ptr [[ARRAYDECAY4]])
// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[STR2]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB17:[0-9]+]], i32 1, ptr [[TMP4]])
// CHECK-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB19:[0-9]+]], i32 1, ptr [[ARRAYDECAY5]])
// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[STR4]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB21:[0-9]+]], i32 1, ptr [[TMP5]])
// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB23:[0-9]+]], i32 1, ptr [[TMP6]])
// CHECK-NEXT: call void @_Z3foov()
// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_PPc(i32 noundef [[TMP7]], ptr noundef [[TMP8]])
// CHECK-NEXT: ret i32 0
// CHECK-LABEL: define linkonce_odr noundef i32 @_Z5tmainIiLi10EEiT_PPc(
// CHECK-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0]] comdat {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[D:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[E:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[F:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[G:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// CHECK-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// CHECK-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[B7:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C8:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK-NEXT: store i32 [[TMP0]], ptr [[B]], align 4
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str1, i64 4, i1 false)
// CHECK-NEXT: store ptr @.str, ptr [[STR2]], align 8
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str3, i64 4, i1 false)
// CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8
// CHECK-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB25:[0-9]+]], i32 2, ptr @.str.3)
// CHECK-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB27:[0-9]+]], i32 2, ptr [[ARRAYDECAY2]])
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[STR2]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB29:[0-9]+]], i32 2, ptr [[TMP1]])
// CHECK-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB31:[0-9]+]], i32 2, ptr [[ARRAYDECAY3]])
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[STR4]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB33:[0-9]+]], i32 2, ptr [[TMP2]])
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB35:[0-9]+]], i32 2, ptr [[TMP3]])
// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 0
// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
// CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 0
// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP6]] to i32
// CHECK-NEXT: store i32 [[CONV]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
// CHECK-NEXT: store i32 [[INC]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB37:[0-9]+]], i32 1, ptr @.str.4)
// CHECK-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB39:[0-9]+]], i32 1, ptr [[ARRAYDECAY5]])
// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[STR2]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB41:[0-9]+]], i32 1, ptr [[TMP8]])
// CHECK-NEXT: [[ARRAYDECAY6:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB43:[0-9]+]], i32 1, ptr [[ARRAYDECAY6]])
// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[STR4]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB45:[0-9]+]], i32 1, ptr [[TMP9]])
// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB47:[0-9]+]], i32 1, ptr [[TMP10]])
// CHECK-NEXT: store i32 10, ptr [[B7]], align 4
// CHECK-NEXT: store i32 100, ptr [[C8]], align 4
// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[B7]], align 4
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[C8]], align 4
// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
// CHECK-NEXT: store i32 [[ADD]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB49:[0-9]+]], i32 2, ptr @.str.1)
// CHECK-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB51:[0-9]+]], i32 2, ptr [[ARRAYDECAY9]])
// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[STR2]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB53:[0-9]+]], i32 2, ptr [[TMP13]])
// CHECK-NEXT: [[ARRAYDECAY10:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB55:[0-9]+]], i32 2, ptr [[ARRAYDECAY10]])
// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[STR4]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB57:[0-9]+]], i32 2, ptr [[TMP14]])
// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[STR5]], align 8
// CHECK-NEXT: call void @__kmpc_error(ptr @[[GLOB59:[0-9]+]], i32 2, ptr [[TMP15]])
// CHECK-NEXT: call void @_Z3foov()
// CHECK-NEXT: ret i32 10
// OMP51-LABEL: define dso_local void @_Z3foov(
// OMP51-SAME: ) #[[ATTR0:[0-9]+]] {
// OMP51-NEXT: [[ENTRY:.*:]]
// OMP51-NEXT: ret void
//
//
// OMP51-LABEL: define dso_local noundef i32 @main(
// OMP51-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] {
// OMP51-NEXT: [[ENTRY:.*:]]
// OMP51-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[B:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[C:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[D:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[E:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[F:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[G:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// OMP51-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// OMP51-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// OMP51-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// OMP51-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// OMP51-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// OMP51-NEXT: store i32 [[TMP0]], ptr [[B]], align 4
// OMP51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const.main.str1, i64 4, i1 false)
// OMP51-NEXT: store ptr @.str, ptr [[STR2]], align 8
// OMP51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const.main.str3, i64 4, i1 false)
// OMP51-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8
// OMP51-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.str.1)
// OMP51-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB3:[0-9]+]], i32 2, ptr [[ARRAYDECAY2]])
// OMP51-NEXT: [[TMP1:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB5:[0-9]+]], i32 2, ptr [[TMP1]])
// OMP51-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB7:[0-9]+]], i32 2, ptr [[ARRAYDECAY3]])
// OMP51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB9:[0-9]+]], i32 2, ptr [[TMP2]])
// OMP51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB11:[0-9]+]], i32 2, ptr [[TMP3]])
// OMP51-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB13:[0-9]+]], i32 1, ptr @.str.2)
// OMP51-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB15:[0-9]+]], i32 1, ptr [[ARRAYDECAY4]])
// OMP51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB17:[0-9]+]], i32 1, ptr [[TMP4]])
// OMP51-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB19:[0-9]+]], i32 1, ptr [[ARRAYDECAY5]])
// OMP51-NEXT: [[TMP5:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB21:[0-9]+]], i32 1, ptr [[TMP5]])
// OMP51-NEXT: [[TMP6:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB23:[0-9]+]], i32 1, ptr [[TMP6]])
// OMP51-NEXT: call void @_Z3foov()
// OMP51-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// OMP51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// OMP51-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_PPc(i32 noundef [[TMP7]], ptr noundef [[TMP8]])
// OMP51-NEXT: ret i32 0
//
//
// OMP51-LABEL: define linkonce_odr noundef i32 @_Z5tmainIiLi10EEiT_PPc(
// OMP51-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0]] comdat {
// OMP51-NEXT: [[ENTRY:.*:]]
// OMP51-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[B:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[C:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[D:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[E:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[F:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[G:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// OMP51-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// OMP51-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// OMP51-NEXT: [[B7:%.*]] = alloca i32, align 4
// OMP51-NEXT: [[C8:%.*]] = alloca i32, align 4
// OMP51-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// OMP51-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// OMP51-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// OMP51-NEXT: store i32 [[TMP0]], ptr [[B]], align 4
// OMP51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str1, i64 4, i1 false)
// OMP51-NEXT: store ptr @.str, ptr [[STR2]], align 8
// OMP51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str3, i64 4, i1 false)
// OMP51-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8
// OMP51-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB25:[0-9]+]], i32 2, ptr @.str.3)
// OMP51-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB27:[0-9]+]], i32 2, ptr [[ARRAYDECAY2]])
// OMP51-NEXT: [[TMP1:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB29:[0-9]+]], i32 2, ptr [[TMP1]])
// OMP51-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB31:[0-9]+]], i32 2, ptr [[ARRAYDECAY3]])
// OMP51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB33:[0-9]+]], i32 2, ptr [[TMP2]])
// OMP51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB35:[0-9]+]], i32 2, ptr [[TMP3]])
// OMP51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// OMP51-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 0
// OMP51-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
// OMP51-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 0
// OMP51-NEXT: [[TMP6:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
// OMP51-NEXT: [[CONV:%.*]] = sext i8 [[TMP6]] to i32
// OMP51-NEXT: store i32 [[CONV]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP51-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP51-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
// OMP51-NEXT: store i32 [[INC]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB37:[0-9]+]], i32 1, ptr @.str.4)
// OMP51-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB39:[0-9]+]], i32 1, ptr [[ARRAYDECAY5]])
// OMP51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB41:[0-9]+]], i32 1, ptr [[TMP8]])
// OMP51-NEXT: [[ARRAYDECAY6:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB43:[0-9]+]], i32 1, ptr [[ARRAYDECAY6]])
// OMP51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB45:[0-9]+]], i32 1, ptr [[TMP9]])
// OMP51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB47:[0-9]+]], i32 1, ptr [[TMP10]])
// OMP51-NEXT: store i32 10, ptr [[B7]], align 4
// OMP51-NEXT: store i32 100, ptr [[C8]], align 4
// OMP51-NEXT: [[TMP11:%.*]] = load i32, ptr [[B7]], align 4
// OMP51-NEXT: [[TMP12:%.*]] = load i32, ptr [[C8]], align 4
// OMP51-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
// OMP51-NEXT: store i32 [[ADD]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB49:[0-9]+]], i32 2, ptr @.str.1)
// OMP51-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB51:[0-9]+]], i32 2, ptr [[ARRAYDECAY9]])
// OMP51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB53:[0-9]+]], i32 2, ptr [[TMP13]])
// OMP51-NEXT: [[ARRAYDECAY10:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB55:[0-9]+]], i32 2, ptr [[ARRAYDECAY10]])
// OMP51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB57:[0-9]+]], i32 2, ptr [[TMP14]])
// OMP51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP51-NEXT: call void @__kmpc_error(ptr @[[GLOB59:[0-9]+]], i32 2, ptr [[TMP15]])
// OMP51-NEXT: call void @_Z3foov()
// OMP51-NEXT: ret i32 10
//
//
// OMP60-LABEL: define dso_local void @_Z3foov(
// OMP60-SAME: ) #[[ATTR0:[0-9]+]] {
// OMP60-NEXT: [[ENTRY:.*:]]
// OMP60-NEXT: ret void
//
//
// OMP60-LABEL: define dso_local noundef i32 @main(
// OMP60-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] {
// OMP60-NEXT: [[ENTRY:.*:]]
// OMP60-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[B:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[C:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[D:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[E:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[F:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[G:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// OMP60-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// OMP60-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// OMP60-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// OMP60-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// OMP60-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// OMP60-NEXT: store i32 [[TMP0]], ptr [[B]], align 4
// OMP60-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const.main.str1, i64 4, i1 false)
// OMP60-NEXT: store ptr @.str, ptr [[STR2]], align 8
// OMP60-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const.main.str3, i64 4, i1 false)
// OMP60-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8
// OMP60-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.str.1)
// OMP60-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB3:[0-9]+]], i32 2, ptr [[ARRAYDECAY2]])
// OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB5:[0-9]+]], i32 2, ptr [[TMP1]])
// OMP60-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB7:[0-9]+]], i32 2, ptr [[ARRAYDECAY3]])
// OMP60-NEXT: [[TMP2:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB9:[0-9]+]], i32 2, ptr [[TMP2]])
// OMP60-NEXT: [[TMP3:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB11:[0-9]+]], i32 2, ptr [[TMP3]])
// OMP60-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB13:[0-9]+]], i32 1, ptr @.str.2)
// OMP60-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB15:[0-9]+]], i32 1, ptr [[ARRAYDECAY4]])
// OMP60-NEXT: [[TMP4:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB17:[0-9]+]], i32 1, ptr [[TMP4]])
// OMP60-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB19:[0-9]+]], i32 1, ptr [[ARRAYDECAY5]])
// OMP60-NEXT: [[TMP5:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB21:[0-9]+]], i32 1, ptr [[TMP5]])
// OMP60-NEXT: [[TMP6:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB23:[0-9]+]], i32 1, ptr [[TMP6]])
// OMP60-NEXT: call void @_Z3foov()
// OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// OMP60-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// OMP60-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_PPc(i32 noundef [[TMP7]], ptr noundef [[TMP8]])
// OMP60-NEXT: ret i32 0
//
//
// OMP60-LABEL: define linkonce_odr noundef i32 @_Z5tmainIiLi10EEiT_PPc(
// OMP60-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0]] comdat {
// OMP60-NEXT: [[ENTRY:.*:]]
// OMP60-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[B:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[C:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[D:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[E:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[F:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[G:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// OMP60-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// OMP60-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// OMP60-NEXT: [[B7:%.*]] = alloca i32, align 4
// OMP60-NEXT: [[C8:%.*]] = alloca i32, align 4
// OMP60-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// OMP60-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// OMP60-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// OMP60-NEXT: store i32 [[TMP0]], ptr [[B]], align 4
// OMP60-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str1, i64 4, i1 false)
// OMP60-NEXT: store ptr @.str, ptr [[STR2]], align 8
// OMP60-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str3, i64 4, i1 false)
// OMP60-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8
// OMP60-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB25:[0-9]+]], i32 2, ptr @.str.3)
// OMP60-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB27:[0-9]+]], i32 2, ptr [[ARRAYDECAY2]])
// OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB29:[0-9]+]], i32 2, ptr [[TMP1]])
// OMP60-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB31:[0-9]+]], i32 2, ptr [[ARRAYDECAY3]])
// OMP60-NEXT: [[TMP2:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB33:[0-9]+]], i32 2, ptr [[TMP2]])
// OMP60-NEXT: [[TMP3:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB35:[0-9]+]], i32 2, ptr [[TMP3]])
// OMP60-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// OMP60-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 0
// OMP60-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
// OMP60-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 0
// OMP60-NEXT: [[TMP6:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
// OMP60-NEXT: [[CONV:%.*]] = sext i8 [[TMP6]] to i32
// OMP60-NEXT: store i32 [[CONV]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP60-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
// OMP60-NEXT: store i32 [[INC]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB37:[0-9]+]], i32 1, ptr @.str.4)
// OMP60-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB39:[0-9]+]], i32 1, ptr [[ARRAYDECAY5]])
// OMP60-NEXT: [[TMP8:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB41:[0-9]+]], i32 1, ptr [[TMP8]])
// OMP60-NEXT: [[ARRAYDECAY6:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB43:[0-9]+]], i32 1, ptr [[ARRAYDECAY6]])
// OMP60-NEXT: [[TMP9:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB45:[0-9]+]], i32 1, ptr [[TMP9]])
// OMP60-NEXT: [[TMP10:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB47:[0-9]+]], i32 1, ptr [[TMP10]])
// OMP60-NEXT: store i32 10, ptr [[B7]], align 4
// OMP60-NEXT: store i32 100, ptr [[C8]], align 4
// OMP60-NEXT: [[TMP11:%.*]] = load i32, ptr [[B7]], align 4
// OMP60-NEXT: [[TMP12:%.*]] = load i32, ptr [[C8]], align 4
// OMP60-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
// OMP60-NEXT: store i32 [[ADD]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB49:[0-9]+]], i32 2, ptr @.str.1)
// OMP60-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR1]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB51:[0-9]+]], i32 2, ptr [[ARRAYDECAY9]])
// OMP60-NEXT: [[TMP13:%.*]] = load ptr, ptr [[STR2]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB53:[0-9]+]], i32 2, ptr [[TMP13]])
// OMP60-NEXT: [[ARRAYDECAY10:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB55:[0-9]+]], i32 2, ptr [[ARRAYDECAY10]])
// OMP60-NEXT: [[TMP14:%.*]] = load ptr, ptr [[STR4]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB57:[0-9]+]], i32 2, ptr [[TMP14]])
// OMP60-NEXT: [[TMP15:%.*]] = load ptr, ptr [[STR5]], align 8
// OMP60-NEXT: call void @__kmpc_error(ptr @[[GLOB59:[0-9]+]], i32 2, ptr [[TMP15]])
// OMP60-NEXT: call void @_Z3foov()
// OMP60-NEXT: ret i32 10
//
//
// SIMD-LABEL: define dso_local void @_Z3foov(
// SIMD-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG29:![0-9]+]] {
// SIMD-NEXT: [[ENTRY:.*:]]
// SIMD-NEXT: ret void, !dbg [[DBG32:![0-9]+]]
//
//
// SIMD-LABEL: define dso_local noundef i32 @main(
// SIMD-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG2:![0-9]+]] {
// SIMD-NEXT: [[ENTRY:.*:]]
// SIMD-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[B:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[C:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[D:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[E:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[F:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[G:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// SIMD-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// SIMD-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// SIMD-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// SIMD-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META33:![0-9]+]], !DIExpression(), [[META34:![0-9]+]])
// SIMD-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// SIMD-NEXT: #dbg_declare(ptr [[ARGV_ADDR]], [[META35:![0-9]+]], !DIExpression(), [[META36:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[B]], [[META37:![0-9]+]], !DIExpression(), [[META38:![0-9]+]])
// SIMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG39:![0-9]+]]
// SIMD-NEXT: store i32 [[TMP0]], ptr [[B]], align 4, !dbg [[META38]]
// SIMD-NEXT: #dbg_declare(ptr [[C]], [[META40:![0-9]+]], !DIExpression(), [[META41:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[D]], [[META42:![0-9]+]], !DIExpression(), [[META43:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[E]], [[META44:![0-9]+]], !DIExpression(), [[META45:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[F]], [[META46:![0-9]+]], !DIExpression(), [[META47:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[G]], [[META48:![0-9]+]], !DIExpression(), [[META49:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[STR1]], [[META50:![0-9]+]], !DIExpression(), [[META51:![0-9]+]])
// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const.main.str1, i64 4, i1 false), !dbg [[META51]]
// SIMD-NEXT: #dbg_declare(ptr [[STR2]], [[META52:![0-9]+]], !DIExpression(), [[META54:![0-9]+]])
// SIMD-NEXT: store ptr @.str, ptr [[STR2]], align 8, !dbg [[META54]]
// SIMD-NEXT: #dbg_declare(ptr [[STR3]], [[META55:![0-9]+]], !DIExpression(), [[META57:![0-9]+]])
// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const.main.str3, i64 4, i1 false), !dbg [[META57]]
// SIMD-NEXT: #dbg_declare(ptr [[STR4]], [[META58:![0-9]+]], !DIExpression(), [[META59:![0-9]+]])
// SIMD-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG60:![0-9]+]]
// SIMD-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8, !dbg [[META59]]
// SIMD-NEXT: #dbg_declare(ptr [[STR5]], [[META61:![0-9]+]], !DIExpression(), [[META63:![0-9]+]])
// SIMD-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG64:![0-9]+]]
// SIMD-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8, !dbg [[META63]]
// SIMD-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4, !dbg [[DBG65:![0-9]+]]
// SIMD-NEXT: call void @_Z3foov(), !dbg [[DBG66:![0-9]+]]
// SIMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG67:![0-9]+]]
// SIMD-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG68:![0-9]+]]
// SIMD-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_PPc(i32 noundef [[TMP1]], ptr noundef [[TMP2]]), !dbg [[DBG69:![0-9]+]]
// SIMD-NEXT: ret i32 0, !dbg [[DBG70:![0-9]+]]
//
//
// SIMD-LABEL: define linkonce_odr noundef i32 @_Z5tmainIiLi10EEiT_PPc(
// SIMD-SAME: i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0]] comdat !dbg [[DBG21:![0-9]+]] {
// SIMD-NEXT: [[ENTRY:.*:]]
// SIMD-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[B:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[C:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[D:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[E:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[F:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[G:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[STR1:%.*]] = alloca [4 x i8], align 1
// SIMD-NEXT: [[STR2:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[STR3:%.*]] = alloca [4 x i8], align 1
// SIMD-NEXT: [[STR4:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[STR5:%.*]] = alloca ptr, align 8
// SIMD-NEXT: [[B3:%.*]] = alloca i32, align 4
// SIMD-NEXT: [[C4:%.*]] = alloca i32, align 4
// SIMD-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// SIMD-NEXT: #dbg_declare(ptr [[ARGC_ADDR]], [[META71:![0-9]+]], !DIExpression(), [[META72:![0-9]+]])
// SIMD-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// SIMD-NEXT: #dbg_declare(ptr [[ARGV_ADDR]], [[META73:![0-9]+]], !DIExpression(), [[META74:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[B]], [[META75:![0-9]+]], !DIExpression(), [[META76:![0-9]+]])
// SIMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG77:![0-9]+]]
// SIMD-NEXT: store i32 [[TMP0]], ptr [[B]], align 4, !dbg [[META76]]
// SIMD-NEXT: #dbg_declare(ptr [[C]], [[META78:![0-9]+]], !DIExpression(), [[META79:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[D]], [[META80:![0-9]+]], !DIExpression(), [[META81:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[E]], [[META82:![0-9]+]], !DIExpression(), [[META83:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[F]], [[META84:![0-9]+]], !DIExpression(), [[META85:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[G]], [[META86:![0-9]+]], !DIExpression(), [[META87:![0-9]+]])
// SIMD-NEXT: #dbg_declare(ptr [[STR1]], [[META88:![0-9]+]], !DIExpression(), [[META89:![0-9]+]])
// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR1]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str1, i64 4, i1 false), !dbg [[META89]]
// SIMD-NEXT: #dbg_declare(ptr [[STR2]], [[META90:![0-9]+]], !DIExpression(), [[META91:![0-9]+]])
// SIMD-NEXT: store ptr @.str, ptr [[STR2]], align 8, !dbg [[META91]]
// SIMD-NEXT: #dbg_declare(ptr [[STR3]], [[META92:![0-9]+]], !DIExpression(), [[META93:![0-9]+]])
// SIMD-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[STR3]], ptr align 1 @__const._Z5tmainIiLi10EEiT_PPc.str3, i64 4, i1 false), !dbg [[META93]]
// SIMD-NEXT: #dbg_declare(ptr [[STR4]], [[META94:![0-9]+]], !DIExpression(), [[META95:![0-9]+]])
// SIMD-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG96:![0-9]+]]
// SIMD-NEXT: store ptr [[ARRAYDECAY]], ptr [[STR4]], align 8, !dbg [[META95]]
// SIMD-NEXT: #dbg_declare(ptr [[STR5]], [[META97:![0-9]+]], !DIExpression(), [[META98:![0-9]+]])
// SIMD-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [4 x i8], ptr [[STR3]], i64 0, i64 0, !dbg [[DBG99:![0-9]+]]
// SIMD-NEXT: store ptr [[ARRAYDECAY1]], ptr [[STR5]], align 8, !dbg [[META98]]
// SIMD-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG100:![0-9]+]]
// SIMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i64 0, !dbg [[DBG100]]
// SIMD-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8, !dbg [[DBG100]]
// SIMD-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 0, !dbg [[DBG100]]
// SIMD-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1, !dbg [[DBG100]]
// SIMD-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32, !dbg [[DBG100]]
// SIMD-NEXT: store i32 [[CONV]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG101:![0-9]+]]
// SIMD-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG102:![0-9]+]]
// SIMD-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG102]]
// SIMD-NEXT: store i32 [[INC]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG102]]
// SIMD-NEXT: #dbg_declare(ptr [[B3]], [[META103:![0-9]+]], !DIExpression(), [[META105:![0-9]+]])
// SIMD-NEXT: store i32 10, ptr [[B3]], align 4, !dbg [[META105]]
// SIMD-NEXT: #dbg_declare(ptr [[C4]], [[META106:![0-9]+]], !DIExpression(), [[META107:![0-9]+]])
// SIMD-NEXT: store i32 100, ptr [[C4]], align 4, !dbg [[META107]]
// SIMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[B3]], align 4, !dbg [[DBG108:![0-9]+]]
// SIMD-NEXT: [[TMP6:%.*]] = load i32, ptr [[C4]], align 4, !dbg [[DBG109:![0-9]+]]
// SIMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP6]], !dbg [[DBG110:![0-9]+]]
// SIMD-NEXT: store i32 [[ADD]], ptr @_ZZ5tmainIiLi10EEiT_PPcE1a, align 4, !dbg [[DBG111:![0-9]+]]
// SIMD-NEXT: call void @_Z3foov(), !dbg [[DBG112:![0-9]+]]
// SIMD-NEXT: ret i32 10, !dbg [[DBG113:![0-9]+]]
//
//.
// SIMD: [[META0:![0-9]+]] = !DIGlobalVariableExpression(var: [[META1:![0-9]+]], expr: !DIExpression())
// SIMD: [[META1]] = distinct !DIGlobalVariable(name: "a", scope: [[DBG2]], file: [[META3:![0-9]+]], line: 61, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true)
// SIMD: [[DBG2]] = distinct !DISubprogram(name: "main", scope: [[META3]], file: [[META3]], line: 59, type: [[META4:![0-9]+]], scopeLine: 59, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META10:![0-9]+]], retainedNodes: [[META22:![0-9]+]])
// SIMD: [[META3]] = !DIFile(filename: "{{.*}}error_codegen.cpp", directory: {{.*}})
// SIMD: [[META4]] = !DISubroutineType(types: [[META5:![0-9]+]])
// SIMD: [[META5]] = !{[[META6]], [[META6]], [[META7:![0-9]+]]}
// SIMD: [[META6]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
// SIMD: [[META7]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META8:![0-9]+]], size: 64)
// SIMD: [[META8]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META9:![0-9]+]], size: 64)
// SIMD: [[META9]] = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char)
// SIMD: [[META10]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_11, file: [[META11:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META12:![0-9]+]], splitDebugInlining: false, nameTableKind: None)
// SIMD: [[META11]] = !DIFile(filename: "{{.*}}<stdin>", directory: {{.*}})
// SIMD: [[META12]] = !{[[META0]], [[META13:![0-9]+]], [[META19:![0-9]+]]}
// SIMD: [[META13]] = !DIGlobalVariableExpression(var: [[META14:![0-9]+]], expr: !DIExpression())
// SIMD: [[META14]] = distinct !DIGlobalVariable(scope: null, file: [[META3]], line: 63, type: [[META15:![0-9]+]], isLocal: true, isDefinition: true)
// SIMD: [[META15]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META16:![0-9]+]], size: 32, elements: [[META17:![0-9]+]])
// SIMD: [[META16]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META9]])
// SIMD: [[META17]] = !{[[META18:![0-9]+]]}
// SIMD: [[META18]] = !DISubrange(count: 4)
// SIMD: [[META19]] = !DIGlobalVariableExpression(var: [[META20:![0-9]+]], expr: !DIExpression())
// SIMD: [[META20]] = distinct !DIGlobalVariable(name: "a", scope: [[DBG21]], file: [[META3]], line: 22, type: [[META6]], isLocal: false, isDefinition: true)
// SIMD: [[DBG21]] = distinct !DISubprogram(name: "tmain<int, 10>", linkageName: "_Z5tmainIiLi10EEiT_PPc", scope: [[META3]], file: [[META3]], line: 20, type: [[META4]], scopeLine: 20, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META10]], templateParams: [[META23:![0-9]+]], retainedNodes: [[META22]])
// SIMD: [[META22]] = !{}
// SIMD: [[META23]] = !{[[META24:![0-9]+]], [[META25:![0-9]+]]}
// SIMD: [[META24]] = !DITemplateTypeParameter(name: "T", type: [[META6]])
// SIMD: [[META25]] = !DITemplateValueParameter(name: "N", type: [[META6]], value: i32 10)
// SIMD: [[DBG29]] = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", scope: [[META3]], file: [[META3]], line: 17, type: [[META30:![0-9]+]], scopeLine: 17, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META10]])
// SIMD: [[META30]] = !DISubroutineType(types: [[META31:![0-9]+]])
// SIMD: [[META31]] = !{null}
// SIMD: [[DBG32]] = !DILocation(line: 17, column: 13, scope: [[DBG29]])
// SIMD: [[META33]] = !DILocalVariable(name: "argc", arg: 1, scope: [[DBG2]], file: [[META3]], line: 59, type: [[META6]])
// SIMD: [[META34]] = !DILocation(line: 59, column: 15, scope: [[DBG2]])
// SIMD: [[META35]] = !DILocalVariable(name: "argv", arg: 2, scope: [[DBG2]], file: [[META3]], line: 59, type: [[META7]])
// SIMD: [[META36]] = !DILocation(line: 59, column: 28, scope: [[DBG2]])
// SIMD: [[META37]] = !DILocalVariable(name: "b", scope: [[DBG2]], file: [[META3]], line: 60, type: [[META6]])
// SIMD: [[META38]] = !DILocation(line: 60, column: 7, scope: [[DBG2]])
// SIMD: [[DBG39]] = !DILocation(line: 60, column: 11, scope: [[DBG2]])
// SIMD: [[META40]] = !DILocalVariable(name: "c", scope: [[DBG2]], file: [[META3]], line: 60, type: [[META6]])
// SIMD: [[META41]] = !DILocation(line: 60, column: 17, scope: [[DBG2]])
// SIMD: [[META42]] = !DILocalVariable(name: "d", scope: [[DBG2]], file: [[META3]], line: 60, type: [[META6]])
// SIMD: [[META43]] = !DILocation(line: 60, column: 20, scope: [[DBG2]])
// SIMD: [[META44]] = !DILocalVariable(name: "e", scope: [[DBG2]], file: [[META3]], line: 60, type: [[META6]])
// SIMD: [[META45]] = !DILocation(line: 60, column: 23, scope: [[DBG2]])
// SIMD: [[META46]] = !DILocalVariable(name: "f", scope: [[DBG2]], file: [[META3]], line: 60, type: [[META6]])
// SIMD: [[META47]] = !DILocation(line: 60, column: 26, scope: [[DBG2]])
// SIMD: [[META48]] = !DILocalVariable(name: "g", scope: [[DBG2]], file: [[META3]], line: 60, type: [[META6]])
// SIMD: [[META49]] = !DILocation(line: 60, column: 29, scope: [[DBG2]])
// SIMD: [[META50]] = !DILocalVariable(name: "str1", scope: [[DBG2]], file: [[META3]], line: 62, type: [[META15]])
// SIMD: [[META51]] = !DILocation(line: 62, column: 14, scope: [[DBG2]])
// SIMD: [[META52]] = !DILocalVariable(name: "str2", scope: [[DBG2]], file: [[META3]], line: 63, type: [[META53:![0-9]+]])
// SIMD: [[META53]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META16]], size: 64)
// SIMD: [[META54]] = !DILocation(line: 63, column: 15, scope: [[DBG2]])
// SIMD: [[META55]] = !DILocalVariable(name: "str3", scope: [[DBG2]], file: [[META3]], line: 64, type: [[META56:![0-9]+]])
// SIMD: [[META56]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META9]], size: 32, elements: [[META17]])
// SIMD: [[META57]] = !DILocation(line: 64, column: 8, scope: [[DBG2]])
// SIMD: [[META58]] = !DILocalVariable(name: "str4", scope: [[DBG2]], file: [[META3]], line: 65, type: [[META8]])
// SIMD: [[META59]] = !DILocation(line: 65, column: 9, scope: [[DBG2]])
// SIMD: [[DBG60]] = !DILocation(line: 65, column: 16, scope: [[DBG2]])
// SIMD: [[META61]] = !DILocalVariable(name: "str5", scope: [[DBG2]], file: [[META3]], line: 66, type: [[META62:![0-9]+]])
// SIMD: [[META62]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META8]])
// SIMD: [[META63]] = !DILocation(line: 66, column: 16, scope: [[DBG2]])
// SIMD: [[DBG64]] = !DILocation(line: 66, column: 23, scope: [[DBG2]])
// SIMD: [[DBG65]] = !DILocation(line: 73, column: 5, scope: [[DBG2]])
// SIMD: [[DBG66]] = !DILocation(line: 80, column: 3, scope: [[DBG2]])
// SIMD: [[DBG67]] = !DILocation(line: 81, column: 18, scope: [[DBG2]])
// SIMD: [[DBG68]] = !DILocation(line: 81, column: 24, scope: [[DBG2]])
// SIMD: [[DBG69]] = !DILocation(line: 81, column: 3, scope: [[DBG2]])
// SIMD: [[DBG70]] = !DILocation(line: 82, column: 1, scope: [[DBG2]])
// SIMD: [[META71]] = !DILocalVariable(name: "argc", arg: 1, scope: [[DBG21]], file: [[META3]], line: 20, type: [[META6]])
// SIMD: [[META72]] = !DILocation(line: 20, column: 13, scope: [[DBG21]])
// SIMD: [[META73]] = !DILocalVariable(name: "argv", arg: 2, scope: [[DBG21]], file: [[META3]], line: 20, type: [[META7]])
// SIMD: [[META74]] = !DILocation(line: 20, column: 26, scope: [[DBG21]])
// SIMD: [[META75]] = !DILocalVariable(name: "b", scope: [[DBG21]], file: [[META3]], line: 21, type: [[META6]])
// SIMD: [[META76]] = !DILocation(line: 21, column: 5, scope: [[DBG21]])
// SIMD: [[DBG77]] = !DILocation(line: 21, column: 9, scope: [[DBG21]])
// SIMD: [[META78]] = !DILocalVariable(name: "c", scope: [[DBG21]], file: [[META3]], line: 21, type: [[META6]])
// SIMD: [[META79]] = !DILocation(line: 21, column: 15, scope: [[DBG21]])
// SIMD: [[META80]] = !DILocalVariable(name: "d", scope: [[DBG21]], file: [[META3]], line: 21, type: [[META6]])
// SIMD: [[META81]] = !DILocation(line: 21, column: 18, scope: [[DBG21]])
// SIMD: [[META82]] = !DILocalVariable(name: "e", scope: [[DBG21]], file: [[META3]], line: 21, type: [[META6]])
// SIMD: [[META83]] = !DILocation(line: 21, column: 21, scope: [[DBG21]])
// SIMD: [[META84]] = !DILocalVariable(name: "f", scope: [[DBG21]], file: [[META3]], line: 21, type: [[META6]])
// SIMD: [[META85]] = !DILocation(line: 21, column: 24, scope: [[DBG21]])
// SIMD: [[META86]] = !DILocalVariable(name: "g", scope: [[DBG21]], file: [[META3]], line: 21, type: [[META6]])
// SIMD: [[META87]] = !DILocation(line: 21, column: 27, scope: [[DBG21]])
// SIMD: [[META88]] = !DILocalVariable(name: "str1", scope: [[DBG21]], file: [[META3]], line: 23, type: [[META15]])
// SIMD: [[META89]] = !DILocation(line: 23, column: 14, scope: [[DBG21]])
// SIMD: [[META90]] = !DILocalVariable(name: "str2", scope: [[DBG21]], file: [[META3]], line: 24, type: [[META53]])
// SIMD: [[META91]] = !DILocation(line: 24, column: 15, scope: [[DBG21]])
// SIMD: [[META92]] = !DILocalVariable(name: "str3", scope: [[DBG21]], file: [[META3]], line: 25, type: [[META56]])
// SIMD: [[META93]] = !DILocation(line: 25, column: 8, scope: [[DBG21]])
// SIMD: [[META94]] = !DILocalVariable(name: "str4", scope: [[DBG21]], file: [[META3]], line: 26, type: [[META8]])
// SIMD: [[META95]] = !DILocation(line: 26, column: 9, scope: [[DBG21]])
// SIMD: [[DBG96]] = !DILocation(line: 26, column: 16, scope: [[DBG21]])
// SIMD: [[META97]] = !DILocalVariable(name: "str5", scope: [[DBG21]], file: [[META3]], line: 27, type: [[META62]])
// SIMD: [[META98]] = !DILocation(line: 27, column: 16, scope: [[DBG21]])
// SIMD: [[DBG99]] = !DILocation(line: 27, column: 23, scope: [[DBG21]])
// SIMD: [[DBG100]] = !DILocation(line: 34, column: 7, scope: [[DBG21]])
// SIMD: [[DBG101]] = !DILocation(line: 34, column: 5, scope: [[DBG21]])
// SIMD: [[DBG102]] = !DILocation(line: 35, column: 3, scope: [[DBG21]])
// SIMD: [[META103]] = !DILocalVariable(name: "b", scope: [[META104:![0-9]+]], file: [[META3]], line: 43, type: [[META6]])
// SIMD: [[META104]] = distinct !DILexicalBlock(scope: [[DBG21]], file: [[META3]], line: 42, column: 3)
// SIMD: [[META105]] = !DILocation(line: 43, column: 9, scope: [[META104]])
// SIMD: [[META106]] = !DILocalVariable(name: "c", scope: [[META104]], file: [[META3]], line: 44, type: [[META6]])
// SIMD: [[META107]] = !DILocation(line: 44, column: 7, scope: [[META104]])
// SIMD: [[DBG108]] = !DILocation(line: 45, column: 9, scope: [[META104]])
// SIMD: [[DBG109]] = !DILocation(line: 45, column: 13, scope: [[META104]])
// SIMD: [[DBG110]] = !DILocation(line: 45, column: 11, scope: [[META104]])
// SIMD: [[DBG111]] = !DILocation(line: 45, column: 7, scope: [[META104]])
// SIMD: [[DBG112]] = !DILocation(line: 53, column: 3, scope: [[DBG21]])
// SIMD: [[DBG113]] = !DILocation(line: 54, column: 1, scope: [[DBG21]])
//.
//CHECK-LABEL: @_Z5tmainIiLi10EEiT_PPc(
//SIMD-LABEL: @_Z5tmainIiLi10EEiT_PPc(
//CHECK: call void @__kmpc_error(ptr @5, i32 2, ptr @.str.2)
//CHECK: call void @__kmpc_error(ptr @7, i32 1, ptr @.str.3)
//CHECK: call void @__kmpc_error(ptr @9, i32 2, ptr @.str)
//SIMD-NOT: call void @__kmpc_error(ptr @5, i32 2, ptr @.str.2)
//SIMD-NOT: call void @__kmpc_error(ptr @7, i32 1, ptr @.str.3)
//SIMD-NOT: call void @__kmpc_error(ptr @9, i32 2, ptr @.str)
//CHECK: ret i32 10

6
clang/test/OpenMP/error_message.cpp
View File

@ -112,12 +112,8 @@ if (1)
// expected-error@+1 {{GPU compiler is needed.}}
#pragma omp error message("GPU compiler is needed.") message("GPU compiler is needed.") // expected-error {{directive '#pragma omp error' cannot contain more than one 'message' clause}}
int a;
// expected-warning@+1 {{expected string in 'clause message' - ignoring}}
#pragma omp error message(a) // expected-error {{ERROR}}
char str[] = "msg";
// expected-warning@+1 {{expected string literal in 'clause message' - ignoring}}
#pragma omp error message(str) // expected-error {{ERROR}}
#pragma omp error at(execution) message(str) // no error
#pragma omp error message(a) // expected-error {{ERROR}}
// expected-error@+1 {{ERROR}}
#pragma omp error message() // expected-error {{expected expression}}
return T();

913
clang/test/OpenMP/nvptx_target_codegen.cpp
View File

File diff suppressed because it is too large Load Diff

760
clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp
View File

@ -1,16 +1,10 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
// Test target codegen - host bc file has to be created first.
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=OMP45_1
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=OMP45_2
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=OMP45_2
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp -fopenmp-version=60 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp -fopenmp-version=60 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefixes=OMP60_1
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp -fopenmp-version=60 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp -fopenmp-version=60 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefixes=OMP60_2
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp -fopenmp-version=60 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefixes=OMP60_2
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
@ -32,13 +26,6 @@ tx ftemplate(int n) {
{
aa += 1;
}
#ifdef OMP60
char str[] = "msg";
#pragma omp target parallel map(tofrom: aa) num_threads(strict: 1024) severity(warning) message(str)
{
aa += 1;
}
#endif
#pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
{
@ -46,15 +33,6 @@ tx ftemplate(int n) {
aa += 1;
b[2] += 1;
}
#ifdef OMP60
const char *str1 = "msg1";
#pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(strict: n) severity(warning) message(str1)
{
a += 1;
aa += 1;
b[2] += 1;
}
#endif
return a;
}
@ -68,675 +46,7 @@ int bar(int n){
}
#endif
// OMP45_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
// OMP45_1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
// OMP45_1-NEXT: entry:
// OMP45_1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
// OMP45_1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// OMP45_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP45_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
// OMP45_1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
// OMP45_1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// OMP45_1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP45_1: user_code.entry:
// OMP45_1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// OMP45_1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// OMP45_1-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 8
// OMP45_1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
// OMP45_1-NEXT: call void @__kmpc_target_deinit()
// OMP45_1-NEXT: ret void
// OMP45_1: worker.exit:
// OMP45_1-NEXT: ret void
//
//
// OMP45_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined
// OMP45_1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
// OMP45_1-NEXT: entry:
// OMP45_1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP45_1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP45_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP45_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
// OMP45_1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// OMP45_1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// OMP45_1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// OMP45_1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
// OMP45_1-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2
// OMP45_1-NEXT: ret void
//
//
// OMP45_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
// OMP45_1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
// OMP45_1-NEXT: entry:
// OMP45_1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// OMP45_1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
// OMP45_1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// OMP45_1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// OMP45_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP45_1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// OMP45_1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// OMP45_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META6]], !align [[META8:![0-9]+]]
// OMP45_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
// OMP45_1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META8]]
// OMP45_1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
// OMP45_1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// OMP45_1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP45_1: user_code.entry:
// OMP45_1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP45_1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP45_1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// OMP45_1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
// OMP45_1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// OMP45_1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
// OMP45_1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
// OMP45_1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
// OMP45_1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
// OMP45_1-NEXT: call void @__kmpc_target_deinit()
// OMP45_1-NEXT: ret void
// OMP45_1: worker.exit:
// OMP45_1-NEXT: ret void
//
//
// OMP45_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined
// OMP45_1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// OMP45_1-NEXT: entry:
// OMP45_1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// OMP45_1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP45_1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP45_1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// OMP45_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP45_1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// OMP45_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META6]], !align [[META8]]
// OMP45_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
// OMP45_1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META8]]
// OMP45_1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// OMP45_1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// OMP45_1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
// OMP45_1-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
// OMP45_1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
// OMP45_1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
// OMP45_1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
// OMP45_1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2
// OMP45_1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2
// OMP45_1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// OMP45_1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
// OMP45_1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// OMP45_1-NEXT: ret void
//
//
// OMP45_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
// OMP45_2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
// OMP45_2-NEXT: entry:
// OMP45_2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
// OMP45_2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// OMP45_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP45_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
// OMP45_2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
// OMP45_2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// OMP45_2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP45_2: user_code.entry:
// OMP45_2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// OMP45_2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// OMP45_2-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 4
// OMP45_2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
// OMP45_2-NEXT: call void @__kmpc_target_deinit()
// OMP45_2-NEXT: ret void
// OMP45_2: worker.exit:
// OMP45_2-NEXT: ret void
//
//
// OMP45_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined
// OMP45_2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
// OMP45_2-NEXT: entry:
// OMP45_2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// OMP45_2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// OMP45_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP45_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
// OMP45_2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// OMP45_2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// OMP45_2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// OMP45_2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
// OMP45_2-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2
// OMP45_2-NEXT: ret void
//
//
// OMP45_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
// OMP45_2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
// OMP45_2-NEXT: entry:
// OMP45_2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// OMP45_2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
// OMP45_2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// OMP45_2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// OMP45_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP45_2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// OMP45_2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP45_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META6]], !align [[META8:![0-9]+]]
// OMP45_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
// OMP45_2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META8]]
// OMP45_2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
// OMP45_2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// OMP45_2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP45_2: user_code.entry:
// OMP45_2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP45_2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP45_2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// OMP45_2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 4
// OMP45_2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// OMP45_2-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4
// OMP45_2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
// OMP45_2-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 4
// OMP45_2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
// OMP45_2-NEXT: call void @__kmpc_target_deinit()
// OMP45_2-NEXT: ret void
// OMP45_2: worker.exit:
// OMP45_2-NEXT: ret void
//
//
// OMP45_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined
// OMP45_2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// OMP45_2-NEXT: entry:
// OMP45_2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// OMP45_2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// OMP45_2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// OMP45_2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// OMP45_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP45_2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// OMP45_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META6]], !align [[META8]]
// OMP45_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
// OMP45_2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META8]]
// OMP45_2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// OMP45_2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// OMP45_2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
// OMP45_2-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
// OMP45_2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
// OMP45_2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
// OMP45_2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
// OMP45_2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2
// OMP45_2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2
// OMP45_2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// OMP45_2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
// OMP45_2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// OMP45_2-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
// OMP60_1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
// OMP60_1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
// OMP60_1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
// OMP60_1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// OMP60_1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_1: user_code.entry:
// OMP60_1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// OMP60_1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// OMP60_1-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 8
// OMP60_1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
// OMP60_1-NEXT: call void @__kmpc_target_deinit()
// OMP60_1-NEXT: ret void
// OMP60_1: worker.exit:
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined
// OMP60_1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// OMP60_1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// OMP60_1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
// OMP60_1-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37
// OMP60_1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
// OMP60_1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR]], align 8, !nonnull [[META8]]
// OMP60_1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
// OMP60_1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_kernel_environment, ptr [[DYN_PTR]])
// OMP60_1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
// OMP60_1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_1: user_code.entry:
// OMP60_1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP60_1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// OMP60_1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8
// OMP60_1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META8]]
// OMP60_1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP5]], i64 0, i64 0
// OMP60_1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1, i32 1, i32 1, ptr [[ARRAYDECAY]])
// OMP60_1-NEXT: call void @__kmpc_target_deinit()
// OMP60_1-NEXT: ret void
// OMP60_1: worker.exit:
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined
// OMP60_1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// OMP60_1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// OMP60_1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
// OMP60_1-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
// OMP60_1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// OMP60_1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
// OMP60_1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// OMP60_1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10:![0-9]+]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
// OMP60_1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// OMP60_1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_1: user_code.entry:
// OMP60_1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP60_1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// OMP60_1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
// OMP60_1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// OMP60_1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
// OMP60_1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
// OMP60_1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
// OMP60_1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
// OMP60_1-NEXT: call void @__kmpc_target_deinit()
// OMP60_1-NEXT: ret void
// OMP60_1: worker.exit:
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined
// OMP60_1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// OMP60_1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// OMP60_1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
// OMP60_1-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
// OMP60_1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
// OMP60_1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
// OMP60_1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2
// OMP60_1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2
// OMP60_1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// OMP60_1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
// OMP60_1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51
// OMP60_1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR4]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// OMP60_1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
// OMP60_1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// OMP60_1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51_kernel_environment, ptr [[DYN_PTR]])
// OMP60_1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// OMP60_1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_1: user_code.entry:
// OMP60_1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP60_1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// OMP60_1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
// OMP60_1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// OMP60_1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
// OMP60_1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
// OMP60_1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
// OMP60_1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
// OMP60_1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 1, i32 1, ptr [[TMP9]])
// OMP60_1-NEXT: call void @__kmpc_target_deinit()
// OMP60_1-NEXT: ret void
// OMP60_1: worker.exit:
// OMP60_1-NEXT: ret void
//
//
// OMP60_1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51_omp_outlined
// OMP60_1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// OMP60_1-NEXT: entry:
// OMP60_1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// OMP60_1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// OMP60_1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// OMP60_1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// OMP60_1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META8]], !align [[META9]]
// OMP60_1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// OMP60_1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// OMP60_1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// OMP60_1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
// OMP60_1-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
// OMP60_1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
// OMP60_1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
// OMP60_1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2
// OMP60_1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2
// OMP60_1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// OMP60_1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
// OMP60_1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// OMP60_1-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
// OMP60_2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
// OMP60_2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]
// OMP60_2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
// OMP60_2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// OMP60_2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_2: user_code.entry:
// OMP60_2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// OMP60_2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// OMP60_2-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 4
// OMP60_2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
// OMP60_2-NEXT: call void @__kmpc_target_deinit()
// OMP60_2-NEXT: ret void
// OMP60_2: worker.exit:
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined
// OMP60_2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// OMP60_2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// OMP60_2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
// OMP60_2-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37
// OMP60_2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[TMP:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
// OMP60_2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4, !nonnull [[META8]]
// OMP60_2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4
// OMP60_2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_kernel_environment, ptr [[DYN_PTR]])
// OMP60_2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
// OMP60_2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_2: user_code.entry:
// OMP60_2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP60_2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// OMP60_2-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4
// OMP60_2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]]
// OMP60_2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP5]], i32 0, i32 0
// OMP60_2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1, i32 1, i32 1, ptr [[ARRAYDECAY]])
// OMP60_2-NEXT: call void @__kmpc_target_deinit()
// OMP60_2-NEXT: ret void
// OMP60_2: worker.exit:
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined
// OMP60_2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// OMP60_2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// OMP60_2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
// OMP60_2-NEXT: store i16 [[CONV1]], ptr [[TMP0]], align 2
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
// OMP60_2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// OMP60_2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
// OMP60_2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// OMP60_2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10:![0-9]+]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
// OMP60_2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// OMP60_2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_2: user_code.entry:
// OMP60_2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP60_2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// OMP60_2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 4
// OMP60_2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// OMP60_2-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4
// OMP60_2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
// OMP60_2-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 4
// OMP60_2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
// OMP60_2-NEXT: call void @__kmpc_target_deinit()
// OMP60_2-NEXT: ret void
// OMP60_2: worker.exit:
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined
// OMP60_2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// OMP60_2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// OMP60_2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
// OMP60_2-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
// OMP60_2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
// OMP60_2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
// OMP60_2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2
// OMP60_2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2
// OMP60_2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// OMP60_2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
// OMP60_2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51
// OMP60_2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR4]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// OMP60_2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
// OMP60_2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// OMP60_2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51_kernel_environment, ptr [[DYN_PTR]])
// OMP60_2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// OMP60_2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// OMP60_2: user_code.entry:
// OMP60_2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// OMP60_2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// OMP60_2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// OMP60_2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 4
// OMP60_2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// OMP60_2-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4
// OMP60_2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
// OMP60_2-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 4
// OMP60_2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
// OMP60_2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 1, i32 1, ptr [[TMP9]])
// OMP60_2-NEXT: call void @__kmpc_target_deinit()
// OMP60_2-NEXT: ret void
// OMP60_2: worker.exit:
// OMP60_2-NEXT: ret void
//
//
// OMP60_2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l51_omp_outlined
// OMP60_2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// OMP60_2-NEXT: entry:
// OMP60_2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// OMP60_2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// OMP60_2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// OMP60_2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// OMP60_2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]
// OMP60_2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// OMP60_2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// OMP60_2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// OMP60_2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
// OMP60_2-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
// OMP60_2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
// OMP60_2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
// OMP60_2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
// OMP60_2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2
// OMP60_2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2
// OMP60_2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// OMP60_2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
// OMP60_2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// OMP60_2-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
@ -744,22 +54,22 @@ int bar(int n){
// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_environment, ptr [[DYN_PTR]])
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 8
// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@ -768,7 +78,7 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
@ -777,7 +87,7 @@ int bar(int n){
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
@ -791,10 +101,10 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META6]], !align [[META8:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META8]]
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK1: user_code.entry:
@ -806,14 +116,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@ -826,9 +136,9 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META6]], !align [[META8]]
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META6]], !align [[META7]]
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META6]], !align [[META8]]
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
@ -844,7 +154,7 @@ int bar(int n){
// CHECK1-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
@ -852,22 +162,22 @@ int bar(int n){
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_kernel_environment, ptr [[DYN_PTR]])
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_kernel_environment, ptr [[DYN_PTR]])
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 4
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l31_omp_outlined
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@ -876,7 +186,7 @@ int bar(int n){
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
@ -885,7 +195,7 @@ int bar(int n){
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
@ -899,10 +209,10 @@ int bar(int n){
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META6]], !align [[META8:![0-9]+]]
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META8]]
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_kernel_environment, ptr [[DYN_PTR]])
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_kernel_environment, ptr [[DYN_PTR]])
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK2: user_code.entry:
@ -914,14 +224,14 @@ int bar(int n){
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 4
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43_omp_outlined
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@ -934,9 +244,9 @@ int bar(int n){
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// CHECK2-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META6]], !align [[META8]]
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4, !nonnull [[META6]], !align [[META7]]
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META6]], !align [[META8]]
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
// CHECK2-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4

214
clang/test/OpenMP/parallel_generic_loop_codegen.cpp
View File

@ -2,16 +2,10 @@
// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp %s
// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp %s
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-OMP60
// Check same results after serialization round-trip
// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH-OMP60
// expected-no-diagnostics
#ifndef HEADER
@ -22,11 +16,7 @@ int foo() {
int x = 0;
int result[N] = {0};
#ifdef OMP60
#pragma omp parallel loop num_threads(strict: N) severity(fatal) message("msg") allocate(x) private(x) collapse(2)
#else
#pragma omp parallel loop num_threads(N) allocate(x) private(x) collapse(2)
#endif
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
result[i] = i + j + x;
@ -64,7 +54,7 @@ int foo() {
// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR]], align 8
// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RESULT_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RESULT_ADDR]], align 8
// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-NEXT: store i32 4095, ptr [[DOTOMP_UB]], align 4
// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@ -133,106 +123,6 @@ int foo() {
// IR-NEXT: ret void
//
//
// IR-OMP60-LABEL: define {{[^@]+}}@_Z3foov
// IR-OMP60-SAME: () #[[ATTR0:[0-9]+]] {
// IR-OMP60-NEXT: entry:
// IR-OMP60-NEXT: [[X:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[RESULT:%.*]] = alloca [64 x i32], align 16
// IR-OMP60-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// IR-OMP60-NEXT: store i32 0, ptr [[X]], align 4
// IR-OMP60-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[RESULT]], i8 0, i64 256, i1 false)
// IR-OMP60-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB2]], i32 [[TMP0]], i32 64, i32 2, ptr @.str)
// IR-OMP60-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z3foov.omp_outlined, ptr [[RESULT]])
// IR-OMP60-NEXT: ret i32 0
//
//
// IR-OMP60-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined
// IR-OMP60-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[RESULT:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-OMP60-NEXT: entry:
// IR-OMP60-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[TMP:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[I:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[J:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR]], align 8
// IR-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RESULT_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// IR-OMP60-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-OMP60-NEXT: store i32 4095, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// IR-OMP60-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// IR-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-OMP60-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
// IR-OMP60-NEXT: [[DOTX__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr null)
// IR-OMP60-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// IR-OMP60-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 4095
// IR-OMP60-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// IR-OMP60: cond.true:
// IR-OMP60-NEXT: br label [[COND_END:%.*]]
// IR-OMP60: cond.false:
// IR-OMP60-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: br label [[COND_END]]
// IR-OMP60: cond.end:
// IR-OMP60-NEXT: [[COND:%.*]] = phi i32 [ 4095, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// IR-OMP60-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// IR-OMP60-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// IR-OMP60: omp.inner.for.cond:
// IR-OMP60-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// IR-OMP60-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// IR-OMP60: omp.inner.for.cond.cleanup:
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// IR-OMP60: omp.inner.for.body:
// IR-OMP60-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 64
// IR-OMP60-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// IR-OMP60-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// IR-OMP60-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// IR-OMP60-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 64
// IR-OMP60-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 64
// IR-OMP60-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
// IR-OMP60-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
// IR-OMP60-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
// IR-OMP60-NEXT: store i32 [[ADD6]], ptr [[J]], align 4
// IR-OMP60-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
// IR-OMP60-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4
// IR-OMP60-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
// IR-OMP60-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTX__VOID_ADDR]], align 4
// IR-OMP60-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP13]]
// IR-OMP60-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4
// IR-OMP60-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
// IR-OMP60-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
// IR-OMP60-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX]], align 4
// IR-OMP60-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-OMP60: omp.body.continue:
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// IR-OMP60: omp.inner.for.inc:
// IR-OMP60-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
// IR-OMP60-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_COND]]
// IR-OMP60: omp.inner.for.end:
// IR-OMP60-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// IR-OMP60: omp.loop.exit:
// IR-OMP60-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
// IR-OMP60-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr null)
// IR-OMP60-NEXT: ret void
//
//
// IR-PCH-LABEL: define {{[^@]+}}@_Z3foov
// IR-PCH-SAME: () #[[ATTR0:[0-9]+]] {
// IR-PCH-NEXT: entry:
@ -264,7 +154,7 @@ int foo() {
// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-PCH-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR]], align 8
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RESULT_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RESULT_ADDR]], align 8
// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-PCH-NEXT: store i32 4095, ptr [[DOTOMP_UB]], align 4
// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@ -332,103 +222,3 @@ int foo() {
// IR-PCH-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr null)
// IR-PCH-NEXT: ret void
//
//
// IR-PCH-OMP60-LABEL: define {{[^@]+}}@_Z3foov
// IR-PCH-OMP60-SAME: () #[[ATTR0:[0-9]+]] {
// IR-PCH-OMP60-NEXT: entry:
// IR-PCH-OMP60-NEXT: [[X:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[RESULT:%.*]] = alloca [64 x i32], align 16
// IR-PCH-OMP60-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// IR-PCH-OMP60-NEXT: store i32 0, ptr [[X]], align 4
// IR-PCH-OMP60-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[RESULT]], i8 0, i64 256, i1 false)
// IR-PCH-OMP60-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB2]], i32 [[TMP0]], i32 64, i32 2, ptr @.str)
// IR-PCH-OMP60-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z3foov.omp_outlined, ptr [[RESULT]])
// IR-PCH-OMP60-NEXT: ret i32 0
//
//
// IR-PCH-OMP60-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined
// IR-PCH-OMP60-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[RESULT:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-PCH-OMP60-NEXT: entry:
// IR-PCH-OMP60-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[TMP:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[I:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[J:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR]], align 8
// IR-PCH-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RESULT_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// IR-PCH-OMP60-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-PCH-OMP60-NEXT: store i32 4095, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// IR-PCH-OMP60-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// IR-PCH-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-PCH-OMP60-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
// IR-PCH-OMP60-NEXT: [[DOTX__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr null)
// IR-PCH-OMP60-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// IR-PCH-OMP60-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 4095
// IR-PCH-OMP60-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// IR-PCH-OMP60: cond.true:
// IR-PCH-OMP60-NEXT: br label [[COND_END:%.*]]
// IR-PCH-OMP60: cond.false:
// IR-PCH-OMP60-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: br label [[COND_END]]
// IR-PCH-OMP60: cond.end:
// IR-PCH-OMP60-NEXT: [[COND:%.*]] = phi i32 [ 4095, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// IR-PCH-OMP60-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// IR-PCH-OMP60-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// IR-PCH-OMP60: omp.inner.for.cond:
// IR-PCH-OMP60-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// IR-PCH-OMP60-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// IR-PCH-OMP60: omp.inner.for.cond.cleanup:
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// IR-PCH-OMP60: omp.inner.for.body:
// IR-PCH-OMP60-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 64
// IR-PCH-OMP60-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// IR-PCH-OMP60-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// IR-PCH-OMP60-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// IR-PCH-OMP60-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 64
// IR-PCH-OMP60-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 64
// IR-PCH-OMP60-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
// IR-PCH-OMP60-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
// IR-PCH-OMP60-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
// IR-PCH-OMP60-NEXT: store i32 [[ADD6]], ptr [[J]], align 4
// IR-PCH-OMP60-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
// IR-PCH-OMP60-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4
// IR-PCH-OMP60-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
// IR-PCH-OMP60-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTX__VOID_ADDR]], align 4
// IR-PCH-OMP60-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP13]]
// IR-PCH-OMP60-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4
// IR-PCH-OMP60-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
// IR-PCH-OMP60-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
// IR-PCH-OMP60-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX]], align 4
// IR-PCH-OMP60-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-PCH-OMP60: omp.body.continue:
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// IR-PCH-OMP60: omp.inner.for.inc:
// IR-PCH-OMP60-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
// IR-PCH-OMP60-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_COND]]
// IR-PCH-OMP60: omp.inner.for.end:
// IR-PCH-OMP60-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// IR-PCH-OMP60: omp.loop.exit:
// IR-PCH-OMP60-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
// IR-PCH-OMP60-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr null)
// IR-PCH-OMP60-NEXT: ret void
//

28
clang/test/OpenMP/parallel_message_messages.cpp
View File

@ -8,9 +8,6 @@ T tmain(T argc, S **argv) {
// Correct usage
#pragma omp parallel message("correct message")
// Template parameter is not yet instantiated.
#pragma omp parallel message(argv[0]) // expected-warning {{expected string in 'clause message' - ignoring}}
// Missing parentheses
#pragma omp parallel message // expected-error {{expected '(' after 'message'}}
@ -18,8 +15,9 @@ T tmain(T argc, S **argv) {
#pragma omp parallel message() // expected-error {{expected expression}}
// Non-string literal
#pragma omp parallel message(123) // expected-warning {{expected string in 'clause message' - ignoring}}
#pragma omp parallel message(argc) // expected-warning {{expected string in 'clause message' - ignoring}}
#pragma omp parallel message(123) // expected-warning {{expected string literal in 'clause message' - ignoring}}
#pragma omp parallel message(argc) // expected-warning {{expected string literal in 'clause message' - ignoring}}
#pragma omp parallel message(argv[0]) // expected-warning {{expected string literal in 'clause message' - ignoring}}
// Multiple arguments
#pragma omp parallel message("msg1", "msg2") // expected-error {{expected ')'}} expected-note {{to match this '('}}
@ -49,10 +47,10 @@ T tmain(T argc, S **argv) {
// Message clause with macro that is not a string
#define NOT_A_STRING 123
#pragma omp parallel message(NOT_A_STRING) // expected-warning {{expected string in 'clause message' - ignoring}}
#pragma omp parallel message(NOT_A_STRING) // expected-warning {{expected string literal in 'clause message' - ignoring}}
// Message clause with template parameter that is not a string
#pragma omp parallel message(N) // expected-warning {{expected string in 'clause message' - ignoring}}
#pragma omp parallel message(N) // expected-warning {{expected string literal in 'clause message' - ignoring}}
// Message clause with macro that is a string
#define A_STRING "macro string"
@ -75,29 +73,15 @@ T tmain(T argc, S **argv) {
return argc;
}
template<int N> int tmain(int argc, char **argv);
int main(int argc, char **argv) {
const char str1[] = "msg";
const char *str2 = "msg";
char str3[] = "msg";
char *str4 = str3;
char * const str5 = str3;
// Correct usage
#pragma omp parallel message("main correct")
#pragma omp parallel message(argv[0])
#pragma omp parallel message(str1)
#pragma omp parallel message(str2)
#pragma omp parallel message(str3)
#pragma omp parallel message(str4)
#pragma omp parallel message(str5)
// Invalid: missing string
#pragma omp parallel message() // expected-error {{expression}}
// Invalid: non-string
#pragma omp parallel message(argc) // expected-warning {{expected string in 'clause message' - ignoring}}
#pragma omp parallel message(argc) // expected-warning {{expected string literal in 'clause message' - ignoring}}
foo();

46
clang/test/OpenMP/parallel_num_threads_codegen.cpp
View File

@ -2,18 +2,9 @@
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp -fopenmp-version=60 -x c++ -triple %itanium_abi_triple -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefixes=CHECK,OMP60 %s
// RUN: %clang_cc1 -DOMP60 -fopenmp -fopenmp-version=60 -x c++ -std=c++11 -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -emit-pch -o %t %s
// RUN: %clang_cc1 -DOMP60 -fopenmp -fopenmp-version=60 -x c++ -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=CHECK,OMP60 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple %itanium_abi_triple -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -DOMP60 -verify -fopenmp-simd -fopenmp-version=60 -x c++ -triple %itanium_abi_triple -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -DOMP60 -fopenmp-simd -fopenmp-version=60 -x c++ -std=c++11 -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -emit-pch -o %t %s
// RUN: %clang_cc1 -DOMP60 -fopenmp-simd -fopenmp-version=60 -x c++ -triple %itanium_abi_triple -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
// expected-no-diagnostics
#ifndef HEADER
@ -41,14 +32,6 @@ int tmain() {
foo();
#pragma omp parallel num_threads(T(23))
foo();
#ifdef OMP60
char str[] = "msg";
const char *str1 = "msg1";
#pragma omp parallel num_threads(strict: C) severity(fatal) message(str)
foo();
#pragma omp parallel num_threads(strict: T(23)) severity(warning) message(str1)
foo();
#endif
return 0;
}
@ -59,14 +42,6 @@ int main() {
foo();
#pragma omp parallel num_threads(a)
foo();
#ifdef OMP60
char str[] = "msg";
const char *str1 = "msg1";
#pragma omp parallel num_threads(strict: 2) severity(fatal) message(str)
foo();
#pragma omp parallel num_threads(strict: a) severity(warning) message(str1)
foo();
#endif
return a + tmain<char, 5>() + tmain<S, 1>();
}
@ -83,13 +58,6 @@ int main() {
// CHECK: [[RES:%.+]] = sext i8 [[A_VAL]] to i32
// CHECK: call {{.*}}void @__kmpc_push_num_threads(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 [[RES]])
// CHECK: call {{.*}}void {{.*}} @__kmpc_fork_call(
// OMP60: [[ARRDECAY:%.+]] = getelementptr inbounds [4 x i8], ptr [[STR:%.+]], i64 0, i64 0
// OMP60: call void @__kmpc_push_num_threads_strict(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 2, i32 2, ptr [[ARRDECAY]])
// OMP60: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(
// OMP60: [[A_VAL1:%.+]] = load i8, ptr [[A_ADDR]]
// OMP60: [[RES1:%.+]] = sext i8 [[A_VAL1]] to i32
// OMP60: call void @__kmpc_push_num_threads_strict(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 [[RES1]], i32 1, ptr [[STR2:%.+]])
// OMP60: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(
// CHECK: invoke{{.*}} [[INT_TY:i[0-9]+]] [[TMAIN_CHAR_5:@.+]]()
// CHECK: invoke{{.*}} [[INT_TY]] [[TMAIN_S_1:@.+]]()
// CHECK: call {{.*}} [[S_TY_DESTR:@.+]](ptr {{[^,]*}} [[S_ADDR]])
@ -102,11 +70,6 @@ int main() {
// CHECK: call {{.*}}void {{.*}} @__kmpc_fork_call(
// CHECK: call {{.*}}void @__kmpc_push_num_threads(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 23)
// CHECK: call {{.*}}void {{.*}} @__kmpc_fork_call(
// OMP60: [[ARRDECAY:%.+]] = getelementptr inbounds [4 x i8], ptr [[STR:%.+]], i64 0, i64 0
// OMP60: call {{.*}}void @__kmpc_push_num_threads_strict(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 5, i32 2, ptr [[ARRDECAY]])
// OMP60: call {{.*}}void {{.*}} @__kmpc_fork_call(
// OMP60: call {{.*}}void @__kmpc_push_num_threads_strict(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 23, i32 1, ptr [[STR1:%.+]])
// OMP60: call {{.*}}void {{.*}} @__kmpc_fork_call(
// CHECK: ret [[INT_TY]] 0
// CHECK-NEXT: }
@ -120,15 +83,6 @@ int main() {
// CHECK: call {{.*}}void @__kmpc_push_num_threads(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 [[RES]])
// CHECK: {{(invoke|call)}} {{.*}} [[S_TY_DESTR]](ptr {{[^,]*}} [[S_TEMP]])
// CHECK: call {{.*}}void {{.*}} @__kmpc_fork_call(
// OMP60: [[ARRDECAY:%.+]] = getelementptr inbounds [4 x i8], ptr [[STR:%.+]], i64 0, i64 0
// OMP60: call {{.*}}void @__kmpc_push_num_threads_strict(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 1, i32 2, ptr [[ARRDECAY]])
// OMP60: call {{.*}}void {{.*}} @__kmpc_fork_call(
// OMP60: {{(invoke|call)}} {{.*}} [[S_TY_CONSTR]](ptr {{[^,]*}} [[S_TEMP:%.+]], [[INTPTR_T_TY]] noundef [[INTPTR_T_TY_ATTR]]23)
// OMP60: [[S_CHAR_OP1:%.+]] = invoke{{.*}} i8 [[S_TY_CHAR_OP]](ptr {{[^,]*}} [[S_TEMP]])
// OMP60: [[RES1:%.+]] = sext {{.*}}i8 [[S_CHAR_OP1]] to i32
// OMP60: call {{.*}}void @__kmpc_push_num_threads_strict(ptr [[DEF_LOC_2]], i32 [[GTID]], i32 [[RES1]], i32 1, ptr [[STR1:%.+]])
// OMP60: {{(invoke|call)}} {{.*}} [[S_TY_DESTR]](ptr {{[^,]*}} [[S_TEMP]])
// OMP60: call {{.*}}void {{.*}} @__kmpc_fork_call(
// CHECK: ret [[INT_TY]] 0
// CHECK: }

436
clang/test/OpenMP/target_parallel_generic_loop_codegen.cpp
View File

@ -10,15 +10,6 @@
// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefixes=IR-GPU-OMP60
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefixes=IR-OMP60
// Check same results after serialization round-trip
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
// RUN: %clang_cc1 -DOMP60 -fopenmp-version=60 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefixes=IR-PCH-OMP60
// expected-no-diagnostics
#ifndef HEADER
@ -43,22 +34,14 @@ int main() {
int x = 0;
int device_result[N] = {0};
#ifdef OMP60
#pragma omp target parallel loop num_threads(strict: N) severity(warning) message("msg") uses_allocators(omp_pteam_mem_alloc) allocate(omp_pteam_mem_alloc: x) private(x) map(from: device_result)
for (int i = 0; i < N; i++) {
x = omp_get_thread_num();
device_result[i] = i + x;
}
#else
#pragma omp target parallel loop num_threads(N) uses_allocators(omp_pteam_mem_alloc) allocate(omp_pteam_mem_alloc: x) private(x) map(from: device_result)
for (int i = 0; i < N; i++) {
x = omp_get_thread_num();
device_result[i] = i + x;
}
#endif
}
#endif
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR0:[0-9]+]] {
// IR-GPU-NEXT: entry:
// IR-GPU-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
@ -72,8 +55,8 @@ int main() {
// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
// IR-GPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53_kernel_environment to ptr), ptr [[DYN_PTR]])
// IR-GPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_kernel_environment to ptr), ptr [[DYN_PTR]])
// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// IR-GPU: user_code.entry:
@ -83,14 +66,14 @@ int main() {
// IR-GPU-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8
// IR-GPU-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP5]], align 8
// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 64, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 2)
// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 64, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 2)
// IR-GPU-NEXT: call void @__kmpc_target_deinit()
// IR-GPU-NEXT: ret void
// IR-GPU: worker.exit:
// IR-GPU-NEXT: ret void
//
//
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53_omp_outlined
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_omp_outlined
// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR1:[0-9]+]] {
// IR-GPU-NEXT: entry:
// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
@ -119,7 +102,7 @@ int main() {
// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]]
// IR-GPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
// IR-GPU-NEXT: store i32 63, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
@ -200,11 +183,11 @@ int main() {
// IR-NEXT: store i32 0, ptr [[X]], align 4
// IR-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[DEVICE_RESULT]], i8 0, i64 256, i1 false)
// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53(ptr [[DEVICE_RESULT]], ptr [[TMP0]]) #[[ATTR3:[0-9]+]]
// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37(ptr [[DEVICE_RESULT]], ptr [[TMP0]]) #[[ATTR3:[0-9]+]]
// IR-NEXT: ret i32 0
//
//
// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53
// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
// IR-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-NEXT: entry:
// IR-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
@ -212,14 +195,14 @@ int main() {
// IR-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// IR-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 64)
// IR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53.omp_outlined, ptr [[TMP1]], ptr [[TMP2]])
// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined, ptr [[TMP1]], ptr [[TMP2]])
// IR-NEXT: ret void
//
//
// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53.omp_outlined
// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined
// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2]] {
// IR-NEXT: entry:
// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@ -237,7 +220,7 @@ int main() {
// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]
// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@ -307,11 +290,11 @@ int main() {
// IR-PCH-NEXT: store i32 0, ptr [[X]], align 4
// IR-PCH-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[DEVICE_RESULT]], i8 0, i64 256, i1 false)
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53(ptr [[DEVICE_RESULT]], ptr [[TMP0]]) #[[ATTR3:[0-9]+]]
// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37(ptr [[DEVICE_RESULT]], ptr [[TMP0]]) #[[ATTR3:[0-9]+]]
// IR-PCH-NEXT: ret i32 0
//
//
// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53
// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
// IR-PCH-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-PCH-NEXT: entry:
// IR-PCH-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
@ -319,14 +302,14 @@ int main() {
// IR-PCH-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// IR-PCH-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-PCH-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-PCH-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 64)
// IR-PCH-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53.omp_outlined, ptr [[TMP1]], ptr [[TMP2]])
// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined, ptr [[TMP1]], ptr [[TMP2]])
// IR-PCH-NEXT: ret void
//
//
// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l53.omp_outlined
// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined
// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2]] {
// IR-PCH-NEXT: entry:
// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@ -344,7 +327,7 @@ int main() {
// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-PCH-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-PCH-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-PCH-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@ -405,386 +388,3 @@ int main() {
// IR-PCH-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr [[TMP14]])
// IR-PCH-NEXT: ret void
//
//
// IR-GPU-OMP60-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47
// IR-GPU-OMP60-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
// IR-GPU-OMP60-NEXT: entry:
// IR-GPU-OMP60-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[TMP:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[DEVICE_RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DEVICE_RESULT_ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OMP_PTEAM_MEM_ALLOC_ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTCAPTURE_EXPR__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR__ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
// IR-GPU-OMP60-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr
// IR-GPU-OMP60-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: store ptr [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]
// IR-GPU-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR_ASCAST]], align 8, !nonnull [[META6]]
// IR-GPU-OMP60-NEXT: store ptr [[TMP1]], ptr [[TMP_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47_kernel_environment to ptr), ptr [[DYN_PTR]])
// IR-GPU-OMP60-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
// IR-GPU-OMP60-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// IR-GPU-OMP60: user_code.entry:
// IR-GPU-OMP60-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr))
// IR-GPU-OMP60-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
// IR-GPU-OMP60-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8
// IR-GPU-OMP60-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
// IR-GPU-OMP60-NEXT: store ptr [[TMP4]], ptr [[TMP6]], align 8
// IR-GPU-OMP60-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP_ASCAST]], align 8, !nonnull [[META6]]
// IR-GPU-OMP60-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP7]], i64 0, i64 0
// IR-GPU-OMP60-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP3]], i32 1, i32 64, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 2, i32 1, i32 1, ptr [[ARRAYDECAY]])
// IR-GPU-OMP60-NEXT: call void @__kmpc_target_deinit()
// IR-GPU-OMP60-NEXT: ret void
// IR-GPU-OMP60: worker.exit:
// IR-GPU-OMP60-NEXT: ret void
//
//
// IR-GPU-OMP60-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47_omp_outlined
// IR-GPU-OMP60-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR1:[0-9]+]] {
// IR-GPU-OMP60-NEXT: entry:
// IR-GPU-OMP60-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-OMP60-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[DEVICE_RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DEVICE_RESULT_ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OMP_PTEAM_MEM_ALLOC_ADDR]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr
// IR-GPU-OMP60-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
// IR-GPU-OMP60-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
// IR-GPU-OMP60-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
// IR-GPU-OMP60-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]]
// IR-GPU-OMP60-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: store i32 63, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-OMP60-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
// IR-GPU-OMP60-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP2]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
// IR-GPU-OMP60-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// IR-GPU-OMP60: omp.dispatch.cond:
// IR-GPU-OMP60-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 63
// IR-GPU-OMP60-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// IR-GPU-OMP60: cond.true:
// IR-GPU-OMP60-NEXT: br label [[COND_END:%.*]]
// IR-GPU-OMP60: cond.false:
// IR-GPU-OMP60-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: br label [[COND_END]]
// IR-GPU-OMP60: cond.end:
// IR-GPU-OMP60-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
// IR-GPU-OMP60-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// IR-GPU-OMP60-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
// IR-GPU-OMP60: omp.dispatch.body:
// IR-GPU-OMP60-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// IR-GPU-OMP60: omp.inner.for.cond:
// IR-GPU-OMP60-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// IR-GPU-OMP60-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// IR-GPU-OMP60: omp.inner.for.body:
// IR-GPU-OMP60-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// IR-GPU-OMP60-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// IR-GPU-OMP60-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[CALL:%.*]] = call noundef i32 @_Z18omp_get_thread_numv() #[[ATTR5:[0-9]+]]
// IR-GPU-OMP60-NEXT: store i32 [[CALL]], ptr addrspacecast (ptr addrspace(3) @x to ptr), align 4
// IR-GPU-OMP60-NEXT: [[TMP11:%.*]] = load i32, ptr [[I_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP12:%.*]] = load i32, ptr addrspacecast (ptr addrspace(3) @x to ptr), align 4
// IR-GPU-OMP60-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
// IR-GPU-OMP60-NEXT: [[TMP13:%.*]] = load i32, ptr [[I_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
// IR-GPU-OMP60-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
// IR-GPU-OMP60-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// IR-GPU-OMP60-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-GPU-OMP60: omp.body.continue:
// IR-GPU-OMP60-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// IR-GPU-OMP60: omp.inner.for.inc:
// IR-GPU-OMP60-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
// IR-GPU-OMP60-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: br label [[OMP_INNER_FOR_COND]]
// IR-GPU-OMP60: omp.inner.for.end:
// IR-GPU-OMP60-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// IR-GPU-OMP60: omp.dispatch.inc:
// IR-GPU-OMP60-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
// IR-GPU-OMP60-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_LB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
// IR-GPU-OMP60-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_UB_ASCAST]], align 4
// IR-GPU-OMP60-NEXT: br label [[OMP_DISPATCH_COND]]
// IR-GPU-OMP60: omp.dispatch.end:
// IR-GPU-OMP60-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]])
// IR-GPU-OMP60-NEXT: ret void
//
//
// IR-OMP60-LABEL: define {{[^@]+}}@main
// IR-OMP60-SAME: () #[[ATTR0:[0-9]+]] {
// IR-OMP60-NEXT: entry:
// IR-OMP60-NEXT: [[X:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DEVICE_RESULT:%.*]] = alloca [64 x i32], align 16
// IR-OMP60-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: store i32 0, ptr [[X]], align 4
// IR-OMP60-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[DEVICE_RESULT]], i8 0, i64 256, i1 false)
// IR-OMP60-NEXT: store ptr @.str, ptr [[DOTCAPTURE_EXPR_]], align 8
// IR-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8, !nonnull [[META3:![0-9]+]]
// IR-OMP60-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
// IR-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-OMP60-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]]
// IR-OMP60-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47(ptr [[DEVICE_RESULT]], ptr [[TMP1]], ptr [[TMP2]]) #[[ATTR3:[0-9]+]]
// IR-OMP60-NEXT: ret i32 0
//
//
// IR-OMP60-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47
// IR-OMP60-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-OMP60-NEXT: entry:
// IR-OMP60-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// IR-OMP60-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// IR-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3]], !align [[META4:![0-9]+]]
// IR-OMP60-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR]], align 8, !nonnull [[META3]]
// IR-OMP60-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
// IR-OMP60-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]]
// IR-OMP60-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP3]], i64 0, i64 0
// IR-OMP60-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB2]], i32 [[TMP0]], i32 64, i32 1, ptr [[ARRAYDECAY]])
// IR-OMP60-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-OMP60-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47.omp_outlined, ptr [[TMP1]], ptr [[TMP4]])
// IR-OMP60-NEXT: ret void
//
//
// IR-OMP60-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47.omp_outlined
// IR-OMP60-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2]] {
// IR-OMP60-NEXT: entry:
// IR-OMP60-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
// IR-OMP60-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[TMP:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: [[I:%.*]] = alloca i32, align 4
// IR-OMP60-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-OMP60-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]
// IR-OMP60-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-OMP60-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// IR-OMP60-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// IR-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-OMP60-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
// IR-OMP60-NEXT: [[TMP3:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-OMP60-NEXT: [[DOTX__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr [[TMP3]])
// IR-OMP60-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// IR-OMP60-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 63
// IR-OMP60-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// IR-OMP60: cond.true:
// IR-OMP60-NEXT: br label [[COND_END:%.*]]
// IR-OMP60: cond.false:
// IR-OMP60-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: br label [[COND_END]]
// IR-OMP60: cond.end:
// IR-OMP60-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
// IR-OMP60-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// IR-OMP60-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// IR-OMP60: omp.inner.for.cond:
// IR-OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-OMP60-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// IR-OMP60-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// IR-OMP60: omp.inner.for.cond.cleanup:
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// IR-OMP60: omp.inner.for.body:
// IR-OMP60-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// IR-OMP60-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// IR-OMP60-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// IR-OMP60-NEXT: [[CALL:%.*]] = call noundef i32 @_Z18omp_get_thread_numv()
// IR-OMP60-NEXT: store i32 [[CALL]], ptr [[DOTX__VOID_ADDR]], align 4
// IR-OMP60-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
// IR-OMP60-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTX__VOID_ADDR]], align 4
// IR-OMP60-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
// IR-OMP60-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4
// IR-OMP60-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
// IR-OMP60-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
// IR-OMP60-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4
// IR-OMP60-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-OMP60: omp.body.continue:
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// IR-OMP60: omp.inner.for.inc:
// IR-OMP60-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1
// IR-OMP60-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
// IR-OMP60-NEXT: br label [[OMP_INNER_FOR_COND]]
// IR-OMP60: omp.inner.for.end:
// IR-OMP60-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// IR-OMP60: omp.loop.exit:
// IR-OMP60-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
// IR-OMP60-NEXT: [[TMP14:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-OMP60-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr [[TMP14]])
// IR-OMP60-NEXT: ret void
//
//
// IR-PCH-OMP60-LABEL: define {{[^@]+}}@main
// IR-PCH-OMP60-SAME: () #[[ATTR0:[0-9]+]] {
// IR-PCH-OMP60-NEXT: entry:
// IR-PCH-OMP60-NEXT: [[X:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DEVICE_RESULT:%.*]] = alloca [64 x i32], align 16
// IR-PCH-OMP60-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: store i32 0, ptr [[X]], align 4
// IR-PCH-OMP60-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[DEVICE_RESULT]], i8 0, i64 256, i1 false)
// IR-PCH-OMP60-NEXT: store ptr @.str, ptr [[DOTCAPTURE_EXPR_]], align 8
// IR-PCH-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8, !nonnull [[META3:![0-9]+]]
// IR-PCH-OMP60-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
// IR-PCH-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-PCH-OMP60-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]]
// IR-PCH-OMP60-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47(ptr [[DEVICE_RESULT]], ptr [[TMP1]], ptr [[TMP2]]) #[[ATTR3:[0-9]+]]
// IR-PCH-OMP60-NEXT: ret i32 0
//
//
// IR-PCH-OMP60-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47
// IR-PCH-OMP60-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]], ptr noundef nonnull align 1 dereferenceable(4) [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-PCH-OMP60-NEXT: entry:
// IR-PCH-OMP60-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// IR-PCH-OMP60-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// IR-PCH-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3]], !align [[META4:![0-9]+]]
// IR-PCH-OMP60-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR__ADDR]], align 8, !nonnull [[META3]]
// IR-PCH-OMP60-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
// IR-PCH-OMP60-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]]
// IR-PCH-OMP60-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP3]], i64 0, i64 0
// IR-PCH-OMP60-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB2]], i32 [[TMP0]], i32 64, i32 1, ptr [[ARRAYDECAY]])
// IR-PCH-OMP60-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-PCH-OMP60-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47.omp_outlined, ptr [[TMP1]], ptr [[TMP4]])
// IR-PCH-OMP60-NEXT: ret void
//
//
// IR-PCH-OMP60-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47.omp_outlined
// IR-PCH-OMP60-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2]] {
// IR-PCH-OMP60-NEXT: entry:
// IR-PCH-OMP60-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
// IR-PCH-OMP60-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[TMP:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: [[I:%.*]] = alloca i32, align 4
// IR-PCH-OMP60-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
// IR-PCH-OMP60-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
// IR-PCH-OMP60-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]
// IR-PCH-OMP60-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// IR-PCH-OMP60-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// IR-PCH-OMP60-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// IR-PCH-OMP60-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// IR-PCH-OMP60-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
// IR-PCH-OMP60-NEXT: [[TMP3:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-PCH-OMP60-NEXT: [[DOTX__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr [[TMP3]])
// IR-PCH-OMP60-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// IR-PCH-OMP60-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 63
// IR-PCH-OMP60-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// IR-PCH-OMP60: cond.true:
// IR-PCH-OMP60-NEXT: br label [[COND_END:%.*]]
// IR-PCH-OMP60: cond.false:
// IR-PCH-OMP60-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: br label [[COND_END]]
// IR-PCH-OMP60: cond.end:
// IR-PCH-OMP60-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
// IR-PCH-OMP60-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// IR-PCH-OMP60-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// IR-PCH-OMP60: omp.inner.for.cond:
// IR-PCH-OMP60-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// IR-PCH-OMP60-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// IR-PCH-OMP60-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
// IR-PCH-OMP60: omp.inner.for.cond.cleanup:
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
// IR-PCH-OMP60: omp.inner.for.body:
// IR-PCH-OMP60-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// IR-PCH-OMP60-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// IR-PCH-OMP60-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// IR-PCH-OMP60-NEXT: [[CALL:%.*]] = call noundef i32 @_Z18omp_get_thread_numv()
// IR-PCH-OMP60-NEXT: store i32 [[CALL]], ptr [[DOTX__VOID_ADDR]], align 4
// IR-PCH-OMP60-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
// IR-PCH-OMP60-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTX__VOID_ADDR]], align 4
// IR-PCH-OMP60-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
// IR-PCH-OMP60-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4
// IR-PCH-OMP60-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
// IR-PCH-OMP60-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
// IR-PCH-OMP60-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4
// IR-PCH-OMP60-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-PCH-OMP60: omp.body.continue:
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// IR-PCH-OMP60: omp.inner.for.inc:
// IR-PCH-OMP60-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1
// IR-PCH-OMP60-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
// IR-PCH-OMP60-NEXT: br label [[OMP_INNER_FOR_COND]]
// IR-PCH-OMP60: omp.inner.for.end:
// IR-PCH-OMP60-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// IR-PCH-OMP60: omp.loop.exit:
// IR-PCH-OMP60-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
// IR-PCH-OMP60-NEXT: [[TMP14:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
// IR-PCH-OMP60-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr [[TMP14]])
// IR-PCH-OMP60-NEXT: ret void
//

106
clang/test/OpenMP/target_parallel_num_threads_messages.cpp
View File

@ -1,8 +1,6 @@
// RUN: %clang_cc1 -verify -fopenmp -ferror-limit 100 %s -Wuninitialized
// RUN: %clang_cc1 -verify -fopenmp-simd -ferror-limit 100 %s -Wuninitialized
// RUN: %clang_cc1 -DOMP60 -verify=expected,omp60 -fopenmp -fopenmp-version=60 -ferror-limit 100 %s -Wuninitialized
// RUN: %clang_cc1 -DOMP60 -verify=expected,omp60 -fopenmp-simd -fopenmp-version=60 -ferror-limit 100 %s -Wuninitialized
// RUN: %clang_cc1 -verify -fopenmp-simd -ferror-limit 100 %s -Wuninitialized
void foo() {
}
@ -11,11 +9,11 @@ bool foobool(int argc) {
return argc;
}
struct S1; // expected-note {{declared here}} omp60-note {{declared here}}
struct S1; // expected-note {{declared here}}
#define redef_num_threads(a, b) num_threads(a)
template <class T, typename S, int N> // expected-note {{declared here}} omp60-note {{declared here}}
template <class T, typename S, int N> // expected-note {{declared here}}
T tmain(T argc, S **argv) {
T z;
#pragma omp target parallel num_threads // expected-error {{expected '(' after 'num_threads'}}
@ -43,56 +41,6 @@ T tmain(T argc, S **argv) {
#pragma omp target parallel redef_num_threads (argc, argc)
foo();
#ifdef OMP60
// Valid uses of strict modifier
#pragma omp target parallel num_threads(strict: 4)
foo();
#pragma omp target parallel num_threads(strict: argc+z)
foo();
// Invalid: missing expression after strict:
#pragma omp target parallel num_threads(strict: ) // omp60-error {{expected expression}}
foo();
#pragma omp target parallel num_threads(strict:) // omp60-error {{expected expression}}
foo();
#pragma omp target parallel num_threads(strict: // omp60-error {{expected expression}} omp60-error {{expected ')'}} omp60-note {{to match this '('}}
foo();
// Invalid: unknown/missing modifier
#pragma omp target parallel num_threads(foo: 4) // omp60-error {{expected 'strict' in OpenMP clause 'num_threads'}}
foo();
#pragma omp target parallel num_threads(: 4) // omp60-error {{expected expression}} omp60-error {{expected ')'}} omp60-note {{to match this '('}}
foo();
#pragma omp target parallel num_threads(:)// omp60-error {{expected expression}} omp60-error {{expected ')'}} omp60-note {{to match this '('}}
foo();
// Invalid: missing colon after modifier
#pragma omp target parallel num_threads(strict 4) // omp60-error {{missing ':' after strict modifier}}
foo();
// Invalid: negative, zero, or non-integral
#pragma omp target parallel num_threads(strict: -1) // omp60-error {{argument to 'num_threads' clause must be a strictly positive integer value}}
foo();
#pragma omp target parallel num_threads(strict: 0) // omp60-error {{argument to 'num_threads' clause must be a strictly positive integer value}}
foo();
#pragma omp target parallel num_threads(strict: (argc > 0) ? argv[1] : argv[2]) // omp60-error 2 {{expression must have integral or unscoped enumeration type, not 'char *'}}
foo();
#pragma omp target parallel num_threads(strict: S) // omp60-error {{'S' does not refer to a value}}
foo();
#pragma omp target parallel num_threads(strict: argv[1]=2) // omp60-error {{expected ')'}} omp60-note {{to match this '('}} omp60-error 2 {{expression must have integral or unscoped enumeration type, not 'char *'}}
foo();
#pragma omp target parallel num_threads(strict: N) // omp60-error {{argument to 'num_threads' clause must be a strictly positive integer value}}
foo();
// Invalid: multiple strict modifiers or mixed with non-strict
#pragma omp target parallel num_threads(strict: 4, strict: 5) // omp60-error {{expected ')'}} expected-note {{to match this '('}}
foo();
#pragma omp target parallel num_threads(strict: 4), num_threads(5) // omp60-error {{directive '#pragma omp target parallel' cannot contain more than one 'num_threads' clause}}
foo();
#pragma omp target parallel num_threads(4), num_threads(strict: 5) // omp60-error {{directive '#pragma omp target parallel' cannot contain more than one 'num_threads' clause}}
foo();
#endif // OMP60
return argc;
}
@ -121,53 +69,5 @@ int main(int argc, char **argv) {
#pragma omp target parallel redef_num_threads (argc, argc)
foo();
#ifdef OMP60
// Valid uses of strict modifier
#pragma omp target parallel num_threads(strict: 4)
foo();
#pragma omp target parallel num_threads(strict: argc+z)
foo();
// Invalid: missing expression after strict:
#pragma omp target parallel num_threads(strict: ) // omp60-error {{expected expression}}
foo();
#pragma omp target parallel num_threads(strict:) // omp60-error {{expected expression}}
foo();
#pragma omp target parallel num_threads(strict: // omp60-error {{expected expression}} omp60-error {{expected ')'}} omp60-note {{to match this '('}}
foo();
// Invalid: unknown/missing modifier
#pragma omp target parallel num_threads(foo: 4) // omp60-error {{expected 'strict' in OpenMP clause 'num_threads'}}
foo();
#pragma omp target parallel num_threads(: 4) // omp60-error {{expected expression}} omp60-error {{expected ')'}} omp60-note {{to match this '('}}
foo();
#pragma omp target parallel num_threads(:) // omp60-error {{expected expression}} omp60-error {{expected ')'}} omp60-note {{to match this '('}}
foo();
// Invalid: missing colon after modifier
#pragma omp target parallel num_threads(strict 4) // omp60-error {{missing ':' after strict modifier}}
foo();
// Invalid: negative, zero, or non-integral
#pragma omp target parallel num_threads(strict: -1) // omp60-error {{argument to 'num_threads' clause must be a strictly positive integer value}}
foo();
#pragma omp target parallel num_threads(strict: 0) // omp60-error {{argument to 'num_threads' clause must be a strictly positive integer value}}
foo();
#pragma omp target parallel num_threads(strict: (argc > 0) ? argv[1] : argv[2]) // omp60-error {{expression must have integral or unscoped enumeration type, not 'char *'}}
foo();
#pragma omp target parallel num_threads(strict: S1) // omp60-error {{'S1' does not refer to a value}}
foo();
#pragma omp target parallel num_threads(strict: argv[1]=2) // omp60-error {{expected ')'}} omp60-note {{to match this '('}} omp60-error {{expression must have integral or unscoped enumeration type, not 'char *'}}
foo();
// Invalid: multiple strict modifiers or mixed with non-strict
#pragma omp target parallel num_threads(strict: 4, strict: 5) // omp60-error {{expected ')'}} expected-note {{to match this '('}}
foo();
#pragma omp target parallel num_threads(strict: 4), num_threads(5) // omp60-error {{directive '#pragma omp target parallel' cannot contain more than one 'num_threads' clause}}
foo();
#pragma omp target parallel num_threads(4), num_threads(strict: 5) // omp60-error {{directive '#pragma omp target parallel' cannot contain more than one 'num_threads' clause}}
foo();
#endif // OMP60
return tmain<int, char, 3>(argc, argv); // expected-note {{in instantiation of function template specialization 'tmain<int, char, 3>' requested here}}
}

2956
clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
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File diff suppressed because it is too large Load Diff

1447
clang/test/OpenMP/teams_distribute_parallel_for_num_threads_strict_codegen.cpp
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File diff suppressed because it is too large Load Diff

1911
clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_strict_codegen.cpp
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File diff suppressed because it is too large Load Diff

68
llvm/include/llvm/Frontend/OpenMP/OMP.td
View File

@ -968,9 +968,9 @@ def OMP_Parallel : Directive<[Spelling<"parallel">]> {
];
let allowedOnceClauses = [VersionedClause<OMPC_Default>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_Severity, 60>,
];
let association = AS_Block;
@ -1358,12 +1358,10 @@ def OMP_DistributeParallelDo : Directive<[Spelling<"distribute parallel do">]> {
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_DistSchedule>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Distribute, OMP_Parallel, OMP_Do];
let category = CA_Executable;
@ -1382,7 +1380,6 @@ def OMP_DistributeParallelDoSimd
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
@ -1391,7 +1388,6 @@ def OMP_DistributeParallelDoSimd
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
];
@ -1410,7 +1406,6 @@ def OMP_DistributeParallelFor
VersionedClause<OMPC_FirstPrivate>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
VersionedClause<OMPC_Order, 50>,
@ -1418,7 +1413,6 @@ def OMP_DistributeParallelFor
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
];
let leafConstructs = [OMP_Distribute, OMP_Parallel, OMP_For];
@ -1438,7 +1432,6 @@ def OMP_DistributeParallelForSimd
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
@ -1448,7 +1441,6 @@ def OMP_DistributeParallelForSimd
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
];
@ -1473,13 +1465,11 @@ def OMP_DistributeSimd : Directive<[Spelling<"distribute simd">]> {
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_DistSchedule>,
VersionedClause<OMPC_If, 50>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_SimdLen>,
];
let leafConstructs = [OMP_Distribute, OMP_Simd];
@ -1690,13 +1680,11 @@ def OMP_ParallelDo : Directive<[Spelling<"parallel do">]> {
let allowedOnceClauses = [
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_Ordered>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Parallel, OMP_Do];
let category = CA_Executable;
@ -1719,7 +1707,6 @@ def OMP_ParallelDoSimd : Directive<[Spelling<"parallel do simd">]> {
];
let allowedOnceClauses = [
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_Ordered>,
@ -1727,7 +1714,6 @@ def OMP_ParallelDoSimd : Directive<[Spelling<"parallel do simd">]> {
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Parallel, OMP_Do, OMP_Simd];
let category = CA_Executable;
@ -1743,7 +1729,6 @@ def OMP_ParallelFor : Directive<[Spelling<"parallel for">]> {
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
VersionedClause<OMPC_Order, 50>,
@ -1752,7 +1737,6 @@ def OMP_ParallelFor : Directive<[Spelling<"parallel for">]> {
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
];
let leafConstructs = [OMP_Parallel, OMP_For];
@ -1770,7 +1754,6 @@ def OMP_ParallelForSimd : Directive<[Spelling<"parallel for simd">]> {
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
@ -1781,7 +1764,6 @@ def OMP_ParallelForSimd : Directive<[Spelling<"parallel for simd">]> {
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
];
@ -1805,11 +1787,9 @@ def OMP_parallel_loop : Directive<[Spelling<"parallel loop">]> {
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_Default>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Parallel, OMP_loop];
let category = CA_Executable;
@ -1822,13 +1802,11 @@ def OMP_ParallelMasked : Directive<[Spelling<"parallel masked">]> {
VersionedClause<OMPC_Filter>,
VersionedClause<OMPC_FirstPrivate>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
VersionedClause<OMPC_Private>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
];
let leafConstructs = [OMP_Parallel, OMP_masked];
@ -1848,7 +1826,6 @@ def OMP_ParallelMaskedTaskloop
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Mergeable>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoGroup>,
VersionedClause<OMPC_NumTasks>,
VersionedClause<OMPC_NumThreads>,
@ -1857,7 +1834,6 @@ def OMP_ParallelMaskedTaskloop
VersionedClause<OMPC_Private>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_Untied>,
];
@ -1880,7 +1856,6 @@ def OMP_ParallelMaskedTaskloopSimd
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Mergeable>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoGroup>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NumTasks>,
@ -1892,7 +1867,6 @@ def OMP_ParallelMaskedTaskloopSimd
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_Untied>,
@ -1907,13 +1881,11 @@ def OMP_ParallelMaster : Directive<[Spelling<"parallel master">]> {
VersionedClause<OMPC_Default>,
VersionedClause<OMPC_FirstPrivate>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
VersionedClause<OMPC_Private>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
];
let leafConstructs = [OMP_Parallel, OMP_Master];
@ -1932,7 +1904,6 @@ def OMP_ParallelMasterTaskloop
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Mergeable>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoGroup>,
VersionedClause<OMPC_NumTasks>,
VersionedClause<OMPC_NumThreads>,
@ -1941,7 +1912,6 @@ def OMP_ParallelMasterTaskloop
VersionedClause<OMPC_Private>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_Untied>,
];
@ -1963,7 +1933,6 @@ def OMP_ParallelMasterTaskloopSimd
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Mergeable>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoGroup>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NumTasks>,
@ -1975,7 +1944,6 @@ def OMP_ParallelMasterTaskloopSimd
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_Untied>,
@ -1998,9 +1966,7 @@ def OMP_ParallelSections : Directive<[Spelling<"parallel sections">]> {
];
let allowedOnceClauses = [
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Parallel, OMP_Sections];
let category = CA_Executable;
@ -2017,10 +1983,8 @@ def OMP_ParallelWorkshare : Directive<[Spelling<"parallel workshare">]> {
];
let allowedOnceClauses = [
VersionedClause<OMPC_If>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Parallel, OMP_Workshare];
let category = CA_Executable;
@ -2047,11 +2011,9 @@ def OMP_TargetParallel : Directive<[Spelling<"target parallel">]> {
let allowedOnceClauses = [
VersionedClause<OMPC_DefaultMap>,
VersionedClause<OMPC_Device>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_DynCGroupMem>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_ThreadLimit, 51>,
];
let leafConstructs = [OMP_Target, OMP_Parallel];
@ -2079,14 +2041,12 @@ def OMP_TargetParallelDo : Directive<[Spelling<"target parallel do">]> {
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_DefaultMap>,
VersionedClause<OMPC_Device>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_Ordered>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
];
let leafConstructs = [OMP_Target, OMP_Parallel, OMP_Do];
let category = CA_Executable;
@ -2110,7 +2070,6 @@ def OMP_TargetParallelDoSimd
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Map>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumThreads>,
@ -2121,7 +2080,6 @@ def OMP_TargetParallelDoSimd
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_UsesAllocators>,
@ -2146,7 +2104,6 @@ def OMP_TargetParallelFor : Directive<[Spelling<"target parallel for">]> {
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Map>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
@ -2156,7 +2113,6 @@ def OMP_TargetParallelFor : Directive<[Spelling<"target parallel for">]> {
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_UsesAllocators, 50>,
];
@ -2186,7 +2142,6 @@ def OMP_TargetParallelForSimd
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Map>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumThreads>,
@ -2198,7 +2153,6 @@ def OMP_TargetParallelForSimd
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_UsesAllocators, 50>,
@ -2234,13 +2188,11 @@ def OMP_target_parallel_loop : Directive<[Spelling<"target parallel loop">]> {
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_Default>,
VersionedClause<OMPC_DefaultMap>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_DynCGroupMem>,
VersionedClause<OMPC_Order>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_ThreadLimit, 51>,
];
let leafConstructs = [OMP_Target, OMP_Parallel, OMP_loop];
@ -2271,14 +2223,12 @@ def OMP_TargetSimd : Directive<[Spelling<"target simd">]> {
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_DefaultMap>,
VersionedClause<OMPC_Device>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_DynCGroupMem>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_ThreadLimit, 51>,
];
@ -2371,14 +2321,12 @@ def OMP_TargetTeamsDistributeParallelDo
VersionedClause<OMPC_DefaultMap>,
VersionedClause<OMPC_Device>,
VersionedClause<OMPC_DistSchedule>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_ThreadLimit>,
];
let leafConstructs =
@ -2412,7 +2360,6 @@ def OMP_TargetTeamsDistributeParallelDoSimd
VersionedClause<OMPC_DefaultMap>,
VersionedClause<OMPC_Device>,
VersionedClause<OMPC_DistSchedule>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
@ -2420,7 +2367,6 @@ def OMP_TargetTeamsDistributeParallelDoSimd
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_ThreadLimit>,
];
@ -2446,7 +2392,6 @@ def OMP_TargetTeamsDistributeParallelFor
VersionedClause<OMPC_IsDevicePtr>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Map>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
@ -2456,7 +2401,6 @@ def OMP_TargetTeamsDistributeParallelFor
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_ThreadLimit>,
VersionedClause<OMPC_UsesAllocators, 50>,
@ -2488,7 +2432,6 @@ def OMP_TargetTeamsDistributeParallelForSimd
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Map>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NoWait>,
VersionedClause<OMPC_NumTeams>,
@ -2500,7 +2443,6 @@ def OMP_TargetTeamsDistributeParallelForSimd
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_ThreadLimit>,
@ -2687,13 +2629,11 @@ def OMP_TeamsDistributeParallelDo
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_Default>,
VersionedClause<OMPC_DistSchedule>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_ThreadLimit>,
];
let leafConstructs = [OMP_Teams, OMP_Distribute, OMP_Parallel, OMP_Do];
@ -2719,14 +2659,12 @@ def OMP_TeamsDistributeParallelDoSimd
VersionedClause<OMPC_Collapse>,
VersionedClause<OMPC_Default>,
VersionedClause<OMPC_DistSchedule>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_Order, 50>,
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_ThreadLimit>,
];
@ -2747,7 +2685,6 @@ def OMP_TeamsDistributeParallelFor
VersionedClause<OMPC_FirstPrivate>,
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
VersionedClause<OMPC_OMPX_Attribute>,
@ -2756,7 +2693,6 @@ def OMP_TeamsDistributeParallelFor
VersionedClause<OMPC_ProcBind>,
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_ThreadLimit>,
];
@ -2777,7 +2713,6 @@ def OMP_TeamsDistributeParallelForSimd
VersionedClause<OMPC_If>,
VersionedClause<OMPC_LastPrivate>,
VersionedClause<OMPC_Linear>,
VersionedClause<OMPC_Message, 60>,
VersionedClause<OMPC_NonTemporal, 50>,
VersionedClause<OMPC_NumTeams>,
VersionedClause<OMPC_NumThreads>,
@ -2788,7 +2723,6 @@ def OMP_TeamsDistributeParallelForSimd
VersionedClause<OMPC_Reduction>,
VersionedClause<OMPC_SafeLen>,
VersionedClause<OMPC_Schedule>,
VersionedClause<OMPC_Severity, 60>,
VersionedClause<OMPC_Shared>,
VersionedClause<OMPC_SimdLen>,
VersionedClause<OMPC_ThreadLimit>,

12
llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
View File

@ -217,8 +217,6 @@ __OMP_RTL(__kmpc_omp_taskwait, false, Int32, IdentPtr, Int32)
__OMP_RTL(__kmpc_omp_taskyield, false, Int32, IdentPtr, Int32, /* Int */ Int32)
__OMP_RTL(__kmpc_push_num_threads, false, Void, IdentPtr, Int32,
/* Int */ Int32)
__OMP_RTL(__kmpc_push_num_threads_strict, false, Void, IdentPtr, Int32,
/* Int */ Int32, /* Int */ Int32, /* const char* */ Int8Ptr)
__OMP_RTL(__kmpc_push_proc_bind, false, Void, IdentPtr, Int32, /* Int */ Int32)
__OMP_RTL(__kmpc_omp_reg_task_with_affinity, false, Int32, IdentPtr, Int32,
/* kmp_task_t */ VoidPtr, Int32,
@ -472,8 +470,6 @@ __OMP_RTL(__kmpc_target_deinit, false, Void,)
__OMP_RTL(__kmpc_kernel_prepare_parallel, false, Void, VoidPtr)
__OMP_RTL(__kmpc_parallel_51, false, Void, IdentPtr, Int32, Int32, Int32, Int32,
VoidPtr, VoidPtr, VoidPtrPtr, SizeTy)
__OMP_RTL(__kmpc_parallel_60, false, Void, IdentPtr, Int32, Int32, Int32, Int32,
VoidPtr, VoidPtr, VoidPtrPtr, SizeTy, Int32, Int32, Int8Ptr)
__OMP_RTL(__kmpc_for_static_loop_4, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int8)
__OMP_RTL(__kmpc_for_static_loop_4u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int8)
__OMP_RTL(__kmpc_for_static_loop_8, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int64, Int8)
@ -712,10 +708,6 @@ __OMP_RTL_ATTRS(__kmpc_omp_taskyield, InaccessibleArgOnlyAttrs, SExt,
ParamAttrs(ReadOnlyPtrAttrs, SExt, SExt))
__OMP_RTL_ATTRS(__kmpc_push_num_threads, InaccessibleArgOnlyAttrs,
AttributeSet(), ParamAttrs(ReadOnlyPtrAttrs, SExt, SExt))
__OMP_RTL_ATTRS(__kmpc_push_num_threads_strict, InaccessibleArgOnlyAttrs,
AttributeSet(),
ParamAttrs(ReadOnlyPtrAttrs, SExt, SExt, SExt,
ReadOnlyPtrAttrs))
__OMP_RTL_ATTRS(__kmpc_push_proc_bind, InaccessibleArgOnlyAttrs, AttributeSet(),
ParamAttrs(ReadOnlyPtrAttrs, SExt, SExt))
__OMP_RTL_ATTRS(__kmpc_omp_reg_task_with_affinity, DefaultAttrs, SExt,
@ -1087,10 +1079,6 @@ __OMP_RTL_ATTRS(__kmpc_parallel_51, AlwaysInlineAttrs, AttributeSet(),
ParamAttrs(AttributeSet(), SExt, SExt, SExt, SExt,
AttributeSet(), AttributeSet(), AttributeSet(),
SizeTyExt))
__OMP_RTL_ATTRS(__kmpc_parallel_60, AlwaysInlineAttrs, AttributeSet(),
ParamAttrs(AttributeSet(), SExt, SExt, SExt, SExt,
AttributeSet(), AttributeSet(), AttributeSet(),
SizeTyExt, SExt, SExt, AttributeSet()))
__OMP_RTL_ATTRS(__kmpc_serialized_parallel, InaccessibleArgOnlyAttrs,
AttributeSet(), ParamAttrs(ReadOnlyPtrAttrs, SExt))
__OMP_RTL_ATTRS(__kmpc_end_serialized_parallel, InaccessibleArgOnlyAttrs,

1
openmp/runtime/src/kmp.h
View File

@ -4629,7 +4629,6 @@ extern void (*kmp_target_sync_cb)(ident_t *loc_ref, int gtid,
#endif // ENABLE_LIBOMPTARGET
// Support for error directive
// See definition in offload/DeviceRTL DeviceTypes.h
typedef enum kmp_severity_t {
severity_warning = 1,
severity_fatal = 2