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[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)

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Similar to https://github.com/llvm/llvm-project/pull/96902, this adds
`getDataLayout()` helpers to Function and GlobalValue, replacing the
current `getParent()->getDataLayout()` pattern.
This commit is contained in:
Nikita Popov 2024-06-28 08:36:49 +02:00 committed by GitHub
parent 519e0bb094
commit 9df71d7673
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
178 changed files with 313 additions and 293 deletions
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2
llvm/include/llvm/Analysis/ScalarEvolution.h
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@ -1266,7 +1266,7 @@ public:
/// Return the DataLayout associated with the module this SCEV instance is
/// operating on.
const DataLayout &getDataLayout() const {
return F.getParent()->getDataLayout();
return F.getDataLayout();
}
const SCEVPredicate *getEqualPredicate(const SCEV *LHS, const SCEV *RHS);

2
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
View File

@ -284,7 +284,7 @@ public:
}
const DataLayout &getDataLayout() const {
return getMF().getFunction().getParent()->getDataLayout();
return getMF().getFunction().getDataLayout();
}
LLVMContext &getContext() const {

6
llvm/include/llvm/IR/Function.h
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@ -47,6 +47,7 @@ typedef unsigned ID;
class AssemblyAnnotationWriter;
class Constant;
class ConstantRange;
class DataLayout;
struct DenormalMode;
class DISubprogram;
enum LibFunc : unsigned;
@ -214,6 +215,11 @@ public:
/// function.
LLVMContext &getContext() const;
/// Get the data layout of the module this function belongs to.
///
/// Requires the function to have a parent module.
const DataLayout &getDataLayout() const;
/// isVarArg - Return true if this function takes a variable number of
/// arguments.
bool isVarArg() const { return getFunctionType()->isVarArg(); }

6
llvm/include/llvm/IR/GlobalValue.h
View File

@ -32,6 +32,7 @@ namespace llvm {
class Comdat;
class ConstantRange;
class DataLayout;
class Error;
class GlobalObject;
class Module;
@ -655,6 +656,11 @@ public:
Module *getParent() { return Parent; }
const Module *getParent() const { return Parent; }
/// Get the data layout of the module this global belongs to.
///
/// Requires the global to have a parent module.
const DataLayout &getDataLayout() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static bool classof(const Value *V) {
return V->getValueID() == Value::FunctionVal ||

2
llvm/lib/Analysis/AliasAnalysisEvaluator.cpp
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@ -99,7 +99,7 @@ PreservedAnalyses AAEvaluator::run(Function &F, FunctionAnalysisManager &AM) {
}
void AAEvaluator::runInternal(Function &F, AAResults &AA) {
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
++FunctionCount;

4
llvm/lib/Analysis/BasicAliasAnalysis.cpp
View File

@ -1919,7 +1919,7 @@ BasicAAResult BasicAA::run(Function &F, FunctionAnalysisManager &AM) {
auto &TLI = AM.getResult<TargetLibraryAnalysis>(F);
auto &AC = AM.getResult<AssumptionAnalysis>(F);
auto *DT = &AM.getResult<DominatorTreeAnalysis>(F);
return BasicAAResult(F.getParent()->getDataLayout(), F, TLI, AC, DT);
return BasicAAResult(F.getDataLayout(), F, TLI, AC, DT);
}
BasicAAWrapperPass::BasicAAWrapperPass() : FunctionPass(ID) {
@ -1947,7 +1947,7 @@ bool BasicAAWrapperPass::runOnFunction(Function &F) {
auto &TLIWP = getAnalysis<TargetLibraryInfoWrapperPass>();
auto &DTWP = getAnalysis<DominatorTreeWrapperPass>();
Result.reset(new BasicAAResult(F.getParent()->getDataLayout(), F,
Result.reset(new BasicAAResult(F.getDataLayout(), F,
TLIWP.getTLI(F), ACT.getAssumptionCache(F),
&DTWP.getDomTree()));

8
llvm/lib/Analysis/ConstantFolding.cpp
View File

@ -644,7 +644,7 @@ Constant *llvm::ReadByteArrayFromGlobal(const GlobalVariable *GV,
if (!GV->isConstant() || !GV->hasDefinitiveInitializer())
return nullptr;
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
Constant *Init = const_cast<Constant *>(GV->getInitializer());
TypeSize InitSize = DL.getTypeAllocSize(Init->getType());
if (InitSize < Offset)
@ -3485,15 +3485,15 @@ Constant *llvm::ConstantFoldCall(const CallBase *Call, Function *F,
StringRef Name = F->getName();
if (auto *FVTy = dyn_cast<FixedVectorType>(Ty))
return ConstantFoldFixedVectorCall(
Name, IID, FVTy, Operands, F->getParent()->getDataLayout(), TLI, Call);
Name, IID, FVTy, Operands, F->getDataLayout(), TLI, Call);
if (auto *SVTy = dyn_cast<ScalableVectorType>(Ty))
return ConstantFoldScalableVectorCall(
Name, IID, SVTy, Operands, F->getParent()->getDataLayout(), TLI, Call);
Name, IID, SVTy, Operands, F->getDataLayout(), TLI, Call);
if (auto *StTy = dyn_cast<StructType>(Ty))
return ConstantFoldStructCall(Name, IID, StTy, Operands,
F->getParent()->getDataLayout(), TLI, Call);
F->getDataLayout(), TLI, Call);
// TODO: If this is a library function, we already discovered that above,
// so we should pass the LibFunc, not the name (and it might be better

4
llvm/lib/Analysis/DependenceAnalysis.cpp
View File

@ -3607,7 +3607,7 @@ DependenceInfo::depends(Instruction *Src, Instruction *Dst,
Value *SrcPtr = getLoadStorePointerOperand(Src);
Value *DstPtr = getLoadStorePointerOperand(Dst);
switch (underlyingObjectsAlias(AA, F->getParent()->getDataLayout(),
switch (underlyingObjectsAlias(AA, F->getDataLayout(),
MemoryLocation::get(Dst),
MemoryLocation::get(Src))) {
case AliasResult::MayAlias:
@ -4034,7 +4034,7 @@ const SCEV *DependenceInfo::getSplitIteration(const Dependence &Dep,
Value *SrcPtr = getLoadStorePointerOperand(Src);
Value *DstPtr = getLoadStorePointerOperand(Dst);
assert(underlyingObjectsAlias(
AA, F->getParent()->getDataLayout(), MemoryLocation::get(Dst),
AA, F->getDataLayout(), MemoryLocation::get(Dst),
MemoryLocation::get(Src)) == AliasResult::MustAlias);
// establish loop nesting levels

4
llvm/lib/Analysis/InlineCost.cpp
View File

@ -498,7 +498,7 @@ public:
ProfileSummaryInfo *PSI = nullptr,
OptimizationRemarkEmitter *ORE = nullptr)
: TTI(TTI), GetAssumptionCache(GetAssumptionCache), GetBFI(GetBFI),
PSI(PSI), F(Callee), DL(F.getParent()->getDataLayout()), ORE(ORE),
PSI(PSI), F(Callee), DL(F.getDataLayout()), ORE(ORE),
CandidateCall(Call) {}
InlineResult analyze();
@ -2999,7 +2999,7 @@ std::optional<InlineResult> llvm::getAttributeBasedInliningDecision(
// alloca, the inlined code would need to be adjusted to handle that the
// argument is in the alloca address space (so it is a little bit complicated
// to solve).
unsigned AllocaAS = Callee->getParent()->getDataLayout().getAllocaAddrSpace();
unsigned AllocaAS = Callee->getDataLayout().getAllocaAddrSpace();
for (unsigned I = 0, E = Call.arg_size(); I != E; ++I)
if (Call.isByValArgument(I)) {
PointerType *PTy = cast<PointerType>(Call.getArgOperand(I)->getType());

4
llvm/lib/Analysis/InstructionSimplify.cpp
View File

@ -7248,7 +7248,7 @@ const SimplifyQuery getBestSimplifyQuery(Pass &P, Function &F) {
auto *TLI = TLIWP ? &TLIWP->getTLI(F) : nullptr;
auto *ACWP = P.getAnalysisIfAvailable<AssumptionCacheTracker>();
auto *AC = ACWP ? &ACWP->getAssumptionCache(F) : nullptr;
return {F.getParent()->getDataLayout(), TLI, DT, AC};
return {F.getDataLayout(), TLI, DT, AC};
}
const SimplifyQuery getBestSimplifyQuery(LoopStandardAnalysisResults &AR,
@ -7262,7 +7262,7 @@ const SimplifyQuery getBestSimplifyQuery(AnalysisManager<T, TArgs...> &AM,
auto *DT = AM.template getCachedResult<DominatorTreeAnalysis>(F);
auto *TLI = AM.template getCachedResult<TargetLibraryAnalysis>(F);
auto *AC = AM.template getCachedResult<AssumptionAnalysis>(F);
return {F.getParent()->getDataLayout(), TLI, DT, AC};
return {F.getDataLayout(), TLI, DT, AC};
}
template const SimplifyQuery getBestSimplifyQuery(AnalysisManager<Function> &,
Function &);

2
llvm/lib/Analysis/LazyValueInfo.cpp
View File

@ -1689,7 +1689,7 @@ LazyValueInfo LazyValueAnalysis::run(Function &F,
FunctionAnalysisManager &FAM) {
auto &AC = FAM.getResult<AssumptionAnalysis>(F);
return LazyValueInfo(&AC, &F.getParent()->getDataLayout());
return LazyValueInfo(&AC, &F.getDataLayout());
}
/// Returns true if we can statically tell that this value will never be a

2
llvm/lib/Analysis/Lint.cpp
View File

@ -709,7 +709,7 @@ Value *Lint::findValueImpl(Value *V, bool OffsetOk,
PreservedAnalyses LintPass::run(Function &F, FunctionAnalysisManager &AM) {
auto *Mod = F.getParent();
auto *DL = &F.getParent()->getDataLayout();
auto *DL = &F.getDataLayout();
auto *AA = &AM.getResult<AAManager>(F);
auto *AC = &AM.getResult<AssumptionAnalysis>(F);
auto *DT = &AM.getResult<DominatorTreeAnalysis>(F);

2
llvm/lib/Analysis/MemDerefPrinter.cpp
View File

@ -26,7 +26,7 @@ PreservedAnalyses MemDerefPrinterPass::run(Function &F,
SmallVector<Value *, 4> Deref;
SmallPtrSet<Value *, 4> DerefAndAligned;
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
for (auto &I : instructions(F)) {
if (LoadInst *LI = dyn_cast<LoadInst>(&I)) {
Value *PO = LI->getPointerOperand();

2
llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp
View File

@ -142,5 +142,5 @@ ModRefInfo ObjCARCAAResult::getModRefInfo(const CallBase *Call,
AnalysisKey ObjCARCAA::Key;
ObjCARCAAResult ObjCARCAA::run(Function &F, FunctionAnalysisManager &AM) {
return ObjCARCAAResult(F.getParent()->getDataLayout());
return ObjCARCAAResult(F.getDataLayout());
}

2
llvm/lib/Analysis/StackLifetime.cpp
View File

@ -87,7 +87,7 @@ void StackLifetime::collectMarkers() {
DenseMap<const BasicBlock *, SmallDenseMap<const IntrinsicInst *, Marker>>
BBMarkerSet;
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
// Compute the set of start/end markers per basic block.
for (const BasicBlock *BB : depth_first(&F)) {

4
llvm/lib/Analysis/StackSafetyAnalysis.cpp
View File

@ -268,7 +268,7 @@ class StackSafetyLocalAnalysis {
public:
StackSafetyLocalAnalysis(Function &F, ScalarEvolution &SE)
: F(F), DL(F.getParent()->getDataLayout()), SE(SE),
: F(F), DL(F.getDataLayout()), SE(SE),
PointerSize(DL.getPointerSizeInBits()),
UnknownRange(PointerSize, true) {}
@ -852,7 +852,7 @@ GVToSSI createGlobalStackSafetyInfo(
}
uint32_t PointerSize =
Copy.begin()->first->getParent()->getDataLayout().getPointerSizeInBits();
Copy.begin()->first->getDataLayout().getPointerSizeInBits();
StackSafetyDataFlowAnalysis<GlobalValue> SSDFA(PointerSize, std::move(Copy));
for (const auto &F : SSDFA.run()) {

2
llvm/lib/Analysis/TargetTransformInfo.cpp
View File

@ -1354,7 +1354,7 @@ TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
AnalysisKey TargetIRAnalysis::Key;
TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
return Result(F.getParent()->getDataLayout());
return Result(F.getDataLayout());
}
// Register the basic pass.

2
llvm/lib/Analysis/ValueTracking.cpp
View File

@ -6115,7 +6115,7 @@ bool llvm::getConstantDataArrayInfo(const Value *V,
// Fail if V is not based on constant global object.
return false;
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
APInt Off(DL.getIndexTypeSizeInBits(V->getType()), 0);
if (GV != V->stripAndAccumulateConstantOffsets(DL, Off,

6
llvm/lib/AsmParser/LLParser.cpp
View File

@ -8282,7 +8282,7 @@ int LLParser::parseCmpXchg(Instruction *&Inst, PerFunctionState &PFS) {
return error(NewLoc, "cmpxchg operand must be a first class value");
const Align DefaultAlignment(
PFS.getFunction().getParent()->getDataLayout().getTypeStoreSize(
PFS.getFunction().getDataLayout().getTypeStoreSize(
Cmp->getType()));
AtomicCmpXchgInst *CXI =
@ -8388,13 +8388,13 @@ int LLParser::parseAtomicRMW(Instruction *&Inst, PerFunctionState &PFS) {
}
unsigned Size =
PFS.getFunction().getParent()->getDataLayout().getTypeStoreSizeInBits(
PFS.getFunction().getDataLayout().getTypeStoreSizeInBits(
Val->getType());
if (Size < 8 || (Size & (Size - 1)))
return error(ValLoc, "atomicrmw operand must be power-of-two byte-sized"
" integer");
const Align DefaultAlignment(
PFS.getFunction().getParent()->getDataLayout().getTypeStoreSize(
PFS.getFunction().getDataLayout().getTypeStoreSize(
Val->getType()));
AtomicRMWInst *RMWI =
new AtomicRMWInst(Operation, Ptr, Val,

2
llvm/lib/CodeGen/Analysis.cpp
View File

@ -730,7 +730,7 @@ bool llvm::returnTypeIsEligibleForTailCall(const Function *F,
// index is compatible with the value we return.
if (!slotOnlyDiscardsData(RetVal, CallVal, TmpRetPath, TmpCallPath,
AllowDifferingSizes, TLI,
F->getParent()->getDataLayout()))
F->getDataLayout()))
return false;
CallEmpty = !nextRealType(CallSubTypes, CallPath);

22
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -783,7 +783,7 @@ void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
// If the alignment is specified, we *must* obey it. Overaligning a global
@ -871,7 +871,7 @@ void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
emitAlignment(Alignment, GV);
OutStreamer->emitLabel(MangSym);
emitGlobalConstant(GV->getParent()->getDataLayout(),
emitGlobalConstant(GV->getDataLayout(),
GV->getInitializer());
}
@ -911,7 +911,7 @@ void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
if (LocalAlias != EmittedInitSym)
OutStreamer->emitLabel(LocalAlias);
emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer());
emitGlobalConstant(GV->getDataLayout(), GV->getInitializer());
if (MAI->hasDotTypeDotSizeDirective())
// .size foo, 42
@ -935,7 +935,7 @@ void AsmPrinter::emitFunctionPrefix(ArrayRef<const Constant *> Prefix) {
const Function &F = MF->getFunction();
if (!MAI->hasSubsectionsViaSymbols()) {
for (auto &C : Prefix)
emitGlobalConstant(F.getParent()->getDataLayout(), C);
emitGlobalConstant(F.getDataLayout(), C);
return;
}
// Preserving prefix-like data on platforms which use subsections-via-symbols
@ -945,7 +945,7 @@ void AsmPrinter::emitFunctionPrefix(ArrayRef<const Constant *> Prefix) {
OutStreamer->emitLabel(OutContext.createLinkerPrivateTempSymbol());
for (auto &C : Prefix) {
emitGlobalConstant(F.getParent()->getDataLayout(), C);
emitGlobalConstant(F.getDataLayout(), C);
}
// Emit an .alt_entry directive for the actual function symbol.
@ -1080,7 +1080,7 @@ void AsmPrinter::emitFunctionHeader() {
// Emit the prologue data.
if (F.hasPrologueData())
emitGlobalConstant(F.getParent()->getDataLayout(), F.getPrologueData());
emitGlobalConstant(F.getDataLayout(), F.getPrologueData());
}
/// EmitFunctionEntryLabel - Emit the label that is the entrypoint for the
@ -1528,7 +1528,7 @@ void AsmPrinter::emitKCFITrapEntry(const MachineFunction &MF,
void AsmPrinter::emitKCFITypeId(const MachineFunction &MF) {
const Function &F = MF.getFunction();
if (const MDNode *MD = F.getMetadata(LLVMContext::MD_kcfi_type))
emitGlobalConstant(F.getParent()->getDataLayout(),
emitGlobalConstant(F.getDataLayout(),
mdconst::extract<ConstantInt>(MD->getOperand(0)));
}
@ -1678,7 +1678,7 @@ void AsmPrinter::emitPCSections(const MachineFunction &MF) {
for (const MDOperand &AuxMDO : AuxMDs->operands()) {
assert(isa<ConstantAsMetadata>(AuxMDO) && "expecting a constant");
const Constant *C = cast<ConstantAsMetadata>(AuxMDO)->getValue();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
const uint64_t Size = DL.getTypeStoreSize(C->getType());
if (auto *CI = dyn_cast<ConstantInt>(C);
@ -2926,14 +2926,14 @@ bool AsmPrinter::emitSpecialLLVMGlobal(const GlobalVariable *GV) {
assert(GV->hasInitializer() && "Not a special LLVM global!");
if (GV->getName() == "llvm.global_ctors") {
emitXXStructorList(GV->getParent()->getDataLayout(), GV->getInitializer(),
emitXXStructorList(GV->getDataLayout(), GV->getInitializer(),
/* isCtor */ true);
return true;
}
if (GV->getName() == "llvm.global_dtors") {
emitXXStructorList(GV->getParent()->getDataLayout(), GV->getInitializer(),
emitXXStructorList(GV->getDataLayout(), GV->getInitializer(),
/* isCtor */ false);
return true;
@ -3147,7 +3147,7 @@ void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
void AsmPrinter::emitAlignment(Align Alignment, const GlobalObject *GV,
unsigned MaxBytesToEmit) const {
if (GV)
Alignment = getGVAlignment(GV, GV->getParent()->getDataLayout(), Alignment);
Alignment = getGVAlignment(GV, GV->getDataLayout(), Alignment);
if (Alignment == Align(1))
return; // 1-byte aligned: no need to emit alignment.

4
llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
View File

@ -2184,7 +2184,7 @@ static AssignmentTrackingLowering::OverlapMap buildOverlapMapAndRecordDeclares(
if (auto *DII = dyn_cast<DbgVariableIntrinsic>(&I)) {
ProcessDbgRecord(DII, InstDeclares);
} else if (auto Info = getUntaggedStoreAssignmentInfo(
I, Fn.getParent()->getDataLayout())) {
I, Fn.getDataLayout())) {
// Find markers linked to this alloca.
auto HandleDbgAssignForStore = [&](auto *Assign) {
std::optional<DIExpression::FragmentInfo> FragInfo;
@ -2800,7 +2800,7 @@ DebugAssignmentTrackingAnalysis::run(Function &F,
if (!isAssignmentTrackingEnabled(*F.getParent()))
return FunctionVarLocs();
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
FunctionVarLocsBuilder Builder;
analyzeFunction(F, DL, &Builder);

4
llvm/lib/CodeGen/AtomicExpandPass.cpp
View File

@ -208,7 +208,7 @@ bool AtomicExpandImpl::run(Function &F, const TargetMachine *TM) {
if (!Subtarget->enableAtomicExpand())
return false;
TLI = Subtarget->getTargetLowering();
DL = &F.getParent()->getDataLayout();
DL = &F.getDataLayout();
SmallVector<Instruction *, 1> AtomicInsts;
@ -1205,7 +1205,7 @@ Value *AtomicExpandImpl::insertRMWLLSCLoop(
Function *F = BB->getParent();
assert(AddrAlign >=
F->getParent()->getDataLayout().getTypeStoreSize(ResultTy) &&
F->getDataLayout().getTypeStoreSize(ResultTy) &&
"Expected at least natural alignment at this point.");
// Given: atomicrmw some_op iN* %addr, iN %incr ordering

2
llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
View File

@ -30,5 +30,5 @@ llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
cl::Hidden);
BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}

6
llvm/lib/CodeGen/CodeGenPrepare.cpp
View File

@ -509,7 +509,7 @@ bool CodeGenPrepareLegacyPass::runOnFunction(Function &F) {
return false;
auto TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
CodeGenPrepare CGP(TM);
CGP.DL = &F.getParent()->getDataLayout();
CGP.DL = &F.getDataLayout();
CGP.SubtargetInfo = TM->getSubtargetImpl(F);
CGP.TLI = CGP.SubtargetInfo->getTargetLowering();
CGP.TRI = CGP.SubtargetInfo->getRegisterInfo();
@ -557,7 +557,7 @@ PreservedAnalyses CodeGenPreparePass::run(Function &F,
}
bool CodeGenPrepare::run(Function &F, FunctionAnalysisManager &AM) {
DL = &F.getParent()->getDataLayout();
DL = &F.getDataLayout();
SubtargetInfo = TM->getSubtargetImpl(F);
TLI = SubtargetInfo->getTargetLowering();
TRI = SubtargetInfo->getRegisterInfo();
@ -5185,7 +5185,7 @@ static bool IsOperandAMemoryOperand(CallInst *CI, InlineAsm *IA, Value *OpVal,
const TargetRegisterInfo &TRI) {
const Function *F = CI->getFunction();
TargetLowering::AsmOperandInfoVector TargetConstraints =
TLI.ParseConstraints(F->getParent()->getDataLayout(), &TRI, *CI);
TLI.ParseConstraints(F->getDataLayout(), &TRI, *CI);
for (TargetLowering::AsmOperandInfo &OpInfo : TargetConstraints) {
// Compute the constraint code and ConstraintType to use.

2
llvm/lib/CodeGen/ExpandMemCmp.cpp
View File

@ -970,7 +970,7 @@ PreservedAnalyses runImpl(Function &F, const TargetLibraryInfo *TLI,
if (DT)
DTU.emplace(DT, DomTreeUpdater::UpdateStrategy::Lazy);
const DataLayout& DL = F.getParent()->getDataLayout();
const DataLayout& DL = F.getDataLayout();
bool MadeChanges = false;
for (auto BBIt = F.begin(); BBIt != F.end();) {
if (runOnBlock(*BBIt, TLI, TTI, TL, DL, PSI, BFI, DTU ? &*DTU : nullptr)) {

2
llvm/lib/CodeGen/ExpandVectorPredication.cpp
View File

@ -571,7 +571,7 @@ CachingVPExpander::expandPredicationInMemoryIntrinsic(IRBuilder<> &Builder,
VPIntrinsic &VPI) {
assert(VPI.canIgnoreVectorLengthParam());
const auto &DL = F.getParent()->getDataLayout();
const auto &DL = F.getDataLayout();
Value *MaskParam = VPI.getMaskParam();
Value *PtrParam = VPI.getMemoryPointerParam();

2
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
View File

@ -733,7 +733,7 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
MachineFunction &MF = MIRBuilder.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
const unsigned NumArgs = Args.size();

2
llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
View File

@ -32,7 +32,7 @@ INITIALIZE_PASS(GISelKnownBitsAnalysis, DEBUG_TYPE,
GISelKnownBits::GISelKnownBits(MachineFunction &MF, unsigned MaxDepth)
: MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),
DL(MF.getFunction().getParent()->getDataLayout()), MaxDepth(MaxDepth) {}
DL(MF.getFunction().getDataLayout()), MaxDepth(MaxDepth) {}
Align GISelKnownBits::computeKnownAlignment(Register R, unsigned Depth) {
const MachineInstr *MI = MRI.getVRegDef(R);

2
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -3841,7 +3841,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
CurBuilder->setMF(*MF);
EntryBuilder->setMF(*MF);
MRI = &MF->getRegInfo();
DL = &F.getParent()->getDataLayout();
DL = &F.getDataLayout();
ORE = std::make_unique<OptimizationRemarkEmitter>(&F);
const TargetMachine &TM = MF->getTarget();
TM.resetTargetOptions(F);

2
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
View File

@ -223,7 +223,7 @@ bool InlineAsmLowering::lowerInlineAsm(
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MachineRegisterInfo *MRI = MIRBuilder.getMRI();

4
llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
View File

@ -318,7 +318,7 @@ bool LoadStoreOpt::mergeStores(SmallVectorImpl<GStore *> &StoresToMerge) {
assert(MRI->getType(StoreMI->getValueReg()) == OrigTy);
#endif
const auto &DL = MF->getFunction().getParent()->getDataLayout();
const auto &DL = MF->getFunction().getDataLayout();
bool AnyMerged = false;
do {
unsigned NumPow2 = llvm::bit_floor(StoresToMerge.size());
@ -955,7 +955,7 @@ void LoadStoreOpt::initializeStoreMergeTargetInfo(unsigned AddrSpace) {
// Need to reserve at least MaxStoreSizeToForm + 1 bits.
BitVector LegalSizes(MaxStoreSizeToForm * 2);
const auto &LI = *MF->getSubtarget().getLegalizerInfo();
const auto &DL = MF->getFunction().getParent()->getDataLayout();
const auto &DL = MF->getFunction().getDataLayout();
Type *IRPtrTy = PointerType::get(MF->getFunction().getContext(), AddrSpace);
LLT PtrTy = getLLTForType(*IRPtrTy, DL);
// We assume that we're not going to be generating any stores wider than

4
llvm/lib/CodeGen/HardwareLoops.cpp
View File

@ -240,7 +240,7 @@ bool HardwareLoopsLegacy::runOnFunction(Function &F) {
auto &SE = getAnalysis<ScalarEvolutionWrapperPass>().getSE();
auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
auto &TTI = getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
auto *ORE = &getAnalysis<OptimizationRemarkEmitterWrapperPass>().getORE();
auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();
auto *TLI = TLIP ? &TLIP->getTLI(F) : nullptr;
@ -275,7 +275,7 @@ PreservedAnalyses HardwareLoopsPass::run(Function &F,
auto *TLI = &AM.getResult<TargetLibraryAnalysis>(F);
auto &AC = AM.getResult<AssumptionAnalysis>(F);
auto *ORE = &AM.getResult<OptimizationRemarkEmitterAnalysis>(F);
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
HardwareLoopsImpl Impl(SE, LI, true, DT, DL, TTI, TLI, AC, ORE, Opts);
bool Changed = Impl.run(F);

2
llvm/lib/CodeGen/IndirectBrExpandPass.cpp
View File

@ -100,7 +100,7 @@ FunctionPass *llvm::createIndirectBrExpandPass() {
}
bool runImpl(Function &F, const TargetLowering *TLI, DomTreeUpdater *DTU) {
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
SmallVector<IndirectBrInst *, 1> IndirectBrs;

2
llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
View File

@ -1256,7 +1256,7 @@ bool InterleavedLoadCombineImpl::run() {
bool changed = false;
unsigned MaxFactor = TLI.getMaxSupportedInterleaveFactor();
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
// Start with the highest factor to avoid combining and recombining.
for (unsigned Factor = MaxFactor; Factor >= 2; Factor--) {

2
llvm/lib/CodeGen/MachineFunction.cpp
View File

@ -307,7 +307,7 @@ void MachineFunction::clear() {
}
const DataLayout &MachineFunction::getDataLayout() const {
return F.getParent()->getDataLayout();
return F.getDataLayout();
}
/// Get the JumpTableInfo for this function.

4
llvm/lib/CodeGen/SafeStack.cpp
View File

@ -886,7 +886,7 @@ public:
if (!TL)
report_fatal_error("TargetLowering instance is required");
auto *DL = &F.getParent()->getDataLayout();
auto *DL = &F.getDataLayout();
auto &TLI = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
auto &ACT = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
@ -946,7 +946,7 @@ PreservedAnalyses SafeStackPass::run(Function &F,
if (!TL)
report_fatal_error("TargetLowering instance is required");
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
// preserve DominatorTree
auto &DT = FAM.getResult<DominatorTreeAnalysis>(F);

4
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -186,7 +186,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
Register SP = TLI->getStackPointerRegisterToSaveRestore();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
std::vector<TargetLowering::AsmOperandInfo> Ops =
TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI,
TLI->ParseConstraints(Fn->getDataLayout(), TRI,
*Call);
for (TargetLowering::AsmOperandInfo &Op : Ops) {
if (Op.Type == InlineAsm::isClobber) {
@ -570,7 +570,7 @@ FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
SmallVector<EVT, 4> ValueVTs;
for (auto &P : ValueMap) {
ValueVTs.clear();
ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(),
ComputeValueVTs(*TLI, Fn->getDataLayout(),
P.first->getType(), ValueVTs);
unsigned Reg = P.second;
for (EVT VT : ValueVTs) {

2
llvm/lib/CodeGen/SjLjEHPrepare.cpp
View File

@ -199,7 +199,7 @@ SjLjEHPrepareImpl::setupFunctionContext(Function &F,
// Create an alloca for the incoming jump buffer ptr and the new jump buffer
// that needs to be restored on all exits from the function. This is an alloca
// because the value needs to be added to the global context list.
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
const Align Alignment = DL.getPrefTypeAlign(FunctionContextTy);
FuncCtx = new AllocaInst(FunctionContextTy, DL.getAllocaAddrSpace(), nullptr,
Alignment, "fn_context", EntryBB->begin());

6
llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
View File

@ -641,7 +641,7 @@ getELFSectionNameForGlobal(const GlobalObject *GO, SectionKind Kind,
// We also need alignment here.
// FIXME: this is getting the alignment of the character, not the
// alignment of the global!
Align Alignment = GO->getParent()->getDataLayout().getPreferredAlign(
Align Alignment = GO->getDataLayout().getPreferredAlign(
cast<GlobalVariable>(GO));
Name += ".str";
@ -1359,7 +1359,7 @@ MCSection *TargetLoweringObjectFileMachO::SelectSectionForGlobal(
// FIXME: Alignment check should be handled by section classifier.
if (Kind.isMergeable1ByteCString() &&
GO->getParent()->getDataLayout().getPreferredAlign(
GO->getDataLayout().getPreferredAlign(
cast<GlobalVariable>(GO)) < Align(32))
return CStringSection;
@ -1367,7 +1367,7 @@ MCSection *TargetLoweringObjectFileMachO::SelectSectionForGlobal(
// externally visible label, this runs into issues with certain linker
// versions.
if (Kind.isMergeable2ByteCString() && !GO->hasExternalLinkage() &&
GO->getParent()->getDataLayout().getPreferredAlign(
GO->getDataLayout().getPreferredAlign(
cast<GlobalVariable>(GO)) < Align(32))
return UStringSection;

2
llvm/lib/CodeGen/TypePromotion.cpp
View File

@ -924,7 +924,7 @@ bool TypePromotionImpl::run(Function &F, const TargetMachine *TM,
SafeToPromote.clear();
SafeWrap.clear();
bool MadeChange = false;
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
const TargetSubtargetInfo *SubtargetInfo = TM->getSubtargetImpl(F);
TLI = SubtargetInfo->getTargetLowering();
RegisterBitWidth =

2
llvm/lib/CodeGen/WinEHPrepare.cpp
View File

@ -138,7 +138,7 @@ bool WinEHPrepareImpl::runOnFunction(Function &Fn) {
if (!isScopedEHPersonality(Personality))
return false;
DL = &Fn.getParent()->getDataLayout();
DL = &Fn.getDataLayout();
return prepareExplicitEH(Fn);
}

4
llvm/lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -192,9 +192,9 @@ std::string ExecutionEngine::getMangledName(const GlobalValue *GV) {
SmallString<128> FullName;
const DataLayout &DL =
GV->getParent()->getDataLayout().isDefault()
GV->getDataLayout().isDefault()
? getDataLayout()
: GV->getParent()->getDataLayout();
: GV->getDataLayout();
Mangler::getNameWithPrefix(FullName, GV->getName(), DL);
return std::string(FullName);

2
llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
View File

@ -117,7 +117,7 @@ void CtorDtorRunner::add(iterator_range<CtorDtorIterator> CtorDtors) {
MangleAndInterner Mangle(
JD.getExecutionSession(),
(*CtorDtors.begin()).Func->getParent()->getDataLayout());
(*CtorDtors.begin()).Func->getDataLayout());
for (auto CtorDtor : CtorDtors) {
assert(CtorDtor.Func && CtorDtor.Func->hasName() &&

2
llvm/lib/ExecutionEngine/Orc/Mangling.cpp
View File

@ -35,7 +35,7 @@ void IRSymbolMapper::add(ExecutionSession &ES, const ManglingOptions &MO,
if (GVs.empty())
return;
MangleAndInterner Mangle(ES, GVs[0]->getParent()->getDataLayout());
MangleAndInterner Mangle(ES, GVs[0]->getDataLayout());
for (auto *G : GVs) {
assert(G && "GVs cannot contain null elements");
if (!G->hasName() || G->isDeclaration() || G->hasLocalLinkage() ||

4
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
View File

@ -5125,7 +5125,7 @@ void OpenMPIRBuilder::applySimd(CanonicalLoopInfo *CanonicalLoop,
for (auto &AlignedItem : AlignedVars) {
Value *AlignedPtr = AlignedItem.first;
Value *Alignment = AlignedItem.second;
Builder.CreateAlignmentAssumption(F->getParent()->getDataLayout(),
Builder.CreateAlignmentAssumption(F->getDataLayout(),
AlignedPtr, Alignment);
}
Builder.restoreIP(IP);
@ -5977,7 +5977,7 @@ OpenMPIRBuilder::createTargetInit(const LocationDescription &Loc, bool IsSPMD,
Function *Fn = getOrCreateRuntimeFunctionPtr(
omp::RuntimeFunction::OMPRTL___kmpc_target_init);
const DataLayout &DL = Fn->getParent()->getDataLayout();
const DataLayout &DL = Fn->getDataLayout();
Twine DynamicEnvironmentName = KernelName + "_dynamic_environment";
Constant *DynamicEnvironmentInitializer =

2
llvm/lib/IR/DebugInfo.cpp
View File

@ -2271,7 +2271,7 @@ bool AssignmentTrackingPass::runOnFunction(Function &F) {
return /*Changed*/ false;
bool Changed = false;
auto *DL = &F.getParent()->getDataLayout();
auto *DL = &F.getDataLayout();
// Collect a map of {backing storage : dbg.declares} (currently "backing
// storage" is limited to Allocas). We'll use this to find dbg.declares to
// delete after running `trackAssignments`.

4
llvm/lib/IR/Function.cpp
View File

@ -359,6 +359,10 @@ LLVMContext &Function::getContext() const {
return getType()->getContext();
}
const DataLayout &Function::getDataLayout() const {
return getParent()->getDataLayout();
}
unsigned Function::getInstructionCount() const {
unsigned NumInstrs = 0;
for (const BasicBlock &BB : BasicBlocks)

4
llvm/lib/IR/Globals.cpp
View File

@ -121,6 +121,10 @@ bool GlobalValue::canBenefitFromLocalAlias() const {
!isa<GlobalIFunc>(this) && !isDeduplicateComdat(getComdat());
}
const DataLayout &GlobalValue::getDataLayout() const {
return getParent()->getDataLayout();
}
void GlobalObject::setAlignment(MaybeAlign Align) {
assert((!Align || *Align <= MaximumAlignment) &&
"Alignment is greater than MaximumAlignment!");

6
llvm/lib/IR/Mangler.cpp
View File

@ -128,7 +128,7 @@ void Mangler::getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV,
PrefixTy = Private;
}
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
if (!GV->hasName()) {
// Get the ID for the global, assigning a new one if we haven't got one
// already.
@ -227,7 +227,7 @@ void llvm::emitLinkerFlagsForGlobalCOFF(raw_ostream &OS, const GlobalValue *GV,
raw_string_ostream FlagOS(Flag);
Mangler.getNameWithPrefix(FlagOS, GV, false);
FlagOS.flush();
if (Flag[0] == GV->getParent()->getDataLayout().getGlobalPrefix())
if (Flag[0] == GV->getDataLayout().getGlobalPrefix())
OS << Flag.substr(1);
else
OS << Flag;
@ -266,7 +266,7 @@ void llvm::emitLinkerFlagsForGlobalCOFF(raw_ostream &OS, const GlobalValue *GV,
raw_string_ostream FlagOS(Flag);
Mangler.getNameWithPrefix(FlagOS, GV, false);
FlagOS.flush();
if (Flag[0] == GV->getParent()->getDataLayout().getGlobalPrefix())
if (Flag[0] == GV->getDataLayout().getGlobalPrefix())
OS << Flag.substr(1);
else
OS << Flag;

2
llvm/lib/Linker/LinkModules.cpp
View File

@ -291,7 +291,7 @@ bool ModuleLinker::shouldLinkFromSource(bool &LinkFromSrc,
return false;
}
const DataLayout &DL = Dest.getParent()->getDataLayout();
const DataLayout &DL = Dest.getDataLayout();
uint64_t DestSize = DL.getTypeAllocSize(Dest.getValueType());
uint64_t SrcSize = DL.getTypeAllocSize(Src.getValueType());
LinkFromSrc = SrcSize > DestSize;

2
llvm/lib/Object/IRSymtab.cpp
View File

@ -295,7 +295,7 @@ Error Builder::addSymbol(const ModuleSymbolTable &Msymtab,
return make_error<StringError>("Only variables can have common linkage!",
inconvertibleErrorCode());
Uncommon().CommonSize =
GV->getParent()->getDataLayout().getTypeAllocSize(GV->getValueType());
GV->getDataLayout().getTypeAllocSize(GV->getValueType());
Uncommon().CommonAlign = GVar->getAlign() ? GVar->getAlign()->value() : 0;
}

6
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -15542,7 +15542,7 @@ bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
const TargetOptions &Options = getTargetMachine().Options;
const Function *F = I->getFunction();
const DataLayout &DL = F->getParent()->getDataLayout();
const DataLayout &DL = F->getDataLayout();
Type *Ty = User->getOperand(0)->getType();
return !(isFMAFasterThanFMulAndFAdd(*F, Ty) &&
@ -16032,7 +16032,7 @@ bool AArch64TargetLowering::shouldSinkOperands(
// the backend to generate a umull.
unsigned Bitwidth = I->getType()->getScalarSizeInBits();
APInt UpperMask = APInt::getHighBitsSet(Bitwidth, Bitwidth / 2);
const DataLayout &DL = I->getFunction()->getParent()->getDataLayout();
const DataLayout &DL = I->getDataLayout();
if (!MaskedValueIsZero(OperandInstr, UpperMask, DL))
continue;
NumZExts++;
@ -24143,7 +24143,7 @@ static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
const GlobalValue *GV = GN->getGlobal();
Type *T = GV->getValueType();
if (!T->isSized() ||
Offset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
Offset > GV->getDataLayout().getTypeAllocSize(T))
return SDValue();
SDLoc DL(GN);

2
llvm/lib/Target/AArch64/AArch64StackTagging.cpp
View File

@ -528,7 +528,7 @@ bool AArch64StackTagging::runOnFunction(Function &Fn) {
if (UseStackSafety)
SSI = &getAnalysis<StackSafetyGlobalInfoWrapperPass>().getResult();
F = &Fn;
DL = &Fn.getParent()->getDataLayout();
DL = &Fn.getDataLayout();
if (MergeInit)
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();

2
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
View File

@ -71,7 +71,7 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
public:
explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
bool areInlineCompatible(const Function *Caller,

6
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
View File

@ -372,7 +372,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
MachineRegisterInfo &MRI = MF.getRegInfo();
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
LLVMContext &Ctx = Val->getType()->getContext();
SmallVector<EVT, 4> SplitEVTs;
@ -639,7 +639,7 @@ bool AArch64CallLowering::lowerFormalArguments(
MachineFunction &MF = MIRBuilder.getMF();
MachineBasicBlock &MBB = MIRBuilder.getMBB();
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
// Arm64EC has extra requirements for varargs calls which are only implemented
@ -1257,7 +1257,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();

2
llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
View File

@ -184,7 +184,7 @@ bool matchFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI,
Type *T = GV->getValueType();
if (!T->isSized() ||
NewOffset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
NewOffset > GV->getDataLayout().getTypeAllocSize(T))
return false;
MatchInfo = std::make_pair(NewOffset, MinOffset);
return true;

2
llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
View File

@ -52,7 +52,7 @@ public:
using Result = AMDGPUAAResult;
AMDGPUAAResult run(Function &F, AnalysisManager<Function> &AM) {
return AMDGPUAAResult(F.getParent()->getDataLayout());
return AMDGPUAAResult(F.getDataLayout());
}
};

4
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
View File

@ -324,7 +324,7 @@ void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
report_fatal_error("symbol '" + Twine(GVSym->getName()) +
"' is already defined");
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
Align Alignment = GV->getAlign().value_or(Align(4));
@ -862,7 +862,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// FIXME: We should be using the number of registers determined during
// calling convention lowering to legalize the types.
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
unsigned PSArgCount = 0;
unsigned IntermediateVGPR = 0;
for (auto &Arg : F.args()) {

4
llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
View File

@ -116,7 +116,7 @@ bool AMDGPUAtomicOptimizer::runOnFunction(Function &F) {
const UniformityInfo *UA =
&getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
const DataLayout *DL = &F.getParent()->getDataLayout();
const DataLayout *DL = &F.getDataLayout();
DominatorTreeWrapperPass *const DTW =
getAnalysisIfAvailable<DominatorTreeWrapperPass>();
@ -137,7 +137,7 @@ PreservedAnalyses AMDGPUAtomicOptimizerPass::run(Function &F,
FunctionAnalysisManager &AM) {
const auto *UA = &AM.getResult<UniformityInfoAnalysis>(F);
const DataLayout *DL = &F.getParent()->getDataLayout();
const DataLayout *DL = &F.getDataLayout();
DomTreeUpdater DTU(&AM.getResult<DominatorTreeAnalysis>(F),
DomTreeUpdater::UpdateStrategy::Lazy);

10
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
View File

@ -416,7 +416,7 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
Align Alignment) const {
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
LLT PtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
@ -516,7 +516,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
@ -598,7 +598,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());
@ -1353,7 +1353,7 @@ bool AMDGPUCallLowering::lowerChainCall(MachineIRBuilder &MIRBuilder,
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
// The function to jump to is actually the first argument, so we'll change the
// Callee and other info to match that before using our existing helper.
@ -1407,7 +1407,7 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
SmallVector<ArgInfo, 8> OutArgs;
for (auto &OrigArg : Info.OrigArgs)

2
llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
View File

@ -312,7 +312,7 @@ void MetadataStreamerMsgPackV4::emitKernelArg(const Argument &Arg,
if (Node && ArgNo < Node->getNumOperands())
TypeQual = cast<MDString>(Node->getOperand(ArgNo))->getString();
const DataLayout &DL = Func->getParent()->getDataLayout();
const DataLayout &DL = Func->getDataLayout();
MaybeAlign PointeeAlign;
Type *Ty = Arg.hasByRefAttr() ? Arg.getParamByRefType() : Arg.getType();

4
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
View File

@ -1158,7 +1158,7 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
Align MaxAlign = Align(1);
uint64_t ExplicitArgOffset = 0;
const DataLayout &DL = Fn.getParent()->getDataLayout();
const DataLayout &DL = Fn.getDataLayout();
unsigned InIndex = 0;
@ -6015,7 +6015,7 @@ AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
case AtomicRMWInst::FMin:
return AtomicExpansionKind::CmpXChg;
case AtomicRMWInst::Xchg: {
const DataLayout &DL = RMW->getFunction()->getParent()->getDataLayout();
const DataLayout &DL = RMW->getFunction()->getDataLayout();
unsigned ValSize = DL.getTypeSizeInBits(RMW->getType());
if (ValSize == 32 || ValSize == 64)
return AtomicExpansionKind::None;

2
llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
View File

@ -104,7 +104,7 @@ static bool lowerKernelArguments(Function &F, const TargetMachine &TM) {
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
LLVMContext &Ctx = F.getParent()->getContext();
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
BasicBlock &EntryBlock = *F.begin();
IRBuilder<> Builder(&EntryBlock, getInsertPt(EntryBlock));

2
llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
View File

@ -101,7 +101,7 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
Value *Remainders[3] = {nullptr, nullptr, nullptr};
Value *GridSizes[3] = {nullptr, nullptr, nullptr};
const DataLayout &DL = F->getParent()->getDataLayout();
const DataLayout &DL = F->getDataLayout();
// We expect to see several GEP users, casted to the appropriate type and
// loaded.

2
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
View File

@ -597,7 +597,7 @@ uint64_t AMDGPUSubtarget::getExplicitKernArgSize(const Function &F,
assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
F.getCallingConv() == CallingConv::SPIR_KERNEL);
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
uint64_t ExplicitArgBytes = 0;
MaxAlign = Align(1);

6
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
View File

@ -95,7 +95,7 @@ static bool dependsOnLocalPhi(const Loop *L, const Value *Cond,
}
AMDGPUTTIImpl::AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()),
: BaseT(TM, F.getDataLayout()),
TargetTriple(TM->getTargetTriple()),
ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),
TLI(ST->getTargetLowering()) {}
@ -292,7 +292,7 @@ const FeatureBitset GCNTTIImpl::InlineFeatureIgnoreList = {
AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops};
GCNTTIImpl::GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()),
: BaseT(TM, F.getDataLayout()),
ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),
TLI(ST->getTargetLowering()), CommonTTI(TM, F),
IsGraphics(AMDGPU::isGraphics(F.getCallingConv())) {
@ -978,7 +978,7 @@ bool GCNTTIImpl::isAlwaysUniform(const Value *V) const {
if (match(V, m_c_And(m_Intrinsic<Intrinsic::amdgcn_workitem_id_x>(),
m_Value(Mask)))) {
const Function *F = cast<Instruction>(V)->getFunction();
const DataLayout &DL = F->getParent()->getDataLayout();
const DataLayout &DL = F->getDataLayout();
return computeKnownBits(Mask, DL).countMinTrailingZeros() >=
ST->getWavefrontSizeLog2() &&
ST->getMaxWorkitemID(*F, 1) == 0 && ST->getMaxWorkitemID(*F, 2) == 0;

2
llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
View File

@ -24,7 +24,7 @@ using namespace llvm;
#define DEBUG_TYPE "R600tti"
R600TTIImpl::R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()),
: BaseT(TM, F.getDataLayout()),
ST(static_cast<const R600Subtarget *>(TM->getSubtargetImpl(F))),
TLI(ST->getTargetLowering()), CommonTTI(TM, F) {}

2
llvm/lib/Target/ARC/ARCTargetTransformInfo.h
View File

@ -38,7 +38,7 @@ class ARCTTIImpl : public BasicTTIImplBase<ARCTTIImpl> {
public:
explicit ARCTTIImpl(const ARCTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl()),
TLI(ST->getTargetLowering()) {}
// Provide value semantics. MSVC requires that we spell all of these out.

12
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -21043,7 +21043,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::arm_neon_vld4dup: {
Info.opc = ISD::INTRINSIC_W_CHAIN;
// Conservatively set memVT to the entire set of vectors loaded.
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
Info.ptrVal = I.getArgOperand(0);
@ -21059,7 +21059,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::arm_neon_vld1x4: {
Info.opc = ISD::INTRINSIC_W_CHAIN;
// Conservatively set memVT to the entire set of vectors loaded.
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
Info.ptrVal = I.getArgOperand(I.arg_size() - 1);
@ -21078,7 +21078,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::arm_neon_vst4lane: {
Info.opc = ISD::INTRINSIC_VOID;
// Conservatively set memVT to the entire set of vectors stored.
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
unsigned NumElts = 0;
for (unsigned ArgI = 1, ArgE = I.arg_size(); ArgI < ArgE; ++ArgI) {
Type *ArgTy = I.getArgOperand(ArgI)->getType();
@ -21100,7 +21100,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::arm_neon_vst1x4: {
Info.opc = ISD::INTRINSIC_VOID;
// Conservatively set memVT to the entire set of vectors stored.
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
unsigned NumElts = 0;
for (unsigned ArgI = 1, ArgE = I.arg_size(); ArgI < ArgE; ++ArgI) {
Type *ArgTy = I.getArgOperand(ArgI)->getType();
@ -21206,7 +21206,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
}
case Intrinsic::arm_ldaex:
case Intrinsic::arm_ldrex: {
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
Type *ValTy = I.getParamElementType(0);
Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::getVT(ValTy);
@ -21218,7 +21218,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
}
case Intrinsic::arm_stlex:
case Intrinsic::arm_strex: {
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
Type *ValTy = I.getParamElementType(1);
Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::getVT(ValTy);

2
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
View File

@ -101,7 +101,7 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
public:
explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
bool areInlineCompatible(const Function *Caller,

2
llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
View File

@ -1257,7 +1257,7 @@ bool MVEGatherScatterLowering::runOnFunction(Function &F) {
if (!ST->hasMVEIntegerOps())
return false;
LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
DL = &F.getParent()->getDataLayout();
DL = &F.getDataLayout();
SmallVector<IntrinsicInst *, 4> Gathers;
SmallVector<IntrinsicInst *, 4> Scatters;

2
llvm/lib/Target/BPF/BPFTargetTransformInfo.h
View File

@ -34,7 +34,7 @@ class BPFTTIImpl : public BasicTTIImplBase<BPFTTIImpl> {
public:
explicit BPFTTIImpl(const BPFTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {

2
llvm/lib/Target/BPF/BTFDebug.cpp
View File

@ -1489,7 +1489,7 @@ void BTFDebug::processGlobals(bool ProcessingMapDef) {
}
// Calculate symbol size
const DataLayout &DL = Global.getParent()->getDataLayout();
const DataLayout &DL = Global.getDataLayout();
uint32_t Size = DL.getTypeAllocSize(Global.getValueType());
DataSecEntries[std::string(SecName)]->addDataSecEntry(VarId,

2
llvm/lib/Target/DirectX/DirectXAsmPrinter.cpp
View File

@ -49,7 +49,7 @@ void DXILAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM);
MCSection *TheSection = getObjFileLowering().SectionForGlobal(GV, GVKind, TM);
OutStreamer->switchSection(TheSection);
emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer());
emitGlobalConstant(GV->getDataLayout(), GV->getInitializer());
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeDirectXAsmPrinter() {

2
llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
View File

@ -31,7 +31,7 @@ class DirectXTTIImpl : public BasicTTIImplBase<DirectXTTIImpl> {
public:
explicit DirectXTTIImpl(const DirectXTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
unsigned getMinVectorRegisterBitWidth() const { return 32; }
};

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -2110,7 +2110,7 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::hexagon_L2_loadrb_pbr:
case Intrinsic::hexagon_L2_loadrub_pbr: {
Info.opc = ISD::INTRINSIC_W_CHAIN;
auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
auto &DL = I.getDataLayout();
auto &Cont = I.getCalledFunction()->getParent()->getContext();
// The intrinsic function call is of the form { ElTy, i8* }
// @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type

4
llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
View File

@ -254,7 +254,7 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO,
}
}
unsigned Size = GVar->getParent()->getDataLayout().getTypeAllocSize(GType);
unsigned Size = GVar->getDataLayout().getTypeAllocSize(GType);
if (Size == 0) {
LLVM_DEBUG(dbgs() << "no, has size 0\n");
return false;
@ -317,7 +317,7 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty,
case Type::FloatTyID:
case Type::DoubleTyID:
case Type::IntegerTyID: {
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
// It is unfortunate that DL's function take non-const Type*.
return DL.getTypeAllocSize(const_cast<Type*>(Ty));
}

2
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
View File

@ -52,7 +52,7 @@ class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
public:
explicit HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()),
: BaseT(TM, F.getDataLayout()),
ST(*TM->getSubtargetImpl(F)), TLI(*ST.getTargetLowering()) {}
/// \name Scalar TTI Implementations

2
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
View File

@ -74,7 +74,7 @@ public:
HexagonVectorCombine(Function &F_, AliasAnalysis &AA_, AssumptionCache &AC_,
DominatorTree &DT_, ScalarEvolution &SE_,
TargetLibraryInfo &TLI_, const TargetMachine &TM_)
: F(F_), DL(F.getParent()->getDataLayout()), AA(AA_), AC(AC_), DT(DT_),
: F(F_), DL(F.getDataLayout()), AA(AA_), AC(AC_), DT(DT_),
SE(SE_), TLI(TLI_),
HST(static_cast<const HexagonSubtarget &>(*TM_.getSubtargetImpl(F))) {}

2
llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp
View File

@ -95,7 +95,7 @@ bool LanaiTargetObjectFile::isGlobalInSmallSectionImpl(
Type *Ty = GVA->getValueType();
return isInSmallSection(
GVA->getParent()->getDataLayout().getTypeAllocSize(Ty));
GVA->getDataLayout().getTypeAllocSize(Ty));
}
MCSection *LanaiTargetObjectFile::SelectSectionForGlobal(

2
llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
View File

@ -38,7 +38,7 @@ class LanaiTTIImpl : public BasicTTIImplBase<LanaiTTIImpl> {
public:
explicit LanaiTTIImpl(const LanaiTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
bool shouldBuildLookupTables() const { return false; }

2
llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
View File

@ -37,7 +37,7 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
public:
explicit LoongArchTTIImpl(const LoongArchTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;

6
llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
View File

@ -103,7 +103,7 @@ bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
CCAssignFn *AssignFn =
TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
if (!VRegs.empty()) {
SmallVector<ArgInfo, 8> SplitArgs;
ArgInfo OrigArg{VRegs, Val->getType(), 0};
@ -125,7 +125,7 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
FunctionLoweringInfo &FLI) const {
MachineFunction &MF = MIRBuilder.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
const auto &DL = F.getParent()->getDataLayout();
const auto &DL = F.getDataLayout();
auto &TLI = *getTLI<M68kTargetLowering>();
SmallVector<ArgInfo, 8> SplitArgs;
@ -191,7 +191,7 @@ bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MachineFunction &MF = MIRBuilder.getMF();
Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
const TargetInstrInfo &TII = *STI.getInstrInfo();

2
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -287,7 +287,7 @@ MipsTargetMachine::getTargetTransformInfo(const Function &F) const {
if (Subtarget->allowMixed16_32()) {
LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
// FIXME: This is no longer necessary as the TTI returned is per-function.
return TargetTransformInfo(F.getParent()->getDataLayout());
return TargetTransformInfo(F.getDataLayout());
}
LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");

2
llvm/lib/Target/Mips/MipsTargetObjectFile.cpp
View File

@ -143,7 +143,7 @@ IsGlobalInSmallSectionImpl(const GlobalObject *GO,
return false;
return IsInSmallSection(
GVA->getParent()->getDataLayout().getTypeAllocSize(Ty));
GVA->getDataLayout().getTypeAllocSize(Ty));
}
MCSection *MipsTargetObjectFile::SelectSectionForGlobal(

2
llvm/lib/Target/Mips/MipsTargetTransformInfo.h
View File

@ -29,7 +29,7 @@ class MipsTTIImpl : public BasicTTIImplBase<MipsTTIImpl> {
public:
explicit MipsTTIImpl(const MipsTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
bool hasDivRemOp(Type *DataType, bool IsSigned);

2
llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
View File

@ -60,7 +60,7 @@ bool NVPTXLowerAggrCopies::runOnFunction(Function &F) {
SmallVector<LoadInst *, 4> AggrLoads;
SmallVector<MemIntrinsic *, 4> MemCalls;
const DataLayout &DL = F.getParent()->getDataLayout();
const DataLayout &DL = F.getDataLayout();
LLVMContext &Context = F.getParent()->getContext();
const TargetTransformInfo &TTI =
getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);

2
llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
View File

@ -369,7 +369,7 @@ void NVPTXLowerArgs::handleByValParam(const NVPTXTargetMachine &TM,
return;
}
const DataLayout &DL = Func->getParent()->getDataLayout();
const DataLayout &DL = Func->getDataLayout();
unsigned AS = DL.getAllocaAddrSpace();
if (isParamGridConstant(*Arg)) {
// Writes to a grid constant are undefined behaviour. We do not need a

2
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
View File

@ -38,7 +38,7 @@ class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
public:
explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl()),
TLI(ST->getTargetLowering()) {}
bool hasBranchDivergence(const Function *F = nullptr) { return true; }

2
llvm/lib/Target/NVPTX/NVVMReflect.cpp
View File

@ -192,7 +192,7 @@ static bool runNVVMReflect(Function &F, unsigned SmVersion) {
while (!ToSimplify.empty()) {
Instruction *I = ToSimplify.pop_back_val();
if (Constant *C =
ConstantFoldInstruction(I, F.getParent()->getDataLayout())) {
ConstantFoldInstruction(I, F.getDataLayout())) {
for (User *U : I->users())
if (Instruction *I = dyn_cast<Instruction>(U))
ToSimplify.push_back(I);

4
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
View File

@ -80,7 +80,7 @@ bool PPCCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &DL = F.getParent()->getDataLayout();
auto &DL = F.getDataLayout();
if (!VRegs.empty()) {
// Setup the information about the return value.
ArgInfo OrigArg{VRegs, Val->getType(), 0};
@ -117,7 +117,7 @@ bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
FunctionLoweringInfo &FLI) const {
MachineFunction &MF = MIRBuilder.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
const auto &DL = F.getParent()->getDataLayout();
const auto &DL = F.getDataLayout();
auto &TLI = *getTLI<PPCTargetLowering>();
// Loop over each arg, set flags and split to single value types

14
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -1613,7 +1613,7 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
}
const MachineOperand &MO = MI->getOperand(OpNum);
if (MO.isGlobal()) {
const DataLayout &DL = MO.getGlobal()->getParent()->getDataLayout();
const DataLayout &DL = MO.getGlobal()->getDataLayout();
if (MO.getGlobal()->getPointerAlignment(DL) < 4)
llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
}
@ -2732,7 +2732,7 @@ static void tocDataChecks(unsigned PointerSize, const GlobalVariable *GV) {
Type *GVType = GV->getValueType();
assert(GVType->isSized() && "A GlobalVariable's size must be known to be "
"supported by the toc data transformation.");
if (GV->getParent()->getDataLayout().getTypeSizeInBits(GVType) >
if (GV->getDataLayout().getTypeSizeInBits(GVType) >
PointerSize * 8)
report_fatal_error(
"A GlobalVariable with size larger than a TOC entry is not currently "
@ -2750,7 +2750,7 @@ void PPCAIXAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
// If the Global Variable has the toc-data attribute, it needs to be emitted
// when we emit the .toc section.
if (GV->hasAttribute("toc-data")) {
unsigned PointerSize = GV->getParent()->getDataLayout().getPointerSize();
unsigned PointerSize = GV->getDataLayout().getPointerSize();
tocDataChecks(PointerSize, GV);
TOCDataGlobalVars.push_back(GV);
return;
@ -2794,7 +2794,7 @@ void PPCAIXAsmPrinter::emitGlobalVariableHelper(const GlobalVariable *GV) {
// Switch to the containing csect.
OutStreamer->switchSection(Csect);
const DataLayout &DL = GV->getParent()->getDataLayout();
const DataLayout &DL = GV->getDataLayout();
// Handle common and zero-initialized local symbols.
if (GV->hasCommonLinkage() || GVKind.isBSSLocal() ||
@ -2837,7 +2837,7 @@ void PPCAIXAsmPrinter::emitGlobalVariableHelper(const GlobalVariable *GV) {
// No alias to emit.
if (!GOAliasMap[GV].size()) {
emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer());
emitGlobalConstant(GV->getDataLayout(), GV->getInitializer());
return;
}
@ -2848,7 +2848,7 @@ void PPCAIXAsmPrinter::emitGlobalVariableHelper(const GlobalVariable *GV) {
AliasList[getAliasOffset(GA->getAliasee())].push_back(GA);
// Emit alias label and element value for global variable.
emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer(),
emitGlobalConstant(GV->getDataLayout(), GV->getInitializer(),
&AliasList);
}
@ -3007,7 +3007,7 @@ bool PPCAIXAsmPrinter::doInitialization(Module &M) {
MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(
getObjFileLowering().SectionForGlobal(GO, GOKind, TM));
Align GOAlign = getGVAlignment(GO, GO->getParent()->getDataLayout());
Align GOAlign = getGVAlignment(GO, GO->getDataLayout());
Csect->ensureMinAlignment(GOAlign);
};

8
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -3467,7 +3467,7 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
IsTLSLocalExecModel) {
Type *GVType = GV->getValueType();
if (GVType->isSized() && !GVType->isEmptyTy() &&
GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
GV->getDataLayout().getTypeAllocSize(GVType) <=
AIXSmallTlsPolicySizeLimit)
return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA, TLSReg);
}
@ -3530,7 +3530,7 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
if (HasAIXSmallLocalDynamicTLS) {
Type *GVType = GV->getValueType();
if (GVType->isSized() && !GVType->isEmptyTy() &&
GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
GV->getDataLayout().getTypeAllocSize(GVType) <=
AIXSmallTlsPolicySizeLimit)
return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA,
ModuleHandle);
@ -5873,7 +5873,7 @@ bool PPCTargetLowering::supportsTailCallFor(const CallBase *CB) const {
GetReturnInfo(CalleeCC, CalleeFunc->getReturnType(),
CalleeFunc->getAttributes(), Outs, *this,
CalleeFunc->getParent()->getDataLayout());
CalleeFunc->getDataLayout());
return isEligibleForTCO(CalleeGV, CalleeCC, CallerCC, CB,
CalleeFunc->isVarArg(), Outs, Ins, CallerFunc,
@ -17543,7 +17543,7 @@ bool PPCTargetLowering::isProfitableToHoist(Instruction *I) const {
const TargetOptions &Options = getTargetMachine().Options;
const Function *F = I->getFunction();
const DataLayout &DL = F->getParent()->getDataLayout();
const DataLayout &DL = F->getDataLayout();
Type *Ty = User->getOperand(0)->getType();
return !(

2
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -4519,7 +4519,7 @@ bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
// load. A DForm load cannot be represented if it is a multiple of say 2.
// XForm loads do not have this restriction.
if (ImmMO.isGlobal()) {
const DataLayout &DL = ImmMO.getGlobal()->getParent()->getDataLayout();
const DataLayout &DL = ImmMO.getGlobal()->getDataLayout();
if (ImmMO.getGlobal()->getPointerAlignment(DL) < III.ImmMustBeMultipleOf)
return false;
}

2
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
View File

@ -37,7 +37,7 @@ class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
public:
explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
std::optional<Instruction *> instCombineIntrinsic(InstCombiner & IC,

2
llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
View File

@ -163,7 +163,7 @@ bool RISCVCodeGenPrepare::runOnFunction(Function &F) {
auto &TM = TPC.getTM<RISCVTargetMachine>();
ST = &TM.getSubtarget<RISCVSubtarget>(F);
DL = &F.getParent()->getDataLayout();
DL = &F.getDataLayout();
bool MadeChange = false;
for (auto &BB : F)

2
llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
View File

@ -548,7 +548,7 @@ bool RISCVGatherScatterLowering::runOnFunction(Function &F) {
return false;
TLI = ST->getTargetLowering();
DL = &F.getParent()->getDataLayout();
DL = &F.getDataLayout();
LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
StridedAddrs.clear();

2
llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
View File

@ -98,7 +98,7 @@ bool RISCVELFTargetObjectFile::isGlobalInSmallSection(
return false;
return isInSmallSection(
GVA->getParent()->getDataLayout().getTypeAllocSize(Ty));
GVA->getDataLayout().getTypeAllocSize(Ty));
}
MCSection *RISCVELFTargetObjectFile::SelectSectionForGlobal(

2
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
View File

@ -57,7 +57,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
TTI::TargetCostKind CostKind);
public:
explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
bool areInlineCompatible(const Function *Caller,

Some files were not shown because too many files have changed in this diff Show More