[llvm][CodeGen] avoid repeated interval calculation in window scheduler (#132352)
Some new registers are reused when replacing some old ones in certain use case of ModuloScheduleExpander. It is necessary to avoid repeated interval calculations for these registers. (cherry picked from commit 7e65944292278cc245e36cc6ca971654d584012d)
This commit is contained in:
Hua Tian
Tom Stellard
parent
d88cd35023
commit
a141e58685
@ -188,9 +188,6 @@ private:
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/// Instructions to change when emitting the final schedule.
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InstrChangesTy InstrChanges;
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/// Record the registers that need to compute live intervals.
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SmallVector<Register> NoIntervalRegs;
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void generatePipelinedLoop();
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void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,
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ValueMapTy *VRMap, MBBVectorTy &PrologBBs);
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@ -214,7 +211,6 @@ private:
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void addBranches(MachineBasicBlock &PreheaderBB, MBBVectorTy &PrologBBs,
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MachineBasicBlock *KernelBB, MBBVectorTy &EpilogBBs,
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ValueMapTy *VRMap);
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void calculateIntervals();
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bool computeDelta(MachineInstr &MI, unsigned &Delta);
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void updateMemOperands(MachineInstr &NewMI, MachineInstr &OldMI,
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unsigned Num);
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@ -181,10 +181,6 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
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// Add branches between prolog and epilog blocks.
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addBranches(*Preheader, PrologBBs, KernelBB, EpilogBBs, VRMap);
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// The intervals of newly created virtual registers are calculated after the
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// kernel expansion.
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calculateIntervals();
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delete[] VRMap;
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delete[] VRMapPhi;
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}
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@ -546,10 +542,8 @@ void ModuloScheduleExpander::generateExistingPhis(
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if (VRMap[LastStageNum - np - 1].count(LoopVal))
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PhiOp2 = VRMap[LastStageNum - np - 1][LoopVal];
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if (IsLast && np == NumPhis - 1) {
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if (IsLast && np == NumPhis - 1)
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replaceRegUsesAfterLoop(Def, NewReg, BB, MRI);
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NoIntervalRegs.push_back(NewReg);
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}
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continue;
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}
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}
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@ -589,10 +583,8 @@ void ModuloScheduleExpander::generateExistingPhis(
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// Check if we need to rename any uses that occurs after the loop. The
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// register to replace depends on whether the Phi is scheduled in the
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// epilog.
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if (IsLast && np == NumPhis - 1) {
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if (IsLast && np == NumPhis - 1)
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replaceRegUsesAfterLoop(Def, NewReg, BB, MRI);
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NoIntervalRegs.push_back(NewReg);
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}
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// In the kernel, a dependent Phi uses the value from this Phi.
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if (InKernel)
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@ -612,10 +604,8 @@ void ModuloScheduleExpander::generateExistingPhis(
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if (NumStages == 0 && IsLast) {
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auto &CurStageMap = VRMap[CurStageNum];
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auto It = CurStageMap.find(LoopVal);
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if (It != CurStageMap.end()) {
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if (It != CurStageMap.end())
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replaceRegUsesAfterLoop(Def, It->second, BB, MRI);
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NoIntervalRegs.push_back(It->second);
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}
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}
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}
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}
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@ -735,10 +725,8 @@ void ModuloScheduleExpander::generatePhis(
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rewriteScheduledInstr(NewBB, InstrMap, CurStageNum, np, &*BBI, Def,
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NewReg);
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}
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if (IsLast && np == NumPhis - 1) {
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if (IsLast && np == NumPhis - 1)
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replaceRegUsesAfterLoop(Def, NewReg, BB, MRI);
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NoIntervalRegs.push_back(NewReg);
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}
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}
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}
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}
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@ -950,14 +938,6 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
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}
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}
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/// Some registers are generated during the kernel expansion. We calculate the
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/// live intervals of these registers after the expansion.
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void ModuloScheduleExpander::calculateIntervals() {
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for (Register Reg : NoIntervalRegs)
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LIS.createAndComputeVirtRegInterval(Reg);
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NoIntervalRegs.clear();
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}
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/// Return true if we can compute the amount the instruction changes
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/// during each iteration. Set Delta to the amount of the change.
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bool ModuloScheduleExpander::computeDelta(MachineInstr &MI, unsigned &Delta) {
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@ -1078,10 +1058,8 @@ void ModuloScheduleExpander::updateInstruction(MachineInstr *NewMI,
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Register NewReg = MRI.createVirtualRegister(RC);
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MO.setReg(NewReg);
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VRMap[CurStageNum][reg] = NewReg;
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if (LastDef) {
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if (LastDef)
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replaceRegUsesAfterLoop(reg, NewReg, BB, MRI);
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NoIntervalRegs.push_back(NewReg);
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}
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} else if (MO.isUse()) {
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MachineInstr *Def = MRI.getVRegDef(reg);
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// Compute the stage that contains the last definition for instruction.
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103
llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir
Normal file
103
llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir
Normal file
@ -0,0 +1,103 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc --mtriple=aarch64 %s -run-pass=pipeliner -o - | FileCheck %s
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...
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---
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name: foo
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: foo
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FMOVD0_]], [[FMOVD0_]], implicit $fpcr
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; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = nsw SUBSXri [[SUBREG_TO_REG]], 1, 0, implicit-def $nzcv
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[SUBSXri]]
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; CHECK-NEXT: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
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; CHECK-NEXT: Bcc 0, %bb.7, implicit $nzcv
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; CHECK-NEXT: B %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.5(0x80000000), %bb.6(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[FADDDrr1:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr]], [[FMOVD0_]], implicit $fpcr
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; CHECK-NEXT: [[FADDDrr2:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FMOVD0_]], [[FMOVD0_]], implicit $fpcr
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; CHECK-NEXT: [[SUBSXri1:%[0-9]+]]:gpr64 = nsw SUBSXri [[COPY1]], 1, 0, implicit-def $nzcv
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[SUBSXri1]]
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; CHECK-NEXT: [[FMOVDi1:%[0-9]+]]:fpr64 = FMOVDi 112
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; CHECK-NEXT: Bcc 0, %bb.6, implicit $nzcv
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; CHECK-NEXT: B %bb.5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.5(0x7c000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY2]], %bb.4, %24, %bb.5
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:fpr64 = PHI [[FMOVDi1]], %bb.4, %25, %bb.5
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; CHECK-NEXT: [[PHI2:%[0-9]+]]:fpr64 = PHI [[FMOVDi]], %bb.4, [[PHI1]], %bb.5
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; CHECK-NEXT: [[PHI3:%[0-9]+]]:fpr64 = PHI [[FADDDrr2]], %bb.4, %22, %bb.5
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; CHECK-NEXT: [[PHI4:%[0-9]+]]:fpr64 = PHI [[FADDDrr1]], %bb.4, %23, %bb.5
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; CHECK-NEXT: [[SUBSXri2:%[0-9]+]]:gpr64 = nsw SUBSXri [[PHI]], 1, 0, implicit-def $nzcv
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; CHECK-NEXT: [[FADDDrr3:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI2]], [[FMOVD0_]], implicit $fpcr
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; CHECK-NEXT: [[FADDDrr4:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI3]], [[PHI2]], implicit $fpcr
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[SUBSXri2]]
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; CHECK-NEXT: STRDui [[PHI4]], [[COPY]], 0
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; CHECK-NEXT: [[FMOVDi2:%[0-9]+]]:fpr64 = FMOVDi 112
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; CHECK-NEXT: Bcc 1, %bb.5, implicit $nzcv
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; CHECK-NEXT: B %bb.6
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6:
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; CHECK-NEXT: successors: %bb.7(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI5:%[0-9]+]]:fpr64 = PHI [[FMOVDi]], %bb.4, [[PHI1]], %bb.5
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; CHECK-NEXT: [[PHI6:%[0-9]+]]:fpr64 = PHI [[FADDDrr2]], %bb.4, [[FADDDrr3]], %bb.5
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; CHECK-NEXT: [[PHI7:%[0-9]+]]:fpr64 = PHI [[FADDDrr1]], %bb.4, [[FADDDrr4]], %bb.5
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; CHECK-NEXT: STRDui [[PHI7]], [[COPY]], 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI8:%[0-9]+]]:fpr64 = PHI [[FMOVD0_]], %bb.3, [[PHI5]], %bb.6
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; CHECK-NEXT: [[PHI9:%[0-9]+]]:fpr64 = PHI [[FADDDrr]], %bb.3, [[PHI6]], %bb.6
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; CHECK-NEXT: [[FADDDrr5:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI9]], [[PHI8]], implicit $fpcr
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; CHECK-NEXT: STRDui [[FADDDrr5]], [[COPY]], 0
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.1(0x80000000)
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liveins: $x0
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%0:gpr64common = COPY $x0
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%1:fpr64 = FMOVD0
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%2:gpr32 = MOVi32imm 1
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%3:gpr64all = SUBREG_TO_REG 0, killed %2, %subreg.sub_32
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bb.1:
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successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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%4:gpr64sp = PHI %3, %bb.0, %5, %bb.1
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%6:fpr64 = PHI %1, %bb.0, %7, %bb.1
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%8:fpr64 = PHI %1, %bb.0, %6, %bb.1
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%9:fpr64 = nofpexcept FADDDrr %8, %1, implicit $fpcr
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%10:fpr64 = nofpexcept FADDDrr killed %9, %6, implicit $fpcr
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STRDui killed %10, %0, 0
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%11:gpr64 = nsw SUBSXri %4, 1, 0, implicit-def $nzcv
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%5:gpr64all = COPY %11
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%7:fpr64 = FMOVDi 112
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Bcc 1, %bb.1, implicit $nzcv
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B %bb.2
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bb.2:
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RET_ReallyLR
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...
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