Revert "[SeparateConstOffsetFromGEP] Decompose constant xor operand if possible" (#179339)
A miscompile was found (see #175724), and it's complicated to fix. We're going to revert for now, and look at reimplementing a fixed version later.
This commit is contained in:
Eli Friedman
GitHub
parent
139e2fb602
commit
a2c7c6032f
@ -295,10 +295,6 @@ private:
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bool CanTraceInto(bool SignExtended, bool ZeroExtended, BinaryOperator *BO,
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bool NonNegative);
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/// Analyze XOR instruction to extract disjoint constant bits that behave
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/// like addition operations for improved address mode folding.
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APInt extractDisjointBitsFromXor(BinaryOperator *XorInst);
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/// The path from the constant offset to the old GEP index. e.g., if the GEP
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/// index is "a * b + (c + 5)". After running function find, UserChain[0] will
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/// be the constant 5, UserChain[1] will be the subexpression "c + 5", and
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@ -601,9 +597,6 @@ APInt ConstantOffsetExtractor::find(Value *V, bool SignExtended,
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// Trace into subexpressions for more hoisting opportunities.
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if (CanTraceInto(SignExtended, ZeroExtended, BO, NonNegative))
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ConstantOffset = findInEitherOperand(BO, SignExtended, ZeroExtended);
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// Handle XOR with disjoint bits that can be treated as addition.
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else if (BO->getOpcode() == Instruction::Xor)
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ConstantOffset = extractDisjointBitsFromXor(BO);
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} else if (isa<TruncInst>(V)) {
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ConstantOffset =
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find(U->getOperand(0), SignExtended, ZeroExtended, NonNegative)
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@ -723,20 +716,11 @@ Value *ConstantOffsetExtractor::removeConstOffset(unsigned ChainIndex) {
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Value *NextInChain = removeConstOffset(ChainIndex - 1);
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Value *TheOther = BO->getOperand(1 - OpNo);
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// If NextInChain is 0 and not the LHS of a sub, we can simplify the
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// sub-expression to be just TheOther.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(NextInChain)) {
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if (CI->isZero()) {
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// Custom XOR handling for disjoint bits - preserves original XOR
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// with non-disjoint constant bits.
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// TODO: The design should be updated to support partial constant
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// extraction.
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if (BO->getOpcode() == Instruction::Xor)
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return BO;
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// If NextInChain is 0 and not the LHS of a sub, we can simplify the
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// sub-expression to be just TheOther.
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if (!(BO->getOpcode() == Instruction::Sub && OpNo == 0))
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return TheOther;
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}
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if (CI->isZero() && !(BO->getOpcode() == Instruction::Sub && OpNo == 0))
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return TheOther;
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}
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BinaryOperator::BinaryOps NewOp = BO->getOpcode();
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@ -767,67 +751,6 @@ Value *ConstantOffsetExtractor::removeConstOffset(unsigned ChainIndex) {
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return NewBO;
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}
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/// Analyze XOR instruction to extract disjoint constant bits for address
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/// folding
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///
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/// This function identifies bits in an XOR constant operand that are disjoint
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/// from the base operand's known set bits. For these disjoint bits, XOR behaves
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/// identically to addition, allowing us to extract them as constant offsets
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/// that can be folded into addressing modes.
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///
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/// Transformation: `Base ^ Const` becomes `(Base ^ NonDisjointBits) +
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/// DisjointBits` where DisjointBits = Const & KnownZeros(Base)
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///
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/// Example with ptr having known-zero low bit:
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/// Original: `xor %ptr, 3` ; 3 = 0b11
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/// Analysis: DisjointBits = 3 & KnownZeros(%ptr) = 0b11 & 0b01 = 0b01
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/// Result: `(xor %ptr, 2) + 1` where 1 can be folded into address mode
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///
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/// \param XorInst The XOR binary operator to analyze
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/// \return APInt containing the disjoint bits that can be extracted as offset,
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/// or zero if no disjoint bits exist
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APInt ConstantOffsetExtractor::extractDisjointBitsFromXor(
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BinaryOperator *XorInst) {
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assert(XorInst && XorInst->getOpcode() == Instruction::Xor &&
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"Expected XOR instruction");
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const unsigned BitWidth = XorInst->getType()->getScalarSizeInBits();
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Value *BaseOperand;
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ConstantInt *XorConstant;
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// Match pattern: xor BaseOperand, Constant.
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if (!match(XorInst, m_Xor(m_Value(BaseOperand), m_ConstantInt(XorConstant))))
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return APInt::getZero(BitWidth);
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// Compute known bits for the base operand.
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const SimplifyQuery SQ(DL);
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const KnownBits BaseKnownBits = computeKnownBits(BaseOperand, SQ);
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const APInt &ConstantValue = XorConstant->getValue();
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// Identify disjoint bits: constant bits that are known zero in base.
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const APInt DisjointBits = ConstantValue & BaseKnownBits.Zero;
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// Early exit if no disjoint bits found.
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if (DisjointBits.isZero())
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return APInt::getZero(BitWidth);
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// Compute the remaining non-disjoint bits that stay in the XOR.
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const APInt NonDisjointBits = ConstantValue & ~DisjointBits;
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// FIXME: Enhance XOR constant extraction to handle nested binary operations.
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// Currently we only extract disjoint bits from the immediate XOR constant,
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// but we could recursively process cases like:
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// xor (add %base, C1), C2 -> add %base, (C1 ^ disjoint_bits(C2))
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// This requires careful analysis to ensure the transformation preserves
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// semantics, particularly around sign extension and overflow behavior.
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// Add the non-disjoint constant to the user chain for later transformation
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// This will replace the original constant in the XOR with the new
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// constant.
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UserChain.push_back(ConstantInt::get(XorInst->getType(), NonDisjointBits));
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return DisjointBits;
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}
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/// A helper function to check if reassociating through an entry in the user
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/// chain would invalidate the GEP's nuw flag.
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static bool allowsPreservingNUW(const User *U) {
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@ -1,435 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; Test the xor with constant operand is decomposed in to gep.
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep \
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; RUN: -S < %s | FileCheck %s
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; Test the gvn pass eliminates the redundant xor instructions from decomposition.
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep,gvn \
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; RUN: -S < %s | FileCheck --check-prefix=GVN %s
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; Check that disjoint constants are properly extracted and folded into GEP
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; addressing modes and GVN to eliminate redundant computations
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define amdgpu_kernel void @test1(i1 %0, ptr addrspace(3) %1) {
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; CHECK-LABEL: define amdgpu_kernel void @test1(
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; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
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; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192
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; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 16384
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; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP12]], i32 24576
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; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
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; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
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; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16
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; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 16
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; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]]
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; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]]
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; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]]
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; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16
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; CHECK-NEXT: ret void
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;
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; GVN-LABEL: define amdgpu_kernel void @test1(
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; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
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; GVN-NEXT: [[ENTRY:.*:]]
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; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
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; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
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; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
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; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192
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; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384
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; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576
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; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
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; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
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; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
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; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
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; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]
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; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]]
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; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]]
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; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16
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; GVN-NEXT: ret void
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;
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entry:
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%2 = select i1 %0, i32 0, i32 288
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%3 = xor i32 %2, 32
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%4 = xor i32 %2, 4128
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%5 = xor i32 %2, 8224
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%6 = xor i32 %2, 12320
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%7 = getelementptr half, ptr addrspace(3) %1, i32 %3
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%8 = getelementptr half, ptr addrspace(3) %1, i32 %4
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%9 = getelementptr half, ptr addrspace(3) %1, i32 %5
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%10 = getelementptr half, ptr addrspace(3) %1, i32 %6
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%11 = load <8 x half>, ptr addrspace(3) %7, align 16
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%12 = load <8 x half>, ptr addrspace(3) %8, align 16
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%13 = load <8 x half>, ptr addrspace(3) %9, align 16
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%14 = load <8 x half>, ptr addrspace(3) %10, align 16
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%15 = fadd <8 x half> %11, %12
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%16 = fadd <8 x half> %13, %14
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%17 = fadd <8 x half> %15, %16
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store <8 x half> %17, ptr addrspace(3) %1, align 16
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ret void
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}
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; Check that disjoint constants are properly extracted and folded into GEP
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; addressing modes and GVN to eliminate redundant computations
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define amdgpu_kernel void @test2(i1 %0, ptr addrspace(3) %1) {
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; CHECK-LABEL: define amdgpu_kernel void @test2(
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; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
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; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP5]], i32 24576
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; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP7]]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP8]], i32 16384
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; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP10]]
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP11]], i32 8192
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
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; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
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; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP9]], align 16
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; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP12]], align 16
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; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 16
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; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]]
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; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]]
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; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]]
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; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16
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; CHECK-NEXT: ret void
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;
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; GVN-LABEL: define amdgpu_kernel void @test2(
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; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
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; GVN-NEXT: [[ENTRY:.*:]]
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; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
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; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
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; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
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; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576
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; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384
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; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192
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; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
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; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
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; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
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; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
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; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]
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; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]]
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; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]]
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; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16
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; GVN-NEXT: ret void
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;
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entry:
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%2 = select i1 %0, i32 0, i32 288
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%3 = xor i32 %2, 12320
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%4 = xor i32 %2, 8224
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%5 = xor i32 %2, 4128
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%6 = xor i32 %2, 32
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%7 = getelementptr half, ptr addrspace(3) %1, i32 %3
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%8 = getelementptr half, ptr addrspace(3) %1, i32 %4
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%9 = getelementptr half, ptr addrspace(3) %1, i32 %5
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%10 = getelementptr half, ptr addrspace(3) %1, i32 %6
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%11 = load <8 x half>, ptr addrspace(3) %7, align 16
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%12 = load <8 x half>, ptr addrspace(3) %8, align 16
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%13 = load <8 x half>, ptr addrspace(3) %9, align 16
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%14 = load <8 x half>, ptr addrspace(3) %10, align 16
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%15 = fadd <8 x half> %11, %12
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%16 = fadd <8 x half> %13, %14
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%17 = fadd <8 x half> %15, %16
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store <8 x half> %17, ptr addrspace(3) %1, align 16
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ret void
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}
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; Verify that xor instructions with different non-disjoint constants are optimized
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define amdgpu_kernel void @test3(i1 %0, ptr addrspace(3) %1) {
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; CHECK-LABEL: define amdgpu_kernel void @test3(
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; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
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; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096
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; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 8192
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; CHECK-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
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; CHECK-NEXT: [[TMP12:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
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; CHECK-NEXT: [[TMP13:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16
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; CHECK-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]]
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; CHECK-NEXT: [[TMP15:%.*]] = fadd <8 x half> [[TMP13]], [[TMP14]]
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; CHECK-NEXT: store <8 x half> [[TMP15]], ptr addrspace(3) [[TMP1]], align 16
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; CHECK-NEXT: ret void
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;
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; GVN-LABEL: define amdgpu_kernel void @test3(
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; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
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; GVN-NEXT: [[ENTRY:.*:]]
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; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
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; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
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; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
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; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288
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; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]
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; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096
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; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192
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; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
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; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
|
||||
; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16
|
||||
; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]
|
||||
; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]]
|
||||
; GVN-NEXT: store <8 x half> [[TMP13]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; GVN-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%2 = select i1 %0, i32 0, i32 288
|
||||
%3 = xor i32 %2, 32
|
||||
%4 = xor i32 %2, 2336
|
||||
%5 = xor i32 %2, 4128
|
||||
%6 = getelementptr half, ptr addrspace(3) %1, i32 %3
|
||||
%7 = getelementptr half, ptr addrspace(3) %1, i32 %4
|
||||
%8 = getelementptr half, ptr addrspace(3) %1, i32 %5
|
||||
%9 = load <8 x half>, ptr addrspace(3) %6, align 16
|
||||
%10 = load <8 x half>, ptr addrspace(3) %7, align 16
|
||||
%11 = load <8 x half>, ptr addrspace(3) %8, align 16
|
||||
%12 = fadd <8 x half> %9, %10
|
||||
%13 = fadd <8 x half> %11, %12
|
||||
store <8 x half> %13, ptr addrspace(3) %1, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; Verify that no optimization occurs when disjoint constants are absent
|
||||
define amdgpu_kernel void @test4(i1 %0, ptr addrspace(3) %1) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @test4(
|
||||
; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; CHECK-NEXT: [[ENTRY:.*:]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]
|
||||
; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GVN-LABEL: define amdgpu_kernel void @test4(
|
||||
; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; GVN-NEXT: [[ENTRY:.*:]]
|
||||
; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288
|
||||
; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]
|
||||
; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
|
||||
; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
|
||||
; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]
|
||||
; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; GVN-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%2 = select i1 %0, i32 0, i32 288
|
||||
%3 = xor i32 %2, 32
|
||||
%4 = xor i32 %2, 288
|
||||
%5 = getelementptr half, ptr addrspace(3) %1, i32 %3
|
||||
%6 = getelementptr half, ptr addrspace(3) %1, i32 %4
|
||||
%7 = load <8 x half>, ptr addrspace(3) %5, align 16
|
||||
%8 = load <8 x half>, ptr addrspace(3) %6, align 16
|
||||
%9 = fadd <8 x half> %7, %8
|
||||
store <8 x half> %9, ptr addrspace(3) %1, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Verify that XOR-BinOp-GEP usage chains are properly optimized
|
||||
define amdgpu_kernel void @test5(i1 %0, ptr addrspace(3) %1) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @test5(
|
||||
; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; CHECK-NEXT: [[ENTRY:.*:]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 256
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]
|
||||
; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GVN-LABEL: define amdgpu_kernel void @test5(
|
||||
; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; GVN-NEXT: [[ENTRY:.*:]]
|
||||
; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; GVN-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], 256
|
||||
; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]
|
||||
; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192
|
||||
; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16
|
||||
; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
|
||||
; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]
|
||||
; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; GVN-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%2 = select i1 %0, i32 0, i32 288
|
||||
%3 = xor i32 %2, 32
|
||||
%4 = xor i32 %2, 4128
|
||||
%5 = add i32 %4, 256
|
||||
%6 = getelementptr half, ptr addrspace(3) %1, i32 %3
|
||||
%7 = getelementptr half, ptr addrspace(3) %1, i32 %5
|
||||
%8 = load <8 x half>, ptr addrspace(3) %6, align 16
|
||||
%9 = load <8 x half>, ptr addrspace(3) %7, align 16
|
||||
%10 = fadd <8 x half> %8, %9
|
||||
store <8 x half> %10, ptr addrspace(3) %1, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; Verify that BinOp-XOR-GEP usage chains are properly optimized.
|
||||
; In the below test, make sure we stop processing the chain at xor
|
||||
; and not fold the constant from add instruction in to gep. The
|
||||
; constant from add can be folded and the future work will cover
|
||||
; these cases.
|
||||
define amdgpu_kernel void @test6(i1 %0, ptr addrspace(3) %1) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @test6(
|
||||
; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; CHECK-NEXT: [[ENTRY:.*:]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]
|
||||
; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GVN-LABEL: define amdgpu_kernel void @test6(
|
||||
; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; GVN-NEXT: [[ENTRY:.*:]]
|
||||
; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256
|
||||
; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; GVN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32
|
||||
; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]]
|
||||
; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192
|
||||
; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
|
||||
; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16
|
||||
; GVN-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]
|
||||
; GVN-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; GVN-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%2 = select i1 %0, i32 0, i32 288
|
||||
%3 = xor i32 %2, 32
|
||||
%4 = add i32 %2, 256
|
||||
%5 = xor i32 %4, 4128
|
||||
%6 = getelementptr half, ptr addrspace(3) %1, i32 %3
|
||||
%7 = getelementptr half, ptr addrspace(3) %1, i32 %5
|
||||
%8 = load <8 x half>, ptr addrspace(3) %6, align 16
|
||||
%9 = load <8 x half>, ptr addrspace(3) %7, align 16
|
||||
%10 = fadd <8 x half> %8, %9
|
||||
store <8 x half> %10, ptr addrspace(3) %1, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; Verify that BinOp-XOR-GEP usage chains with non disjoint xor works as
|
||||
; intended.
|
||||
define amdgpu_kernel void @test6a(i1 %0, ptr addrspace(3) %1) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @test6a(
|
||||
; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; CHECK-NEXT: [[ENTRY:.*:]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]
|
||||
; CHECK-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GVN-LABEL: define amdgpu_kernel void @test6a(
|
||||
; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; GVN-NEXT: [[ENTRY:.*:]]
|
||||
; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256
|
||||
; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288
|
||||
; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]
|
||||
; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
|
||||
; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16
|
||||
; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]
|
||||
; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; GVN-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%2 = select i1 %0, i32 0, i32 288
|
||||
%3 = xor i32 %2, 32
|
||||
%4 = add i32 %2, 256
|
||||
%5 = xor i32 %4, 288
|
||||
%6 = getelementptr half, ptr addrspace(3) %1, i32 %3
|
||||
%7 = getelementptr half, ptr addrspace(3) %1, i32 %5
|
||||
%8 = load <8 x half>, ptr addrspace(3) %6, align 16
|
||||
%9 = load <8 x half>, ptr addrspace(3) %7, align 16
|
||||
%10 = fadd <8 x half> %8, %9
|
||||
store <8 x half> %10, ptr addrspace(3) %1, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; Ensure disjoint constants exceeding addressing mode limits (e.g., 32768) are
|
||||
; not extracted
|
||||
define amdgpu_kernel void @test7(i1 %0, ptr addrspace(3) %1) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @test7(
|
||||
; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; CHECK-NEXT: [[ENTRY:.*:]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]
|
||||
; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
; GVN-LABEL: define amdgpu_kernel void @test7(
|
||||
; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {
|
||||
; GVN-NEXT: [[ENTRY:.*:]]
|
||||
; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288
|
||||
; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32
|
||||
; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800
|
||||
; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]
|
||||
; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]
|
||||
; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16
|
||||
; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16
|
||||
; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]
|
||||
; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16
|
||||
; GVN-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%2 = select i1 %0, i32 0, i32 288
|
||||
%3 = xor i32 %2, 32
|
||||
%4 = xor i32 %2, 32800
|
||||
%5 = getelementptr half, ptr addrspace(3) %1, i32 %3
|
||||
%6 = getelementptr half, ptr addrspace(3) %1, i32 %4
|
||||
%7 = load <8 x half>, ptr addrspace(3) %5, align 16
|
||||
%8 = load <8 x half>, ptr addrspace(3) %6, align 16
|
||||
%9 = fadd <8 x half> %7, %8
|
||||
store <8 x half> %9, ptr addrspace(3) %1, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -32,9 +32,8 @@ define ptr @test_overflow(ptr %p, i32 %a) {
|
||||
define ptr @test_xor_overflow(ptr %p, i32 range(i32 0, -2147483648) %a) {
|
||||
; CHECK-LABEL: define ptr @test_xor_overflow(
|
||||
; CHECK-SAME: ptr [[P:%.*]], i32 range(i32 0, -2147483648) [[A:%.*]]) {
|
||||
; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], 2147483647
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[XOR1]], 2
|
||||
; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[P]], i32 [[TMP1]]
|
||||
; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], -1
|
||||
; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr inbounds i32, ptr [[P]], i32 [[XOR]]
|
||||
; CHECK-NEXT: ret ptr [[UGLYGEP]]
|
||||
;
|
||||
%xor = xor i32 %a, -1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user