shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)

Browse Source 
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.
This commit is contained in:
Christudasan Devadasan 2025-11-21 19:42:17 +05:30 committed by GitHub
parent 49995b2af0
commit a2dc4e02e7
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
149 changed files with 7119 additions and 715 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
View File

@ -772,6 +772,17 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
PreloadedScratchRsrcReg,
ScratchRsrcReg, ScratchWaveOffsetReg);
}
if (ST.hasWaitXCnt()) {
// Set REPLAY_MODE (bit 25) in MODE register to enable multi-group XNACK
// replay. This aligns hardware behavior with the compiler's s_wait_xcnt
// insertion logic, which assumes multi-group mode by default.
unsigned RegEncoding =
AMDGPU::Hwreg::HwregEncoding::encode(AMDGPU::Hwreg::ID_MODE, 25, 1);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
.addImm(1)
.addImm(RegEncoding);
}
}
// Emit scratch RSRC setup code, assuming `ScratchRsrcReg != AMDGPU::NoReg`

48
llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
View File

@ -41,6 +41,7 @@ define amdgpu_kernel void @raw_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -71,6 +72,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -114,6 +116,7 @@ define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsr
;
; GFX1250-LABEL: raw_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -160,6 +163,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8)
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -190,6 +194,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -233,6 +238,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrsp
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -279,6 +285,7 @@ define amdgpu_kernel void @struct_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -309,6 +316,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -352,6 +360,7 @@ define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %
;
; GFX1250-LABEL: struct_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -397,6 +406,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_add_noret_f64(ptr addrspace(
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -427,6 +437,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -470,6 +481,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr add
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -515,6 +527,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -545,6 +558,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -588,6 +602,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %rsr
;
; GFX1250-LABEL: raw_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -634,6 +649,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8)
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -664,6 +680,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -707,6 +724,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrsp
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -753,6 +771,7 @@ define amdgpu_kernel void @struct_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -783,6 +802,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -826,6 +846,7 @@ define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %
;
; GFX1250-LABEL: struct_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -871,6 +892,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_min_noret_f64(ptr addrspace(
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -901,6 +923,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -944,6 +967,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr add
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -989,6 +1013,7 @@ define amdgpu_kernel void @raw_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1019,6 +1044,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1062,6 +1088,7 @@ define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %rsr
;
; GFX1250-LABEL: raw_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1108,6 +1135,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8)
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1138,6 +1166,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1181,6 +1210,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrsp
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1227,6 +1257,7 @@ define amdgpu_kernel void @struct_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1257,6 +1288,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1300,6 +1332,7 @@ define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %
;
; GFX1250-LABEL: struct_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1345,6 +1378,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_max_noret_f64(ptr addrspace(
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1375,6 +1409,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1418,6 +1453,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr add
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1486,6 +1522,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat(ptr addrspace(1) %pt
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -1558,6 +1595,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent(ptr addrspace(
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_agent:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -1632,6 +1670,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_system(ptr addrspace
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_system:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -1704,6 +1743,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_flush(ptr addrspace(
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_flush:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -1894,6 +1934,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent_safe(ptr addrs
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_agent_safe:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -1949,6 +1990,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(ptr %ptr) #1 {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1991,6 +2033,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent(ptr %ptr) #1 {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat_agent:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -2035,6 +2078,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(ptr %ptr) #1 {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat_system:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -2197,6 +2241,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent_safe(ptr %ptr) {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat_agent_safe:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -2255,6 +2300,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat(ptr addrspace(3) %ptr
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret_pat:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -2320,6 +2366,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat_flush(ptr addrspace(3
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret_pat_flush:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0
@ -2385,6 +2432,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat_flush_safe(ptr addrsp
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret_pat_flush_safe:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s0, exec_lo
; GFX1250-NEXT: s_mov_b32 s1, exec_lo
; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, s0, 0

157
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
View File

@ -34,6 +34,7 @@ define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
;
; GFX1250-LABEL: abs_sgpr_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_sext_i32_i16 s0, s0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_abs_i32 s0, s0
@ -43,10 +44,26 @@ define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
}
define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
; GFX-LABEL: abs_sgpr_i32:
; GFX: ; %bb.0:
; GFX-NEXT: s_abs_i32 s0, s0
; GFX-NEXT: ; return to shader part epilog
; GFX6-LABEL: abs_sgpr_i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_abs_i32 s0, s0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: abs_sgpr_i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_abs_i32 s0, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: abs_sgpr_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_abs_i32 s0, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: abs_sgpr_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_abs_i32 s0, s0
; GFX1250-NEXT: ; return to shader part epilog
%res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
ret i32 %res
}
@ -81,6 +98,7 @@ define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
;
; GFX1250-LABEL: abs_sgpr_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_ashr_i32 s2, s1, 31
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT: s_mov_b32 s3, s2
@ -93,13 +111,38 @@ define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
}
define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {
; GFX-LABEL: abs_sgpr_v4i32:
; GFX: ; %bb.0:
; GFX-NEXT: s_abs_i32 s0, s0
; GFX-NEXT: s_abs_i32 s1, s1
; GFX-NEXT: s_abs_i32 s2, s2
; GFX-NEXT: s_abs_i32 s3, s3
; GFX-NEXT: ; return to shader part epilog
; GFX6-LABEL: abs_sgpr_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_abs_i32 s0, s0
; GFX6-NEXT: s_abs_i32 s1, s1
; GFX6-NEXT: s_abs_i32 s2, s2
; GFX6-NEXT: s_abs_i32 s3, s3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: abs_sgpr_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_abs_i32 s0, s0
; GFX8-NEXT: s_abs_i32 s1, s1
; GFX8-NEXT: s_abs_i32 s2, s2
; GFX8-NEXT: s_abs_i32 s3, s3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: abs_sgpr_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_abs_i32 s0, s0
; GFX10-NEXT: s_abs_i32 s1, s1
; GFX10-NEXT: s_abs_i32 s2, s2
; GFX10-NEXT: s_abs_i32 s3, s3
; GFX10-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: abs_sgpr_v4i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_abs_i32 s0, s0
; GFX1250-NEXT: s_abs_i32 s1, s1
; GFX1250-NEXT: s_abs_i32 s2, s2
; GFX1250-NEXT: s_abs_i32 s3, s3
; GFX1250-NEXT: ; return to shader part epilog
%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
ret <4 x i32> %res
}
@ -278,13 +321,38 @@ define <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
}
define amdgpu_cs <2 x i8> @abs_sgpr_v2i8(<2 x i8> inreg %arg) {
; GFX-LABEL: abs_sgpr_v2i8:
; GFX: ; %bb.0:
; GFX-NEXT: s_sext_i32_i8 s0, s0
; GFX-NEXT: s_sext_i32_i8 s1, s1
; GFX-NEXT: s_abs_i32 s0, s0
; GFX-NEXT: s_abs_i32 s1, s1
; GFX-NEXT: ; return to shader part epilog
; GFX6-LABEL: abs_sgpr_v2i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_abs_i32 s0, s0
; GFX6-NEXT: s_abs_i32 s1, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: abs_sgpr_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i8 s0, s0
; GFX8-NEXT: s_sext_i32_i8 s1, s1
; GFX8-NEXT: s_abs_i32 s0, s0
; GFX8-NEXT: s_abs_i32 s1, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: abs_sgpr_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_sext_i32_i8 s0, s0
; GFX10-NEXT: s_sext_i32_i8 s1, s1
; GFX10-NEXT: s_abs_i32 s0, s0
; GFX10-NEXT: s_abs_i32 s1, s1
; GFX10-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: abs_sgpr_v2i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_sext_i32_i8 s0, s0
; GFX1250-NEXT: s_sext_i32_i8 s1, s1
; GFX1250-NEXT: s_abs_i32 s0, s0
; GFX1250-NEXT: s_abs_i32 s1, s1
; GFX1250-NEXT: ; return to shader part epilog
%res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
ret <2 x i8> %res
}
@ -340,15 +408,46 @@ define <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
}
define amdgpu_cs <3 x i8> @abs_sgpr_v3i8(<3 x i8> inreg %arg) {
; GFX-LABEL: abs_sgpr_v3i8:
; GFX: ; %bb.0:
; GFX-NEXT: s_sext_i32_i8 s0, s0
; GFX-NEXT: s_sext_i32_i8 s1, s1
; GFX-NEXT: s_sext_i32_i8 s2, s2
; GFX-NEXT: s_abs_i32 s0, s0
; GFX-NEXT: s_abs_i32 s1, s1
; GFX-NEXT: s_abs_i32 s2, s2
; GFX-NEXT: ; return to shader part epilog
; GFX6-LABEL: abs_sgpr_v3i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_sext_i32_i8 s2, s2
; GFX6-NEXT: s_abs_i32 s0, s0
; GFX6-NEXT: s_abs_i32 s1, s1
; GFX6-NEXT: s_abs_i32 s2, s2
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: abs_sgpr_v3i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i8 s0, s0
; GFX8-NEXT: s_sext_i32_i8 s1, s1
; GFX8-NEXT: s_sext_i32_i8 s2, s2
; GFX8-NEXT: s_abs_i32 s0, s0
; GFX8-NEXT: s_abs_i32 s1, s1
; GFX8-NEXT: s_abs_i32 s2, s2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: abs_sgpr_v3i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_sext_i32_i8 s0, s0
; GFX10-NEXT: s_sext_i32_i8 s1, s1
; GFX10-NEXT: s_sext_i32_i8 s2, s2
; GFX10-NEXT: s_abs_i32 s0, s0
; GFX10-NEXT: s_abs_i32 s1, s1
; GFX10-NEXT: s_abs_i32 s2, s2
; GFX10-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: abs_sgpr_v3i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_sext_i32_i8 s0, s0
; GFX1250-NEXT: s_sext_i32_i8 s1, s1
; GFX1250-NEXT: s_sext_i32_i8 s2, s2
; GFX1250-NEXT: s_abs_i32 s0, s0
; GFX1250-NEXT: s_abs_i32 s1, s1
; GFX1250-NEXT: s_abs_i32 s2, s2
; GFX1250-NEXT: ; return to shader part epilog
%res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
ret <3 x i8> %res
}
@ -446,6 +545,7 @@ define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
;
; GFX1250-LABEL: abs_sgpr_v2i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_sext_i32_i16 s1, s0
; GFX1250-NEXT: s_ashr_i32 s0, s0, 16
; GFX1250-NEXT: s_abs_i32 s1, s1
@ -536,6 +636,7 @@ define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
;
; GFX1250-LABEL: abs_sgpr_v3i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_sext_i32_i16 s2, s0
; GFX1250-NEXT: s_ashr_i32 s0, s0, 16
; GFX1250-NEXT: s_abs_i32 s2, s2
@ -598,3 +699,5 @@ define <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {
%res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
ret <3 x i16> %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX: {{.*}}

34
llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
View File

@ -930,6 +930,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align1(ptr addrspace(4) inreg
;
; GFX1250-UNALIGNED-LABEL: s_load_constant_v3i32_align1:
; GFX1250-UNALIGNED: ; %bb.0:
; GFX1250-UNALIGNED-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-UNALIGNED-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-UNALIGNED-NEXT: global_load_b96 v[0:2], v0, s[0:1]
; GFX1250-UNALIGNED-NEXT: s_wait_loadcnt 0x0
@ -940,6 +941,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align1(ptr addrspace(4) inreg
;
; GFX1250-NOUNALIGNED-LABEL: s_load_constant_v3i32_align1:
; GFX1250-NOUNALIGNED: ; %bb.0:
; GFX1250-NOUNALIGNED-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NOUNALIGNED-NEXT: s_clause 0xb
; GFX1250-NOUNALIGNED-NEXT: s_load_u8 s2, s[0:1], 0x1
; GFX1250-NOUNALIGNED-NEXT: s_load_u8 s3, s[0:1], 0x3
@ -1208,6 +1210,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align2(ptr addrspace(4) inreg
;
; GFX1250-UNALIGNED-LABEL: s_load_constant_v3i32_align2:
; GFX1250-UNALIGNED: ; %bb.0:
; GFX1250-UNALIGNED-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-UNALIGNED-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-UNALIGNED-NEXT: global_load_b96 v[0:2], v0, s[0:1]
; GFX1250-UNALIGNED-NEXT: s_wait_loadcnt 0x0
@ -1218,6 +1221,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align2(ptr addrspace(4) inreg
;
; GFX1250-NOUNALIGNED-LABEL: s_load_constant_v3i32_align2:
; GFX1250-NOUNALIGNED: ; %bb.0:
; GFX1250-NOUNALIGNED-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NOUNALIGNED-NEXT: s_clause 0x5
; GFX1250-NOUNALIGNED-NEXT: s_load_u16 s2, s[0:1], 0x2
; GFX1250-NOUNALIGNED-NEXT: s_load_u16 s3, s[0:1], 0x6
@ -1362,6 +1366,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg
;
; GFX1250-LABEL: s_load_constant_v3i32_align4:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s4, s0
; GFX1250-NEXT: s_mov_b32 s5, s1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
@ -1413,6 +1418,7 @@ define amdgpu_ps i96 @s_load_constant_i96_align8(ptr addrspace(4) inreg %ptr) {
;
; GFX1250-LABEL: s_load_constant_i96_align8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s4, s0
; GFX1250-NEXT: s_mov_b32 s5, s1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
@ -1464,6 +1470,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align8(ptr addrspace(4) inreg
;
; GFX1250-LABEL: s_load_constant_v3i32_align8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s4, s0
; GFX1250-NEXT: s_mov_b32 s5, s1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
@ -1515,6 +1522,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v6i16_align8(ptr addrspace(4) inreg
;
; GFX1250-LABEL: s_load_constant_v6i16_align8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s4, s0
; GFX1250-NEXT: s_mov_b32 s5, s1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
@ -1593,6 +1601,7 @@ define amdgpu_ps <12 x i8> @s_load_constant_v12i8_align8(ptr addrspace(4) inreg
;
; GFX1250-LABEL: s_load_constant_v12i8_align8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s4, s0
; GFX1250-NEXT: s_mov_b32 s5, s1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
@ -1670,11 +1679,24 @@ define amdgpu_ps <12 x i8> @s_load_constant_v12i8_align8(ptr addrspace(4) inreg
}
define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align16(ptr addrspace(4) inreg %ptr) {
; GFX12-LABEL: s_load_constant_v3i32_align16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: ; return to shader part epilog
; GFX12-UNALIGNED-LABEL: s_load_constant_v3i32_align16:
; GFX12-UNALIGNED: ; %bb.0:
; GFX12-UNALIGNED-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
; GFX12-UNALIGNED-NEXT: s_wait_kmcnt 0x0
; GFX12-UNALIGNED-NEXT: ; return to shader part epilog
;
; GFX12-NOUNALIGNED-LABEL: s_load_constant_v3i32_align16:
; GFX12-NOUNALIGNED: ; %bb.0:
; GFX12-NOUNALIGNED-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
; GFX12-NOUNALIGNED-NEXT: s_wait_kmcnt 0x0
; GFX12-NOUNALIGNED-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: s_load_constant_v3i32_align16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: ; return to shader part epilog
;
; GCN-LABEL: s_load_constant_v3i32_align16:
; GCN: ; %bb.0:
@ -1684,3 +1706,5 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align16(ptr addrspace(4) inreg
%load = load <3 x i32>, ptr addrspace(4) %ptr, align 16
ret <3 x i32> %load
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX12: {{.*}}

5
llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
View File

@ -132,6 +132,7 @@ define i64 @test_abs_i64(i64 %a) {
define amdgpu_ps i64 @test_umin_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_umin_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-NEXT: v_min_u64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
@ -144,6 +145,7 @@ define amdgpu_ps i64 @test_umin_i64_s(i64 inreg %a, i64 inreg %b) {
define amdgpu_ps i64 @test_umax_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_umax_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-NEXT: v_max_u64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
@ -156,6 +158,7 @@ define amdgpu_ps i64 @test_umax_i64_s(i64 inreg %a, i64 inreg %b) {
define amdgpu_ps i64 @test_smin_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_smin_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-NEXT: v_min_i64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
@ -168,6 +171,7 @@ define amdgpu_ps i64 @test_smin_i64_s(i64 inreg %a, i64 inreg %b) {
define amdgpu_ps i64 @test_smax_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_smax_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-NEXT: v_max_i64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
@ -180,6 +184,7 @@ define amdgpu_ps i64 @test_smax_i64_s(i64 inreg %a, i64 inreg %b) {
define amdgpu_ps i64 @test_abs_i64_s(i64 inreg %a) {
; CHECK-LABEL: test_abs_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-NEXT: s_ashr_i32 s2, s1, 31
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT: s_mov_b32 s3, s2

14
llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
View File

@ -26,6 +26,7 @@ define amdgpu_ps i16 @s_mul_i16(i16 inreg %num, i16 inreg %den) {
;
; GFX1250-LABEL: s_mul_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s0, s0, s1
; GFX1250-NEXT: ; return to shader part epilog
%result = mul i16 %num, %den
@ -125,6 +126,7 @@ define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inre
;
; GFX1250-LABEL: s_mul_i16_zeroext:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s0, s0, s1
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_b32 s0, 0xffff, s0
@ -220,6 +222,7 @@ define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inre
;
; GFX1250-LABEL: s_mul_i16_signext:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s0, s0, s1
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_sext_i32_i16 s0, s0
@ -315,6 +318,7 @@ define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) {
;
; GFX1250-LABEL: s_mul_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s0, s0, s1
; GFX1250-NEXT: ; return to shader part epilog
%result = mul i32 %num, %den
@ -375,6 +379,7 @@ define amdgpu_ps <2 x i32> @s_mul_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %d
;
; GFX1250-LABEL: s_mul_v2i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s0, s0, s2
; GFX1250-NEXT: s_mul_i32 s1, s1, s3
; GFX1250-NEXT: ; return to shader part epilog
@ -474,6 +479,7 @@ define amdgpu_cs i33 @s_mul_i33(i33 inreg %num, i33 inreg %den) {
;
; GFX1250-LABEL: s_mul_i33:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]
; GFX1250-NEXT: ; return to shader part epilog
%result = mul i33 %num, %den
@ -535,6 +541,7 @@ define amdgpu_ps i64 @s_mul_i64(i64 inreg %num, i64 inreg %den) {
;
; GFX1250-LABEL: s_mul_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_u64 s[0:1], s[0:1], s[2:3]
; GFX1250-NEXT: ; return to shader part epilog
%result = mul i64 %num, %den
@ -712,6 +719,7 @@ define amdgpu_ps <3 x i32> @s_mul_i96(i96 inreg %num, i96 inreg %den) {
;
; GFX1250-LABEL: s_mul_i96:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s6, s0, s5
; GFX1250-NEXT: s_mul_i32 s7, s1, s4
; GFX1250-NEXT: s_mul_i32 s2, s2, s3
@ -1027,6 +1035,7 @@ define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) {
;
; GFX1250-LABEL: s_mul_i128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s9, s0, s6
; GFX1250-NEXT: s_mul_i32 s11, s1, s5
; GFX1250-NEXT: s_mul_hi_u32 s10, s0, s6
@ -2218,6 +2227,7 @@ define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) {
;
; GFX1250-LABEL: s_mul_i256:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s17, s0, s10
; GFX1250-NEXT: s_mul_i32 s19, s1, s9
; GFX1250-NEXT: s_mul_hi_u32 s18, s0, s10
@ -2997,6 +3007,7 @@ define amdgpu_ps void @s_mul_u64_zext_with_vregs(ptr addrspace(1) %out, ptr addr
;
; GFX1250-LABEL: s_mul_u64_zext_with_vregs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v4, v[2:3], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_mad_nc_u64_u32 v[2:3], 0x50, v4, 0
@ -3101,6 +3112,7 @@ define amdgpu_kernel void @s_mul_u64_zext_with_sregs(ptr addrspace(1) %out, ptr
;
; GFX1250-LABEL: s_mul_u64_zext_with_sregs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -3191,6 +3203,7 @@ define amdgpu_ps void @s_mul_u64_sext_with_vregs(ptr addrspace(1) %out, ptr addr
;
; GFX1250-LABEL: s_mul_u64_sext_with_vregs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v4, v[2:3], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_mad_nc_i64_i32 v[2:3], 0x50, v4, 0
@ -3310,6 +3323,7 @@ define amdgpu_kernel void @s_mul_u64_sext_with_sregs(ptr addrspace(1) %out, ptr
;
; GFX1250-LABEL: s_mul_u64_sext_with_sregs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0

22
llvm/test/CodeGen/AMDGPU/add-max.ll
View File

@ -5,6 +5,7 @@
define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: add_max_u32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_u32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -16,6 +17,7 @@ define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) {
define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) {
; GCN-LABEL: add_max_u32_svv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_u32 v0, s0, v0, v1
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -27,6 +29,7 @@ define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) {
define amdgpu_ps float @add_max_u32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
; GCN-LABEL: add_max_u32_ssv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_u32 v0, s0, s1, v0
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -38,6 +41,7 @@ define amdgpu_ps float @add_max_u32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
; SDAG-LABEL: add_max_u32_sss:
; SDAG: ; %bb.0:
; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-NEXT: v_max_u32_e32 v0, s2, v0
@ -45,6 +49,7 @@ define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c
;
; GISEL-LABEL: add_max_u32_sss:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: v_mov_b32_e32 v0, s2
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_add_max_u32 v0, s0, s1, v0
@ -58,6 +63,7 @@ define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c
define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) {
; GCN-LABEL: add_max_u32_vsi:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_u32 v0, v0, s0, 4
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -69,6 +75,7 @@ define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) {
define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) {
; GCN-LABEL: add_max_u32_svl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_u32 v0, s0, v0, 0x64
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -80,6 +87,7 @@ define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) {
define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b, i32 %c) {
; GCN-LABEL: add_max_u32_slv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_u32 v0, s0, v0, v1
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -91,6 +99,7 @@ define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b, i32 %c) {
define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: add_max_i32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_max_i32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.sadd.sat.i32(i32 %a, i32 %b)
@ -102,6 +111,7 @@ define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) {
define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: add_min_u32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_min_u32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)
@ -113,6 +123,7 @@ define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) {
define amdgpu_ps float @add_min_i32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: add_min_i32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_min_i32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call i32 @llvm.sadd.sat.i32(i32 %a, i32 %b)
@ -124,6 +135,7 @@ define amdgpu_ps float @add_min_i32_vvv(i32 %a, i32 %b, i32 %c) {
define amdgpu_ps float @add_max_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: add_max_v2u16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_u16 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -135,6 +147,7 @@ define amdgpu_ps float @add_max_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16>
define amdgpu_ps float @add_max_v2u16_svv(<2 x i16> inreg %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: add_max_v2u16_svv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, v1
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -146,6 +159,7 @@ define amdgpu_ps float @add_max_v2u16_svv(<2 x i16> inreg %a, <2 x i16> %b, <2 x
define amdgpu_ps float @add_max_v2u16_ssv(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> %c) {
; GCN-LABEL: add_max_v2u16_ssv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_u16 v0, s0, s1, v0
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -157,6 +171,7 @@ define amdgpu_ps float @add_max_v2u16_ssv(<2 x i16> inreg %a, <2 x i16> inreg %b
define amdgpu_ps float @add_max_v2u16_sss(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> inreg %c) {
; SDAG-LABEL: add_max_v2u16_sss:
; SDAG: ; %bb.0:
; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-NEXT: v_pk_add_u16 v0, s0, s1 clamp
; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-NEXT: v_pk_max_u16 v0, v0, s2
@ -164,6 +179,7 @@ define amdgpu_ps float @add_max_v2u16_sss(<2 x i16> inreg %a, <2 x i16> inreg %b
;
; GISEL-LABEL: add_max_v2u16_sss:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: v_mov_b32_e32 v0, s2
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_pk_add_max_u16 v0, s0, s1, v0
@ -177,6 +193,7 @@ define amdgpu_ps float @add_max_v2u16_sss(<2 x i16> inreg %a, <2 x i16> inreg %b
define amdgpu_ps float @add_max_v2u16_vsi(<2 x i16> %a, <2 x i16> inreg %b) {
; GCN-LABEL: add_max_v2u16_vsi:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_u16 v0, v0, s0, 4
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -188,6 +205,7 @@ define amdgpu_ps float @add_max_v2u16_vsi(<2 x i16> %a, <2 x i16> inreg %b) {
define amdgpu_ps float @add_max_v2u16_svl(<2 x i16> inreg %a, <2 x i16> %b) {
; GCN-LABEL: add_max_v2u16_svl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, 0x650064
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -199,6 +217,7 @@ define amdgpu_ps float @add_max_v2u16_svl(<2 x i16> inreg %a, <2 x i16> %b) {
define amdgpu_ps float @add_max_v2u16_slv(<2 x i16> inreg %a, <2 x i16> %b) {
; GCN-LABEL: add_max_v2u16_slv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_u16 v0, 0x640064, s0, v0
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> <i16 100, i16 100>)
@ -210,6 +229,7 @@ define amdgpu_ps float @add_max_v2u16_slv(<2 x i16> inreg %a, <2 x i16> %b) {
define amdgpu_ps float @add_max_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: add_max_v2s16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_max_i16 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.sadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -221,6 +241,7 @@ define amdgpu_ps float @add_max_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16>
define amdgpu_ps float @add_min_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: add_min_v2u16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_min_u16 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)
@ -232,6 +253,7 @@ define amdgpu_ps float @add_min_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16>
define amdgpu_ps float @add_min_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: add_min_v2s16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_min_i16 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%add = call <2 x i16> @llvm.sadd.sat.i32(<2 x i16> %a, <2 x i16> %b)

48
llvm/test/CodeGen/AMDGPU/add_u64.ll
View File

@ -12,6 +12,7 @@ define amdgpu_ps <2 x float> @test_add_u64_vv(i64 %a, i64 %b) {
;
; GFX1250-LABEL: test_add_u64_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
@ -29,6 +30,7 @@ define amdgpu_ps <2 x float> @test_add_u64_vs(i64 %a, i64 inreg %b) {
;
; GFX1250-LABEL: test_add_u64_vs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
@ -46,6 +48,7 @@ define amdgpu_ps <2 x float> @test_add_u64_sv(i64 inreg %a, i64 %b) {
;
; GFX1250-LABEL: test_add_u64_sv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
@ -54,12 +57,20 @@ define amdgpu_ps <2 x float> @test_add_u64_sv(i64 inreg %a, i64 %b) {
}
define amdgpu_ps <2 x float> @test_add_u64_ss(i64 inreg %a, i64 inreg %b) {
; GCN-LABEL: test_add_u64_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GCN-NEXT: ; return to shader part epilog
; GFX12-LABEL: test_add_u64_ss:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_ss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, %b
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
@ -75,6 +86,7 @@ define amdgpu_ps <2 x float> @test_add_u64_v_inline_lit(i64 %a) {
;
; GFX1250-LABEL: test_add_u64_v_inline_lit:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 5, v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 5
@ -92,6 +104,7 @@ define amdgpu_ps <2 x float> @test_add_u64_v_small_imm(i64 %a) {
;
; GFX1250-LABEL: test_add_u64_v_small_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 0x1f4, v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 500
@ -109,6 +122,7 @@ define amdgpu_ps <2 x float> @test_add_u64_v_64bit_imm(i64 %a) {
;
; GFX1250-LABEL: test_add_u64_v_64bit_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 0x13b9ac9ff, v[0:1]
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 5294967295
@ -117,13 +131,23 @@ define amdgpu_ps <2 x float> @test_add_u64_v_64bit_imm(i64 %a) {
}
define amdgpu_ps <2 x float> @test_add_u64_s_small_imm(i64 inreg %a) {
; GCN-LABEL: test_add_u64_s_small_imm:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x1f4
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GCN-NEXT: ; return to shader part epilog
; GFX12-LABEL: test_add_u64_s_small_imm:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x1f4
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_add_u64_s_small_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x1f4
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX1250-NEXT: ; return to shader part epilog
%add = add i64 %a, 500
%ret = bitcast i64 %add to <2 x float>
ret <2 x float> %ret
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}

7
llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
View File

@ -9,6 +9,7 @@ target triple = "amdgcn-amd-amdhsa"
define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) {
; GFX1250-SDAG-LABEL: use_private_to_flat_addrspacecast:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -26,6 +27,7 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %p
;
; GFX1250-GISEL-LABEL: use_private_to_flat_addrspacecast:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], src_flat_scratch_base_lo
; GFX1250-GISEL-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 0
@ -53,6 +55,7 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %p
define amdgpu_kernel void @use_private_to_flat_addrspacecast_nonnull(ptr addrspace(5) %ptr) {
; GFX1250-SDAG-LABEL: use_private_to_flat_addrspacecast_nonnull:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
@ -66,6 +69,7 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast_nonnull(ptr addrspa
;
; GFX1250-GISEL-LABEL: use_private_to_flat_addrspacecast_nonnull:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 0
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], src_flat_scratch_base_lo
@ -87,6 +91,7 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast_nonnull(ptr addrspa
define amdgpu_kernel void @use_flat_to_private_addrspacecast(ptr %ptr) {
; GFX1250-LABEL: use_flat_to_private_addrspacecast:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -104,6 +109,7 @@ define amdgpu_kernel void @use_flat_to_private_addrspacecast(ptr %ptr) {
define amdgpu_kernel void @use_flat_to_private_addrspacecast_nonnull(ptr %ptr) {
; GFX1250-SDAG-LABEL: use_flat_to_private_addrspacecast_nonnull:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -114,6 +120,7 @@ define amdgpu_kernel void @use_flat_to_private_addrspacecast_nonnull(ptr %ptr) {
;
; GFX1250-GISEL-LABEL: use_flat_to_private_addrspacecast_nonnull:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0

14
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
View File

@ -13,6 +13,7 @@ define amdgpu_ps float @v_test_cvt_bf16_f32_v(bfloat %v) {
;
; GFX1250-LABEL: v_test_cvt_bf16_f32_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250-NEXT: ; return to shader part epilog
%cvt = fpext bfloat %v to float
@ -28,6 +29,7 @@ define amdgpu_ps float @v_test_cvt_bf16_f32_s(bfloat inreg %v) {
;
; GFX1250-LABEL: v_test_cvt_bf16_f32_s:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
@ -63,6 +65,7 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_v(<2 x float> %src) {
;
; GFX1250-LABEL: v_test_cvt_v2f32_v2bf16_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
; GFX1250-NEXT: ; return to shader part epilog
%res = fptrunc <2 x float> %src to <2 x bfloat>
@ -101,6 +104,7 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
;
; GFX1250-LABEL: v_test_cvt_v2f32_v2bf16_s:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, s0, s1
; GFX1250-NEXT: ; return to shader part epilog
%res = fptrunc <2 x float> %src to <2 x bfloat>
@ -129,6 +133,7 @@ define amdgpu_ps float @v_test_cvt_f32_bf16_v(float %src) {
;
; GFX1250-LABEL: v_test_cvt_f32_bf16_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
@ -205,6 +210,7 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
;
; GFX1250-LABEL: v_test_cvt_v2f64_v2bf16_v:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_f64_e32 v8, v[2:3]
; GFX1250-NEXT: v_cvt_f32_f64_e32 v9, v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@ -264,6 +270,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
;
; GFX1250-LABEL: fptrunc_f32_f32_to_v2bf16:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
; GFX1250-NEXT: ; return to shader part epilog
entry:
@ -304,6 +311,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16_mods(float %a, float %b) {
;
; GFX1250-LABEL: fptrunc_f32_f32_to_v2bf16_mods:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, -v0, |v1|
; GFX1250-NEXT: ; return to shader part epilog
entry:
@ -342,6 +350,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16(float %a, ptr %out) {
;
; GFX1250-LABEL: fptrunc_f32_to_bf16:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
@ -378,6 +387,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16_abs(float %a, ptr %out) {
;
; GFX1250-LABEL: fptrunc_f32_to_bf16_abs:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, |v0|, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
@ -415,6 +425,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16_neg(float %a, ptr %out) {
;
; GFX1250-LABEL: fptrunc_f32_to_bf16_neg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, -v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
@ -467,6 +478,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
;
; GFX1250-LABEL: fptrunc_f64_to_bf16:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
@ -529,6 +541,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
;
; GFX1250-LABEL: fptrunc_f64_to_bf16_neg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
@ -593,6 +606,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
;
; GFX1250-LABEL: fptrunc_f64_to_bf16_abs:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_f64_f32_e32 v[4:5], v6

49
llvm/test/CodeGen/AMDGPU/bf16-math.ll
View File

@ -5,6 +5,7 @@
define amdgpu_ps void @llvm_sqrt_bf16_v(ptr addrspace(1) %out, bfloat %src) {
; GCN-LABEL: llvm_sqrt_bf16_v:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_sqrt_bf16_e32 v2, v2
; GCN-NEXT: global_store_b16 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -16,6 +17,7 @@ define amdgpu_ps void @llvm_sqrt_bf16_v(ptr addrspace(1) %out, bfloat %src) {
define amdgpu_ps void @llvm_sqrt_bf16_s(ptr addrspace(1) %out, bfloat inreg %src) {
; GCN-LABEL: llvm_sqrt_bf16_s:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_sqrt_bf16_e32 v2, s0
; GCN-NEXT: global_store_b16 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -27,6 +29,7 @@ define amdgpu_ps void @llvm_sqrt_bf16_s(ptr addrspace(1) %out, bfloat inreg %src
define amdgpu_ps void @v_test_add_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b) {
; GCN-LABEL: v_test_add_v2bf16_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, v3
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -38,6 +41,7 @@ define amdgpu_ps void @v_test_add_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_add_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_add_v2bf16_vs:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, s0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -49,6 +53,7 @@ define amdgpu_ps void @v_test_add_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_add_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_add_v2bf16_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -60,6 +65,7 @@ define amdgpu_ps void @v_test_add_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_add_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_add_v2bf16_vc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, 2.0 op_sel_hi:[1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -71,6 +77,7 @@ define amdgpu_ps void @v_test_add_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_add_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_add_v2bf16_vl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, 0x42c83f80, v2
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -82,6 +89,7 @@ define amdgpu_ps void @v_test_add_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b) {
; GCN-LABEL: v_test_sub_v2bf16_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, v3 neg_lo:[0,1] neg_hi:[0,1]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -93,6 +101,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_sub_v2bf16_vs:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, s0 neg_lo:[0,1] neg_hi:[0,1]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -104,6 +113,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_sub_v2bf16_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, s0, s1 neg_lo:[0,1] neg_hi:[0,1]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -115,6 +125,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_sub_v2bf16_vc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, -2.0 op_sel_hi:[1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -126,6 +137,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_sub_v2bf16_vl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, 0xc2c8bf80, v2
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -137,6 +149,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_lv(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_sub_v2bf16_lv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, 0x42c83f80, v2 neg_lo:[0,1] neg_hi:[0,1]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -148,6 +161,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_lv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_sub_v2bf16_iv(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_sub_v2bf16_iv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_add_bf16 v2, v2, 1.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -159,6 +173,7 @@ define amdgpu_ps void @v_test_sub_v2bf16_iv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_mul_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b) {
; GCN-LABEL: v_test_mul_v2bf16_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_mul_bf16 v2, v2, v3
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -170,6 +185,7 @@ define amdgpu_ps void @v_test_mul_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_mul_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_mul_v2bf16_vs:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_mul_bf16 v2, v2, s0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -181,6 +197,7 @@ define amdgpu_ps void @v_test_mul_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_mul_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_mul_v2bf16_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_mul_bf16 v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -194,6 +211,7 @@ define amdgpu_ps void @v_test_mul_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_mul_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_mul_v2bf16_vc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_mul_bf16 v2, v2, 0.5 op_sel_hi:[1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -205,6 +223,7 @@ define amdgpu_ps void @v_test_mul_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_mul_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_mul_v2bf16_vl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_mul_bf16 v2, 0x42c83f80, v2
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -216,6 +235,7 @@ define amdgpu_ps void @v_test_mul_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_min_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b) {
; GCN-LABEL: v_test_min_v2bf16_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_min_num_bf16 v2, v2, v3
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -227,6 +247,7 @@ define amdgpu_ps void @v_test_min_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_min_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_min_v2bf16_vs:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_min_num_bf16 v2, v2, s0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -238,6 +259,7 @@ define amdgpu_ps void @v_test_min_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_min_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_min_v2bf16_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_min_num_bf16 v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -249,6 +271,7 @@ define amdgpu_ps void @v_test_min_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_min_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_min_v2bf16_vc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_min_num_bf16 v2, v2, 0.5 op_sel_hi:[1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -260,6 +283,7 @@ define amdgpu_ps void @v_test_min_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_min_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_min_v2bf16_vl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_min_num_bf16 v2, 0x42c83f80, v2
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -271,6 +295,7 @@ define amdgpu_ps void @v_test_min_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_max_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b) {
; GCN-LABEL: v_test_max_v2bf16_vv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v2, v2, v3
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -282,6 +307,7 @@ define amdgpu_ps void @v_test_max_v2bf16_vv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_max_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_max_v2bf16_vs:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v2, v2, s0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -293,6 +319,7 @@ define amdgpu_ps void @v_test_max_v2bf16_vs(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_max_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_max_v2bf16_ss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -304,6 +331,7 @@ define amdgpu_ps void @v_test_max_v2bf16_ss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_max_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_max_v2bf16_vc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v2, v2, 0.5 op_sel_hi:[1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -315,6 +343,7 @@ define amdgpu_ps void @v_test_max_v2bf16_vc(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_max_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_max_v2bf16_vl:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v2, 0x42c83f80, v2
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -326,6 +355,7 @@ define amdgpu_ps void @v_test_max_v2bf16_vl(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps bfloat @test_clamp_bf16(bfloat %src) {
; GCN-LABEL: test_clamp_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v0, v0, v0 clamp
; GCN-NEXT: ; return to shader part epilog
%max = call bfloat @llvm.maxnum.bf16(bfloat %src, bfloat 0.0)
@ -336,6 +366,7 @@ define amdgpu_ps bfloat @test_clamp_bf16(bfloat %src) {
define amdgpu_ps bfloat @test_clamp_bf16_s(bfloat inreg %src) {
; GCN-LABEL: test_clamp_bf16_s:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v0, s0, s0 clamp
; GCN-NEXT: ; return to shader part epilog
%max = call bfloat @llvm.maxnum.bf16(bfloat %src, bfloat 0.0)
@ -346,6 +377,7 @@ define amdgpu_ps bfloat @test_clamp_bf16_s(bfloat inreg %src) {
define amdgpu_ps float @test_clamp_v2bf16(<2 x bfloat> %src) {
; GCN-LABEL: test_clamp_v2bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v0, v0, v0 clamp
; GCN-NEXT: ; return to shader part epilog
%max = call <2 x bfloat> @llvm.maxnum.v2bf16(<2 x bfloat> %src, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
@ -357,6 +389,7 @@ define amdgpu_ps float @test_clamp_v2bf16(<2 x bfloat> %src) {
define amdgpu_ps float @test_clamp_v2bf16_s(<2 x bfloat> inreg %src) {
; GCN-LABEL: test_clamp_v2bf16_s:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_max_num_bf16 v0, s0, s0 clamp
; GCN-NEXT: ; return to shader part epilog
%max = call <2 x bfloat> @llvm.maxnum.v2bf16(<2 x bfloat> %src, <2 x bfloat> <bfloat 0.0, bfloat 0.0>)
@ -368,6 +401,7 @@ define amdgpu_ps float @test_clamp_v2bf16_s(<2 x bfloat> inreg %src) {
define amdgpu_ps bfloat @test_clamp_bf16_folding(bfloat %src) {
; GCN-LABEL: test_clamp_bf16_folding:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_exp_bf16_e32 v0, v0
; GCN-NEXT: v_nop
; GCN-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
@ -382,6 +416,7 @@ define amdgpu_ps bfloat @test_clamp_bf16_folding(bfloat %src) {
define amdgpu_ps float @test_clamp_v2bf16_folding(<2 x bfloat> %src0, <2 x bfloat> %src1) {
; GCN-LABEL: test_clamp_v2bf16_folding:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_mul_bf16 v0, v0, v1 clamp
; GCN-NEXT: ; return to shader part epilog
%mul = fmul <2 x bfloat> %src0, %src1
@ -394,6 +429,7 @@ define amdgpu_ps float @test_clamp_v2bf16_folding(<2 x bfloat> %src0, <2 x bfloa
define amdgpu_ps void @v_test_mul_add_v2bf16_vvv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
; GCN-LABEL: v_test_mul_add_v2bf16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, v3, v4
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -406,6 +442,7 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vvv(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_vss(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b, <2 x bfloat> inreg %c) {
; GCN-LABEL: v_test_mul_add_v2bf16_vss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -418,6 +455,7 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vss(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_sss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b, <2 x bfloat> inreg %c) {
; GCN-LABEL: v_test_mul_add_v2bf16_sss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_fma_bf16 v2, s0, s1, v2
@ -432,6 +470,7 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_sss(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_vsc(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_mul_add_v2bf16_vsc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, 0.5 op_sel_hi:[1,1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -444,6 +483,7 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vsc(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_mul_add_v2bf16_vll(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_mul_add_v2bf16_vll:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_mov_b32 s0, 0x43484000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_pk_fma_bf16 v2, 0x42c83f80, v2, s0
@ -458,6 +498,7 @@ define amdgpu_ps void @v_test_mul_add_v2bf16_vll(ptr addrspace(1) %out, <2 x bfl
define amdgpu_ps void @v_test_fma_v2bf16_vvv(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) {
; GCN-LABEL: v_test_fma_v2bf16_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, v3, v4
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -469,6 +510,7 @@ define amdgpu_ps void @v_test_fma_v2bf16_vvv(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_fma_v2bf16_vss(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b, <2 x bfloat> inreg %c) {
; GCN-LABEL: v_test_fma_v2bf16_vss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, s1
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -480,6 +522,7 @@ define amdgpu_ps void @v_test_fma_v2bf16_vss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_fma_v2bf16_sss(ptr addrspace(1) %out, <2 x bfloat> inreg %a, <2 x bfloat> inreg %b, <2 x bfloat> inreg %c) {
; GCN-LABEL: v_test_fma_v2bf16_sss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_pk_fma_bf16 v2, s0, s1, v2
@ -493,6 +536,7 @@ define amdgpu_ps void @v_test_fma_v2bf16_sss(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_fma_v2bf16_vsc(ptr addrspace(1) %out, <2 x bfloat> %a, <2 x bfloat> inreg %b) {
; GCN-LABEL: v_test_fma_v2bf16_vsc:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, 0.5 op_sel_hi:[1,1,0]
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -504,6 +548,7 @@ define amdgpu_ps void @v_test_fma_v2bf16_vsc(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @v_test_fma_v2bf16_vll(ptr addrspace(1) %out, <2 x bfloat> %a) {
; GCN-LABEL: v_test_fma_v2bf16_vll:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_mov_b32 s0, 0x42c83f80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_pk_fma_bf16 v2, v2, s0, 0x43484000
@ -517,6 +562,7 @@ define amdgpu_ps void @v_test_fma_v2bf16_vll(ptr addrspace(1) %out, <2 x bfloat>
define amdgpu_ps void @llvm_log2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
; GCN-LABEL: llvm_log2_bf16_v:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_log_bf16_e32 v2, v2
; GCN-NEXT: global_store_b16 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -528,6 +574,7 @@ define amdgpu_ps void @llvm_log2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
define amdgpu_ps void @llvm_log2_bf16_s(ptr addrspace(1) %out, bfloat inreg %src) {
; GCN-LABEL: llvm_log2_bf16_s:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_log_bf16_e32 v2, s0
; GCN-NEXT: global_store_b16 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -539,6 +586,7 @@ define amdgpu_ps void @llvm_log2_bf16_s(ptr addrspace(1) %out, bfloat inreg %src
define amdgpu_ps void @llvm_exp2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
; GCN-LABEL: llvm_exp2_bf16_v:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_exp_bf16_e32 v2, v2
; GCN-NEXT: global_store_b16 v[0:1], v2, off
; GCN-NEXT: s_endpgm
@ -550,6 +598,7 @@ define amdgpu_ps void @llvm_exp2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
define amdgpu_ps void @llvm_exp2_bf16_s(ptr addrspace(1) %out, bfloat inreg %src) {
; GCN-LABEL: llvm_exp2_bf16_s:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_exp_bf16_e32 v2, s0
; GCN-NEXT: global_store_b16 v[0:1], v2, off
; GCN-NEXT: s_endpgm

13
llvm/test/CodeGen/AMDGPU/bf16.ll
View File

@ -21317,6 +21317,7 @@ define amdgpu_ps i32 @s_fabs_bf16(bfloat inreg %a) {
;
; GFX1250-LABEL: s_fabs_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_and_b32 s0, s0, 0x7fff
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_b32 s0, 0xffff, s0
@ -21433,6 +21434,7 @@ define amdgpu_ps i32 @s_fneg_bf16(bfloat inreg %a) {
;
; GFX1250-LABEL: s_fneg_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_xor_b32 s0, s0, 0x8000
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_b32 s0, 0xffff, s0
@ -21554,6 +21556,7 @@ define amdgpu_ps i32 @s_fneg_fabs_bf16(bfloat inreg %a) {
;
; GFX1250-LABEL: s_fneg_fabs_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_bitset1_b32 s0, 15
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_b32 s0, 0xffff, s0
@ -44236,6 +44239,7 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) {
;
; GFX1250TRUE16-LABEL: s_select_bf16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
@ -44246,6 +44250,7 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) {
;
; GFX1250FAKE16-LABEL: s_select_bf16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250FAKE16-NEXT: v_mov_b32_e32 v1, s0
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@ -44392,6 +44397,7 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
;
; GFX1250TRUE16-LABEL: s_select_v2bf16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250TRUE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
@ -44406,6 +44412,7 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
;
; GFX1250FAKE16-LABEL: s_select_v2bf16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250FAKE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250FAKE16-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s0
@ -44558,6 +44565,7 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
;
; GFX1250TRUE16-LABEL: s_vselect_v2bf16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250TRUE16-NEXT: s_lshr_b32 s3, s0, 16
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
@ -44573,6 +44581,7 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
;
; GFX1250FAKE16-LABEL: s_vselect_v2bf16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250FAKE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX1250FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s0
@ -46190,6 +46199,7 @@ define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat>
;
; GFX1250-LABEL: s_select_v3bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
@ -46330,6 +46340,7 @@ define amdgpu_ps <2 x i32> @s_select_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
;
; GFX1250-LABEL: s_select_v4bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s0
; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
@ -46576,6 +46587,7 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
;
; GFX1250TRUE16-LABEL: s_vselect_v4bf16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250TRUE16-NEXT: s_lshr_b32 s7, s1, 16
; GFX1250TRUE16-NEXT: s_lshr_b32 s9, s0, 16
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
@ -46599,6 +46611,7 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
;
; GFX1250FAKE16-LABEL: s_vselect_v4bf16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
; GFX1250FAKE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s1

166
llvm/test/CodeGen/AMDGPU/bitop3.ll
View File

@ -9,10 +9,16 @@
; ========= Single bit functions =========
define amdgpu_ps float @not_and_not_and_not_and(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: not_and_not_and_not_and:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:1
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: not_and_not_and_not_and:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:1
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: not_and_not_and_not_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:1
; GFX1250-NEXT: ; return to shader part epilog
%nota = xor i32 %a, -1
%notb = xor i32 %b, -1
%notc = xor i32 %c, -1
@ -23,10 +29,16 @@ define amdgpu_ps float @not_and_not_and_not_and(i32 %a, i32 %b, i32 %c) {
}
define amdgpu_ps float @not_and_not_and_and(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: not_and_not_and_and:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:2
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: not_and_not_and_and:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:2
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: not_and_not_and_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:2
; GFX1250-NEXT: ; return to shader part epilog
%nota = xor i32 %a, -1
%notb = xor i32 %b, -1
%and1 = and i32 %nota, %c
@ -36,10 +48,16 @@ define amdgpu_ps float @not_and_not_and_and(i32 %a, i32 %b, i32 %c) {
}
define amdgpu_ps float @not_and_and_not_and(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: not_and_and_not_and:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:4
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: not_and_and_not_and:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:4
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: not_and_and_not_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:4
; GFX1250-NEXT: ; return to shader part epilog
%nota = xor i32 %a, -1
%notc = xor i32 %c, -1
%and1 = and i32 %nota, %notc
@ -62,11 +80,13 @@ define amdgpu_ps float @not_and_and_and(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-SDAG-LABEL: not_and_and_and:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:8
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: not_and_and_and:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
@ -79,10 +99,16 @@ define amdgpu_ps float @not_and_and_and(i32 %a, i32 %b, i32 %c) {
}
define amdgpu_ps float @and_not_and_not_and(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: and_not_and_not_and:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x10
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: and_not_and_not_and:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x10
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: and_not_and_not_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x10
; GFX1250-NEXT: ; return to shader part epilog
%notb = xor i32 %b, -1
%notc = xor i32 %c, -1
%and1 = and i32 %a, %notc
@ -105,11 +131,13 @@ define amdgpu_ps float @and_not_and_and(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-SDAG-LABEL: and_not_and_and:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x20
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: and_not_and_and:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_bfi_b32 v0, v1, 0, v0
@ -135,11 +163,13 @@ define amdgpu_ps float @and_and_not_and(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-SDAG-LABEL: and_and_not_and:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x40
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: and_and_not_and:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0x30
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
@ -152,10 +182,16 @@ define amdgpu_ps float @and_and_not_and(i32 %a, i32 %b, i32 %c) {
}
define amdgpu_ps float @and_and_and(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: and_and_and:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: and_and_and:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: and_and_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x80
; GFX1250-NEXT: ; return to shader part epilog
%and1 = and i32 %a, %c
%and2 = and i32 %and1, %b
%ret_cast = bitcast i32 %and2 to float
@ -165,10 +201,16 @@ define amdgpu_ps float @and_and_and(i32 %a, i32 %b, i32 %c) {
; ========= Multi bit functions =========
define amdgpu_ps float @test_12(i32 %a, i32 %b) {
; GCN-LABEL: test_12:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: test_12:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_12:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc
; GFX1250-NEXT: ; return to shader part epilog
%nota = xor i32 %a, -1
%and1 = and i32 %nota, %b
%ret_cast = bitcast i32 %and1 to float
@ -189,11 +231,13 @@ define amdgpu_ps float @test_63(i32 %a, i32 %b) {
;
; GFX1250-SDAG-LABEL: test_63:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0x3f
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: test_63:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_not_b32_e32 v1, v1
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_bfi_b32 v0, v0, v1, -1
@ -206,10 +250,16 @@ define amdgpu_ps float @test_63(i32 %a, i32 %b) {
}
define amdgpu_ps float @test_59(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_59:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x3b
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: test_59:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x3b
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_59:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x3b
; GFX1250-NEXT: ; return to shader part epilog
%nota = xor i32 %a, -1
%notb = xor i32 %b, -1
%and1 = and i32 %nota, %c
@ -233,11 +283,13 @@ define amdgpu_ps float @test_126(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-SDAG-LABEL: test_126:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v2, v1 bitop3:0x7e
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: test_126:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v1, v0, v1
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -271,11 +323,13 @@ define amdgpu_ps float @test_12_src_overflow(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-SDAG-LABEL: test_12_src_overflow:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, v0 bitop3:0xc
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: test_12_src_overflow:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_not_b32_e32 v3, v0
; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, v2, v0 bitop3:0xc
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@ -317,6 +371,7 @@ define amdgpu_ps float @test_100_src_overflow(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-SDAG-LABEL: test_100_src_overflow:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_bitop3_b32 v3, v1, v2, v0 bitop3:0x10
; GFX1250-SDAG-NEXT: v_bitop3_b32 v4, v0, v2, v1 bitop3:0x40
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v1, v2, v0 bitop3:0x20
@ -326,6 +381,7 @@ define amdgpu_ps float @test_100_src_overflow(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-GISEL-LABEL: test_100_src_overflow:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_or_b32_e32 v3, v2, v0
; GFX1250-GISEL-NEXT: v_bitop3_b32 v4, v0, v1, v0 bitop3:0x30
; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v1, v0
@ -362,6 +418,7 @@ define amdgpu_ps float @test_xor3(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-LABEL: test_xor3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_xor3_b32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%xor1 = xor i32 %a, %b
@ -371,10 +428,16 @@ define amdgpu_ps float @test_xor3(i32 %a, i32 %b, i32 %c) {
}
define amdgpu_ps float @test_or3(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_or3:
; GCN: ; %bb.0:
; GCN-NEXT: v_or3_b32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: test_or3:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_or3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%or1 = or i32 %a, %b
%or2 = or i32 %or1, %c
%ret_cast = bitcast i32 %or2 to float
@ -382,10 +445,16 @@ define amdgpu_ps float @test_or3(i32 %a, i32 %b, i32 %c) {
}
define amdgpu_ps float @test_and_or(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_and_or:
; GCN: ; %bb.0:
; GCN-NEXT: v_and_or_b32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: test_and_or:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: test_and_or:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%and1 = and i32 %a, %b
%or1 = or i32 %and1, %c
%ret_cast = bitcast i32 %or1 to float
@ -404,6 +473,7 @@ define amdgpu_ps float @uniform_3_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
;
; GFX1250-LABEL: uniform_3_op:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_and_not1_b32 s0, s2, s0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT: s_and_b32 s0, s0, s1
@ -433,6 +503,7 @@ define amdgpu_ps float @uniform_4_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
;
; GFX1250-SDAG-LABEL: uniform_4_op:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:2
@ -440,6 +511,7 @@ define amdgpu_ps float @uniform_4_op(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
;
; GFX1250-GISEL-LABEL: uniform_4_op:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_and_not1_b32 s0, s2, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT: s_and_not1_b32 s0, s0, s1
@ -463,21 +535,25 @@ define amdgpu_ps half @not_and_not_and_not_and_b16(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-SDAG-FAKE16-LABEL: not_and_not_and_not_and_b16:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-TRUE16-LABEL: not_and_not_and_not_and_b16:
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: not_and_not_and_not_and_b16:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:1
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: not_and_not_and_not_and_b16:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%nota = xor i16 %a, -1
@ -497,21 +573,25 @@ define amdgpu_ps half @not_and_not_and_and_b16(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-SDAG-FAKE16-LABEL: not_and_not_and_and_b16:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-TRUE16-LABEL: not_and_not_and_and_b16:
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: not_and_not_and_and_b16:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:2
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: not_and_not_and_and_b16:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%nota = xor i16 %a, -1
@ -530,21 +610,25 @@ define amdgpu_ps half @not_and_and_not_and_b16(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-SDAG-FAKE16-LABEL: not_and_and_not_and_b16:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-TRUE16-LABEL: not_and_and_not_and_b16:
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: not_and_and_not_and_b16:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:4
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: not_and_and_not_and_b16:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%nota = xor i16 %a, -1
@ -569,16 +653,19 @@ define amdgpu_ps half @test_xor3_b16(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_xor3_b16:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0x96
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-TRUE16-LABEL: test_xor3_b16:
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0x96
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: test_xor3_b16:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_xor3_b32 v0, v0, v1, v2
; GFX1250-GISEL-NEXT: ; return to shader part epilog
%xor1 = xor i16 %a, %b
@ -600,16 +687,19 @@ define amdgpu_ps half @test_or3_b16(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_or3_b16:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xfe
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-TRUE16-LABEL: test_or3_b16:
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xfe
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: test_or3_b16:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX1250-GISEL-NEXT: ; return to shader part epilog
%or1 = or i16 %a, %b
@ -631,16 +721,19 @@ define amdgpu_ps half @test_and_or_b16(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_and_or_b16:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, v1 bitop3:0xec
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-TRUE16-LABEL: test_and_or_b16:
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v2.l, v1.l bitop3:0xec
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: test_and_or_b16:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_and_or_b32 v0, v0, v1, v2
; GFX1250-GISEL-NEXT: ; return to shader part epilog
%and1 = and i16 %a, %b
@ -649,5 +742,6 @@ define amdgpu_ps half @test_and_or_b16(i16 %a, i16 %b, i16 %c) {
ret half %ret_cast
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
; GFX1250-FAKE16: {{.*}}
; GFX1250-TRUE16: {{.*}}

11
llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
View File

@ -22,6 +22,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {
; GCN-LABEL: uniform_conditional_max_short_forward_branch:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_cmp_eq_u32 s0, 0
@ -62,6 +63,7 @@ bb3:
define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {
; GCN-LABEL: uniform_conditional_min_long_forward_branch:
; GCN: ; %bb.0: ; %bb0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_cmp_eq_u32 s0, 0
@ -104,6 +106,7 @@ bb3:
define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr addrspace(1) %arg, float %cnd) #0 {
; GCN-LABEL: uniform_conditional_min_long_forward_vcnd_branch:
; GCN: ; %bb.0: ; %bb0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_cmp_eq_f32 s0, 0
@ -146,6 +149,7 @@ bb3:
define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
; GCN-LABEL: min_long_forward_vbranch:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0
@ -198,6 +202,7 @@ bb3:
define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {
; GCN-LABEL: long_backward_sbranch:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: .LBB4_1: ; %bb2
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
@ -238,6 +243,7 @@ bb3:
define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %arg1) {
; GCN-LABEL: uniform_unconditional_min_long_forward_branch:
; GCN: ; %bb.0: ; %bb0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_cmp_eq_u32 s0, 0
@ -299,6 +305,7 @@ bb4:
define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr addrspace(1) %arg, i32 %arg1) {
; GCN-LABEL: uniform_unconditional_min_long_backward_branch:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_mov_b32 vcc_lo, exec_lo
; GCN-NEXT: .LBB6_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
@ -334,6 +341,7 @@ loop:
define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
; GCN-LABEL: expand_requires_expand:
; GCN: ; %bb.0: ; %bb0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b32 s0, s[4:5], 0x24
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_cmp_lt_i32 s0, 0
@ -401,6 +409,7 @@ bb3:
define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 %cond) #0 {
; GCN-LABEL: uniform_inside_divergent:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GCN-NEXT: s_mov_b32 s3, exec_lo
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -450,6 +459,7 @@ endif:
define amdgpu_kernel void @analyze_mask_branch() #0 {
; GCN-LABEL: analyze_mask_branch:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_mov_b32 s0, exec_lo
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: v_mov_b32_e64 v0, 0
@ -518,6 +528,7 @@ ret:
define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {
; GCN-LABEL: long_branch_hang:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GCN-NEXT: s_mov_b32 s7, -1
; GCN-NEXT: s_wait_kmcnt 0x0

101
llvm/test/CodeGen/AMDGPU/calling-conventions.ll
View File

@ -39,6 +39,7 @@ define spir_kernel void @kernel(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: kernel:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -83,11 +84,15 @@ define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
;
; GFX1250-TRUE16-LABEL: ps_ret_cc_f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: ps_ret_cc_f16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%add = fadd half %arg0, 1.0
@ -119,6 +124,8 @@ define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
;
; GFX1250-LABEL: ps_ret_cc_inreg_f16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: s_add_f16 s0, s0, 1.0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
@ -277,6 +284,8 @@ define amdgpu_kernel void @call_coldcc() #0 {
;
; GFX1250-LABEL: call_coldcc:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_mov_b32 s32, 0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX1250-NEXT: s_get_pc_i64 s[6:7]
; GFX1250-NEXT: s_add_nc_u64 s[6:7], s[6:7], coldcc@gotpcrel+4
@ -286,7 +295,6 @@ define amdgpu_kernel void @call_coldcc() #0 {
; GFX1250-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1250-NEXT: s_mov_b32 s32, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[12:13]
; GFX1250-NEXT: global_store_b32 v[0:1], v0, off
@ -388,6 +396,8 @@ define amdgpu_kernel void @call_fastcc() #0 {
;
; GFX1250-LABEL: call_fastcc:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_mov_b32 s32, 0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX1250-NEXT: s_get_pc_i64 s[6:7]
; GFX1250-NEXT: s_add_nc_u64 s[6:7], s[6:7], fastcc@gotpcrel+4
@ -397,7 +407,6 @@ define amdgpu_kernel void @call_fastcc() #0 {
; GFX1250-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1250-NEXT: s_mov_b32 s32, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[12:13]
; GFX1250-NEXT: global_store_b32 v[0:1], v0, off
@ -433,11 +442,15 @@ define amdgpu_cs half @cs_mesa(half %arg0) {
;
; GFX1250-TRUE16-LABEL: cs_mesa:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: cs_mesa:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%add = fadd half %arg0, 1.0
@ -470,11 +483,15 @@ define amdgpu_ps half @ps_mesa_f16(half %arg0) {
;
; GFX1250-TRUE16-LABEL: ps_mesa_f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: ps_mesa_f16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%add = fadd half %arg0, 1.0
@ -507,11 +524,15 @@ define amdgpu_vs half @vs_mesa(half %arg0) {
;
; GFX1250-TRUE16-LABEL: vs_mesa:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: vs_mesa:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%add = fadd half %arg0, 1.0
@ -544,11 +565,15 @@ define amdgpu_gs half @gs_mesa(half %arg0) {
;
; GFX1250-TRUE16-LABEL: gs_mesa:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: gs_mesa:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%add = fadd half %arg0, 1.0
@ -581,11 +606,15 @@ define amdgpu_hs half @hs_mesa(half %arg0) {
;
; GFX1250-TRUE16-LABEL: hs_mesa:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: hs_mesa:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%add = fadd half %arg0, 1.0
@ -620,6 +649,8 @@ define amdgpu_ps <2 x half> @ps_mesa_v2f16(<2 x half> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v2f16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
; GFX1250-NEXT: ; return to shader part epilog
%add = fadd <2 x half> %arg0, <half 1.0, half 1.0>
@ -654,6 +685,8 @@ define amdgpu_ps <2 x half> @ps_mesa_inreg_v2f16(<2 x half> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v2f16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_pk_add_f16 v0, s0, 1.0 op_sel_hi:[1,0]
; GFX1250-NEXT: ; return to shader part epilog
%add = fadd <2 x half> %arg0, <half 1.0, half 1.0>
@ -690,6 +723,7 @@ define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v2i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0]
; GFX1250-NEXT: global_store_b32 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
@ -731,6 +765,7 @@ define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v2i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_pk_add_u16 v0, s0, 1 op_sel_hi:[1,0]
; GFX1250-NEXT: global_store_b32 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
@ -777,6 +812,8 @@ define amdgpu_ps <4 x half> @ps_mesa_v4f16(<4 x half> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v4f16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
; GFX1250-NEXT: v_pk_add_f16 v1, v1, 1.0 op_sel_hi:[1,0]
; GFX1250-NEXT: ; return to shader part epilog
@ -824,6 +861,8 @@ define amdgpu_ps <4 x half> @ps_mesa_inreg_v4f16(<4 x half> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v4f16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_pk_add_f16 v0, s0, 1.0 op_sel_hi:[1,0]
; GFX1250-NEXT: v_pk_add_f16 v1, s1, 1.0 op_sel_hi:[1,0]
; GFX1250-NEXT: ; return to shader part epilog
@ -871,6 +910,7 @@ define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v3i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_co_i32 s2, s2, 3
; GFX1250-NEXT: s_add_co_i32 s0, s0, 1
; GFX1250-NEXT: s_add_co_i32 s1, s1, 2
@ -914,6 +954,7 @@ define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v3f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_f32 s0, s0, 1.0
; GFX1250-NEXT: s_add_f32 s1, s1, 2.0
; GFX1250-NEXT: s_add_f32 s2, s2, 4.0
@ -980,6 +1021,7 @@ define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v5i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_co_i32 s3, s3, 4
; GFX1250-NEXT: s_add_co_i32 s2, s2, 3
; GFX1250-NEXT: s_add_co_i32 s1, s1, 2
@ -1037,6 +1079,7 @@ define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_v5f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_f32 s3, s3, -1.0
; GFX1250-NEXT: s_add_f32 s4, s4, 0.5
; GFX1250-NEXT: s_add_f32 s0, s0, 1.0
@ -1085,6 +1128,7 @@ define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v3i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_add_nc_u32 v2, 3, v2 :: v_dual_add_nc_u32 v1, 2, v1
; GFX1250-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX1250-NEXT: global_store_b96 v[0:1], v[0:2], off
@ -1123,6 +1167,7 @@ define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v3f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_add_f32 v2, 4.0, v2 :: v_dual_add_f32 v1, 2.0, v1
; GFX1250-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX1250-NEXT: global_store_b96 v[0:1], v[0:2], off
@ -1171,6 +1216,7 @@ define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v5i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_add_nc_u32 v3, 4, v3 :: v_dual_add_nc_u32 v2, 3, v2
; GFX1250-NEXT: v_dual_add_nc_u32 v1, 2, v1 :: v_dual_add_nc_u32 v4, 5, v4
; GFX1250-NEXT: v_add_nc_u32_e32 v0, 1, v0
@ -1220,6 +1266,7 @@ define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
;
; GFX1250-LABEL: ps_mesa_v5f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_add_f32 v3, -1.0, v3 :: v_dual_add_f32 v2, 4.0, v2
; GFX1250-NEXT: v_dual_add_f32 v1, 2.0, v1 :: v_dual_add_f32 v4, 0.5, v4
; GFX1250-NEXT: v_add_f32_e32 v0, 1.0, v0
@ -1261,12 +1308,14 @@ define amdgpu_ps void @ps_mesa_i16(i16 %arg0) {
;
; GFX1250-TRUE16-LABEL: ps_mesa_i16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.l
; GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
; GFX1250-TRUE16-NEXT: s_endpgm
;
; GFX1250-FAKE16-LABEL: ps_mesa_i16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_add_nc_u16 v0, v0, v0
; GFX1250-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
; GFX1250-FAKE16-NEXT: s_endpgm
@ -1302,6 +1351,7 @@ define amdgpu_ps void @ps_mesa_inreg_i16(i16 inreg %arg0) {
;
; GFX1250-LABEL: ps_mesa_inreg_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
@ -1313,10 +1363,26 @@ define amdgpu_ps void @ps_mesa_inreg_i16(i16 inreg %arg0) {
}
define amdgpu_ps i16 @ret_ps_mesa_i16() {
; GCN-LABEL: ret_ps_mesa_i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_movk_i32 s0, 0x7b
; GCN-NEXT: ; return to shader part epilog
; SI-LABEL: ret_ps_mesa_i16:
; SI: ; %bb.0:
; SI-NEXT: s_movk_i32 s0, 0x7b
; SI-NEXT: ; return to shader part epilog
;
; VI-LABEL: ret_ps_mesa_i16:
; VI: ; %bb.0:
; VI-NEXT: s_movk_i32 s0, 0x7b
; VI-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: ret_ps_mesa_i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_movk_i32 s0, 0x7b
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: ret_ps_mesa_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_movk_i32 s0, 0x7b
; GFX1250-NEXT: ; return to shader part epilog
ret i16 123
}
@ -1353,6 +1419,7 @@ define amdgpu_kernel void @amd_kernel_i8(i8 %arg0) {
;
; GFX1250-LABEL: amd_kernel_i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
@ -1418,6 +1485,7 @@ define amdgpu_kernel void @amd_kernel_v2i8(<2 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v2i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1519,6 +1587,7 @@ define amdgpu_kernel void @amd_kernel_v4i8(<4 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v4i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1617,6 +1686,7 @@ define amdgpu_kernel void @amd_kernel_v3i8(<3 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v3i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 2
; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 0
@ -1737,6 +1807,7 @@ define amdgpu_kernel void @amd_kernel_v5i8(<5 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v5i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4
; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 0
@ -1902,6 +1973,7 @@ define amdgpu_kernel void @amd_kernel_v8i8(<8 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v8i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -2179,6 +2251,7 @@ define amdgpu_kernel void @amd_kernel_v16i8(<16 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v16i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[4:5], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -2700,6 +2773,7 @@ define amdgpu_kernel void @amd_kernel_v32i8(<32 x i8> %arg0) {
;
; GFX1250-LABEL: amd_kernel_v32i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[8:9], 16
; GFX1250-NEXT: v_mov_b64_e32 v[10:11], 0
@ -2869,6 +2943,7 @@ define amdgpu_cs void @amdgpu_cs_i1(i1 %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0
; GFX1250-NEXT: global_store_b8 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
@ -2993,6 +3068,7 @@ define amdgpu_cs void @amdgpu_cs_v8i1(<8 x i1> %arg0) {
;
; GFX1250-TRUE16-LABEL: amdgpu_cs_v8i1:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v2.h, 3, v3.l
; GFX1250-TRUE16-NEXT: v_and_b16 v3.l, v6.l, 1
; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 1
@ -3018,6 +3094,7 @@ define amdgpu_cs void @amdgpu_cs_v8i1(<8 x i1> %arg0) {
;
; GFX1250-FAKE16-LABEL: amdgpu_cs_v8i1:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v7
@ -3258,6 +3335,7 @@ define amdgpu_cs void @amdgpu_cs_v16i1(<16 x i1> %arg0) {
;
; GFX1250-TRUE16-LABEL: amdgpu_cs_v16i1:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_and_b16 v2.h, v6.l, 1
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, 3, v7.l
; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, v10.l, 1
@ -3302,6 +3380,7 @@ define amdgpu_cs void @amdgpu_cs_v16i1(<16 x i1> %arg0) {
;
; GFX1250-FAKE16-LABEL: amdgpu_cs_v16i1:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v7
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
@ -3742,6 +3821,7 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
;
; GFX1250-TRUE16-LABEL: amdgpu_cs_v32i1:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v18.h, 3, v19.l
; GFX1250-TRUE16-NEXT: v_and_b16 v19.l, v22.l, 1
; GFX1250-TRUE16-NEXT: v_and_b16 v18.l, v18.l, 1
@ -3819,6 +3899,7 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
;
; GFX1250-FAKE16-LABEL: amdgpu_cs_v32i1:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v3
@ -3930,6 +4011,7 @@ define amdgpu_cs void @amdgpu_cs_inreg_i1(i1 inreg %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_inreg_i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_and_b32 s0, s0, 1
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
@ -4026,6 +4108,7 @@ define amdgpu_cs void @amdgpu_cs_inreg_v8i1(<8 x i1> inreg %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_inreg_v8i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_and_b32 s6, s6, 1
; GFX1250-NEXT: s_lshl_b32 s5, s5, 1
; GFX1250-NEXT: s_and_b32 s4, s4, 1
@ -4214,6 +4297,7 @@ define amdgpu_cs void @amdgpu_cs_inreg_v16i1(<16 x i1> inreg %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_inreg_v16i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_and_b32 s10, s10, 1
; GFX1250-NEXT: s_lshl_b32 s9, s9, 1
; GFX1250-NEXT: s_and_b32 s8, s8, 1
@ -4570,6 +4654,7 @@ define amdgpu_cs void @amdgpu_cs_inreg_v32i1(<32 x i1> inreg %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_inreg_v32i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_and_b32 s10, s10, 1
; GFX1250-NEXT: s_lshl_b32 s9, s9, 1
; GFX1250-NEXT: s_and_b32 s8, s8, 1
@ -4694,6 +4779,7 @@ define amdgpu_cs void @amdgpu_cs_i1_sext(i1 signext %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_i1_sext:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0
; GFX1250-NEXT: global_store_b8 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
@ -4721,6 +4807,7 @@ define amdgpu_cs void @amdgpu_cs_i1_zext(i1 zeroext %arg0) {
;
; GFX1250-LABEL: amdgpu_cs_i1_zext:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_store_b8 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
store i1 %arg0, ptr addrspace(1) poison
@ -4728,3 +4815,5 @@ define amdgpu_cs void @amdgpu_cs_i1_zext(i1 zeroext %arg0) {
}
attributes #0 = { nounwind noinline }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}

17
llvm/test/CodeGen/AMDGPU/carryout-selection.ll
View File

@ -117,6 +117,7 @@ define amdgpu_kernel void @sadd64rr(ptr addrspace(1) %out, i64 %a, i64 %b) {
;
; GFX1250-LABEL: sadd64rr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -228,6 +229,7 @@ define amdgpu_kernel void @sadd64ri(ptr addrspace(1) %out, i64 %a) {
;
; GFX1250-LABEL: sadd64ri:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -329,6 +331,7 @@ define amdgpu_kernel void @vadd64rr(ptr addrspace(1) %out, i64 %a) {
;
; GFX1250-LABEL: vadd64rr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
@ -430,6 +433,7 @@ define amdgpu_kernel void @vadd64ri(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: vadd64ri:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
@ -536,6 +540,7 @@ define amdgpu_kernel void @suaddo32(ptr addrspace(1) %out, ptr addrspace(1) %car
;
; GFX1250-LABEL: suaddo32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
@ -668,6 +673,7 @@ define amdgpu_kernel void @uaddo32_vcc_user(ptr addrspace(1) %out, ptr addrspace
;
; GFX1250-LABEL: uaddo32_vcc_user:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -813,6 +819,7 @@ define amdgpu_kernel void @suaddo64(ptr addrspace(1) %out, ptr addrspace(1) %car
;
; GFX1250-LABEL: suaddo64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_add_co_u32 s0, s12, s14
@ -955,6 +962,7 @@ define amdgpu_kernel void @vuaddo64(ptr addrspace(1) %out, ptr addrspace(1) %car
;
; GFX1250-LABEL: vuaddo64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1086,6 +1094,7 @@ define amdgpu_kernel void @ssub64rr(ptr addrspace(1) %out, i64 %a, i64 %b) {
;
; GFX1250-LABEL: ssub64rr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -1197,6 +1206,7 @@ define amdgpu_kernel void @ssub64ri(ptr addrspace(1) %out, i64 %a) {
;
; GFX1250-LABEL: ssub64ri:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1298,6 +1308,7 @@ define amdgpu_kernel void @vsub64rr(ptr addrspace(1) %out, i64 %a) {
;
; GFX1250-LABEL: vsub64rr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
@ -1399,6 +1410,7 @@ define amdgpu_kernel void @vsub64ri(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: vsub64ri:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
@ -1506,6 +1518,7 @@ define amdgpu_kernel void @susubo32(ptr addrspace(1) %out, ptr addrspace(1) %car
;
; GFX1250-LABEL: susubo32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
@ -1638,6 +1651,7 @@ define amdgpu_kernel void @usubo32_vcc_user(ptr addrspace(1) %out, ptr addrspace
;
; GFX1250-LABEL: usubo32_vcc_user:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1783,6 +1797,7 @@ define amdgpu_kernel void @susubo64(ptr addrspace(1) %out, ptr addrspace(1) %car
;
; GFX1250-LABEL: susubo64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_sub_co_u32 s0, s12, s14
@ -1925,6 +1940,7 @@ define amdgpu_kernel void @vusubo64(ptr addrspace(1) %out, ptr addrspace(1) %car
;
; GFX1250-LABEL: vusubo64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -3041,6 +3057,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
;
; GFX1250-LABEL: sudiv64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34

3
llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
View File

@ -581,6 +581,7 @@ define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
;
; GFX1250-LABEL: s_fmaak_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; encoding: [0x41,0x06,0x80,0xb9,0x01,0x00,0x00,0x00]
; GFX1250-NEXT: s_fmaak_f32 s0, s0, s1, 0x43800000 ; encoding: [0x00,0x01,0x80,0xa2,0x00,0x00,0x80,0x43]
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; encoding: [0x0b,0x00,0x87,0xbf]
; GFX1250-NEXT: v_mov_b32_e32 v0, s0 ; encoding: [0x00,0x02,0x00,0x7e]
@ -594,7 +595,7 @@ define amdgpu_ps float @s_fmaak_f32(float inreg %x, float inreg %y) {
; GFX1100: codeLenInByte = 16
; GFX1150: codeLenInByte = 16
; GFX1200: codeLenInByte = 16
; GFX1250: codeLenInByte = 16
; GFX1250: codeLenInByte = 24
define double @v_mul_f64_vop2_literal_32(double %x) {
; GFX9-LABEL: v_mul_f64_vop2_literal_32:

34
llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll
View File

@ -10,6 +10,7 @@
define amdgpu_kernel void @simple_read2_f32(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -35,6 +36,7 @@ define amdgpu_kernel void @simple_read2_f32(ptr addrspace(1) %out) #0 {
define amdgpu_kernel void @simple_read2_f32_max_offset(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_max_offset:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -60,6 +62,7 @@ define amdgpu_kernel void @simple_read2_f32_max_offset(ptr addrspace(1) %out) #0
define amdgpu_kernel void @simple_read2_f32_too_far(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_too_far:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -86,6 +89,7 @@ define amdgpu_kernel void @simple_read2_f32_too_far(ptr addrspace(1) %out) #0 {
define amdgpu_kernel void @simple_read2_f32_x2(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_x2:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@ -127,6 +131,7 @@ define amdgpu_kernel void @simple_read2_f32_x2(ptr addrspace(1) %out) #0 {
define amdgpu_kernel void @simple_read2_f32_x2_barrier(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_x2_barrier:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -174,6 +179,7 @@ define amdgpu_kernel void @simple_read2_f32_x2_barrier(ptr addrspace(1) %out) #0
define amdgpu_kernel void @simple_read2_f32_x2_nonzero_base(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_x2_nonzero_base:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@ -219,6 +225,7 @@ define amdgpu_kernel void @simple_read2_f32_x2_nonzero_base(ptr addrspace(1) %ou
define amdgpu_kernel void @read2_ptr_is_subreg_arg_f32(ptr addrspace(1) %out, <2 x ptr addrspace(3)> %lds.ptr) #0 {
; GFX1250-LABEL: read2_ptr_is_subreg_arg_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -251,6 +258,7 @@ define amdgpu_kernel void @read2_ptr_is_subreg_arg_f32(ptr addrspace(1) %out, <2
define amdgpu_kernel void @read2_ptr_is_subreg_arg_offset_f32(ptr addrspace(1) %out, <2 x ptr addrspace(3)> %lds.ptr) #0 {
; GFX1250-LABEL: read2_ptr_is_subreg_arg_offset_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -283,6 +291,7 @@ define amdgpu_kernel void @read2_ptr_is_subreg_arg_offset_f32(ptr addrspace(1) %
define amdgpu_kernel void @read2_ptr_is_subreg_f32(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: read2_ptr_is_subreg_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -314,6 +323,7 @@ define amdgpu_kernel void @read2_ptr_is_subreg_f32(ptr addrspace(1) %out) #0 {
define amdgpu_kernel void @simple_read2_f32_volatile_0(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_volatile_0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -340,6 +350,7 @@ define amdgpu_kernel void @simple_read2_f32_volatile_0(ptr addrspace(1) %out) #0
define amdgpu_kernel void @simple_read2_f32_volatile_1(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f32_volatile_1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -367,6 +378,7 @@ define amdgpu_kernel void @simple_read2_f32_volatile_1(ptr addrspace(1) %out) #0
define amdgpu_kernel void @unaligned_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {
; GFX1250-LABEL: unaligned_read2_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@ -393,6 +405,7 @@ define amdgpu_kernel void @unaligned_read2_f32(ptr addrspace(1) %out, ptr addrsp
define amdgpu_kernel void @unaligned_offset_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {
; GFX1250-LABEL: unaligned_offset_read2_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@ -419,6 +432,7 @@ define amdgpu_kernel void @unaligned_offset_read2_f32(ptr addrspace(1) %out, ptr
define amdgpu_kernel void @misaligned_2_simple_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {
; GFX1250-LABEL: misaligned_2_simple_read2_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@ -445,12 +459,14 @@ define amdgpu_kernel void @misaligned_2_simple_read2_f32(ptr addrspace(1) %out,
define amdgpu_kernel void @simple_read2_f64(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0
; GFX1250-NEXT: ds_load_2addr_b64 v[0:3], v4 offset1:8
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]
@ -470,12 +486,14 @@ define amdgpu_kernel void @simple_read2_f64(ptr addrspace(1) %out) #0 {
define amdgpu_kernel void @simple_read2_f64_max_offset(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f64_max_offset:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0
; GFX1250-NEXT: ds_load_2addr_b64 v[0:3], v4 offset1:255
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]
@ -495,6 +513,7 @@ define amdgpu_kernel void @simple_read2_f64_max_offset(ptr addrspace(1) %out) #0
define amdgpu_kernel void @simple_read2_f64_too_far(ptr addrspace(1) %out) #0 {
; GFX1250-LABEL: simple_read2_f64_too_far:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -502,6 +521,7 @@ define amdgpu_kernel void @simple_read2_f64_too_far(ptr addrspace(1) %out) #0 {
; GFX1250-NEXT: ds_load_b64 v[0:1], v4
; GFX1250-NEXT: ds_load_b64 v[2:3], v4 offset:2056
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]
@ -522,6 +542,7 @@ define amdgpu_kernel void @simple_read2_f64_too_far(ptr addrspace(1) %out) #0 {
define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {
; GFX1250-LABEL: misaligned_read2_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@ -531,6 +552,7 @@ define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrs
; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:1
; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v2 offset0:14 offset1:15
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1250-NEXT: s_endpgm
@ -551,6 +573,7 @@ define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrs
define amdgpu_kernel void @load_constant_adjacent_offsets(ptr addrspace(1) %out) {
; GFX1250-LABEL: load_constant_adjacent_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: ds_load_b64 v[0:1], v2
@ -569,6 +592,7 @@ define amdgpu_kernel void @load_constant_adjacent_offsets(ptr addrspace(1) %out)
define amdgpu_kernel void @load_constant_disjoint_offsets(ptr addrspace(1) %out) {
; GFX1250-LABEL: load_constant_disjoint_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:2
@ -589,6 +613,7 @@ define amdgpu_kernel void @load_constant_disjoint_offsets(ptr addrspace(1) %out)
define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %out) {
; GFX1250-LABEL: load_misaligned64_constant_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: ds_load_b128 v[0:3], v4
@ -609,6 +634,7 @@ define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %
define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspace(1) %out) {
; GFX1250-LABEL: load_misaligned64_constant_large_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: ds_load_b64 v[0:1], v4 offset:16384
@ -631,6 +657,7 @@ define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspac
define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb) #0 {
; GFX1250-LABEL: sgemm_inner_loop_read2_sequence:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c
; GFX1250-NEXT: s_and_b32 s1, ttmp6, 15
; GFX1250-NEXT: s_add_co_i32 s0, s0, 1
@ -719,6 +746,7 @@ define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(ptr addrspace(1) %C,
define amdgpu_kernel void @misaligned_read2_v2i32(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {
; GFX1250-LABEL: misaligned_read2_v2i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2
@ -734,6 +762,7 @@ define amdgpu_kernel void @misaligned_read2_v2i32(ptr addrspace(1) %out, ptr add
define amdgpu_kernel void @misaligned_read2_i64(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {
; GFX1250-LABEL: misaligned_read2_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2
@ -749,6 +778,7 @@ define amdgpu_kernel void @misaligned_read2_i64(ptr addrspace(1) %out, ptr addrs
define amdgpu_kernel void @ds_read_diff_base_interleaving(
; GFX1250-LABEL: ds_read_diff_base_interleaving:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_dual_lshrrev_b32 v1, 6, v0 :: v_dual_lshlrev_b32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@ -815,6 +845,8 @@ bb:
define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspace(3) %arg) {
; GFX1250-LABEL: ds_read_call_read:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_mov_b32 s32, 0
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[36:38], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-NEXT: v_dual_mov_b32 v42, 0 :: v_dual_mov_b32 v31, v0
@ -824,7 +856,6 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX1250-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1250-NEXT: s_mov_b32 s32, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_lshl_add_u32 v40, v1, 2, s38
; GFX1250-NEXT: ds_load_b32 v41, v40
@ -850,6 +881,7 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out) {
; GFX1250-LABEL: read2_v2i32_align1_odd_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: ds_load_b64 v[0:1], v2 offset:65

23
llvm/test/CodeGen/AMDGPU/ds_write2.ll
View File

@ -34,6 +34,7 @@ define amdgpu_kernel void @simple_write2_one_val_f32(ptr addrspace(1) %C, ptr ad
;
; GFX1250-LABEL: simple_write2_one_val_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -85,6 +86,7 @@ define amdgpu_kernel void @simple_write2_two_val_f32(ptr addrspace(1) %C, ptr ad
;
; GFX1250-LABEL: simple_write2_two_val_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -145,6 +147,7 @@ define amdgpu_kernel void @simple_write2_two_val_f32_volatile_0(ptr addrspace(1)
;
; GFX1250-LABEL: simple_write2_two_val_f32_volatile_0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -206,6 +209,7 @@ define amdgpu_kernel void @simple_write2_two_val_f32_volatile_1(ptr addrspace(1)
;
; GFX1250-LABEL: simple_write2_two_val_f32_volatile_1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -271,6 +275,7 @@ define amdgpu_kernel void @simple_write2_two_val_subreg2_mixed_f32(ptr addrspace
;
; GFX1250-LABEL: simple_write2_two_val_subreg2_mixed_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -325,6 +330,7 @@ define amdgpu_kernel void @simple_write2_two_val_subreg2_f32(ptr addrspace(1) %C
;
; GFX1250-LABEL: simple_write2_two_val_subreg2_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -376,6 +382,7 @@ define amdgpu_kernel void @simple_write2_two_val_subreg4_f32(ptr addrspace(1) %C
;
; GFX1250-LABEL: simple_write2_two_val_subreg4_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -428,6 +435,7 @@ define amdgpu_kernel void @simple_write2_two_val_max_offset_f32(ptr addrspace(1)
;
; GFX1250-LABEL: simple_write2_two_val_max_offset_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -488,6 +496,7 @@ define amdgpu_kernel void @simple_write2_two_val_too_far_f32(ptr addrspace(1) %C
;
; GFX1250-LABEL: simple_write2_two_val_too_far_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -548,6 +557,7 @@ define amdgpu_kernel void @simple_write2_two_val_f32_x2(ptr addrspace(1) %C, ptr
;
; GFX1250-LABEL: simple_write2_two_val_f32_x2:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -619,6 +629,7 @@ define amdgpu_kernel void @simple_write2_two_val_f32_x2_nonzero_base(ptr addrspa
;
; GFX1250-LABEL: simple_write2_two_val_f32_x2_nonzero_base:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -698,6 +709,7 @@ define amdgpu_kernel void @write2_ptr_subreg_arg_two_val_f32(ptr addrspace(1) %C
;
; GFX1250-LABEL: write2_ptr_subreg_arg_two_val_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -761,6 +773,7 @@ define amdgpu_kernel void @simple_write2_one_val_f64(ptr addrspace(1) %C, ptr ad
;
; GFX1250-LABEL: simple_write2_one_val_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -814,6 +827,7 @@ define amdgpu_kernel void @misaligned_simple_write2_one_val_f64(ptr addrspace(1)
;
; GFX1250-LABEL: misaligned_simple_write2_one_val_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -913,6 +927,7 @@ define amdgpu_kernel void @unaligned_offset_simple_write2_one_val_f64(ptr addrsp
;
; GFX1250-LABEL: unaligned_offset_simple_write2_one_val_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -967,6 +982,7 @@ define amdgpu_kernel void @simple_write2_two_val_f64(ptr addrspace(1) %C, ptr ad
;
; GFX1250-LABEL: simple_write2_two_val_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -1013,6 +1029,7 @@ define amdgpu_kernel void @store_constant_adjacent_offsets() {
;
; GFX1250-LABEL: store_constant_adjacent_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0x7b0000007b
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: ds_store_b64 v2, v[0:1]
@ -1040,6 +1057,7 @@ define amdgpu_kernel void @store_constant_disjoint_offsets() {
;
; GFX1250-LABEL: store_constant_disjoint_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0
; GFX1250-NEXT: ds_store_2addr_b32 v1, v0, v0 offset1:2
; GFX1250-NEXT: s_endpgm
@ -1072,6 +1090,7 @@ define amdgpu_kernel void @store_misaligned64_constant_offsets() {
;
; GFX1250-LABEL: store_misaligned64_constant_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v1
@ -1108,6 +1127,7 @@ define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
;
; GFX1250-LABEL: store_misaligned64_constant_large_offsets:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0x7b
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:16384
@ -1167,6 +1187,7 @@ define amdgpu_kernel void @write2_sgemm_sequence(ptr addrspace(1) %C, i32 %lda,
;
; GFX1250-LABEL: write2_sgemm_sequence:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x10
; GFX1250-NEXT: s_and_b32 s2, ttmp6, 15
; GFX1250-NEXT: s_getreg_b32 s3, hwreg(HW_REG_IB_STS2, 6, 4)
@ -1283,6 +1304,7 @@ define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(ptr addrspace(3)
;
; GFX1250-LABEL: simple_write2_v4f32_superreg_align4:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x8
; GFX1250-NEXT: s_load_b32 s8, s[4:5], 0x0
@ -1351,6 +1373,7 @@ define amdgpu_kernel void @write2_v2i32_align1_odd_offset() {
;
; GFX1250-LABEL: write2_v2i32_align1_odd_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0x1c80000007b
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:65

47
llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
View File

@ -18,6 +18,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0
define amdgpu_kernel void @test_fold_canonicalize_undef_value_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_undef_value_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -31,6 +32,7 @@ define amdgpu_kernel void @test_fold_canonicalize_undef_value_bf16(ptr addrspace
define amdgpu_kernel void @v_test_canonicalize_var_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -51,6 +53,7 @@ define amdgpu_kernel void @v_test_canonicalize_var_bf16(ptr addrspace(1) %out) #
define amdgpu_kernel void @s_test_canonicalize_var_bf16(ptr addrspace(1) %out, i16 zeroext %val.arg) #1 {
; GFX1250-LABEL: s_test_canonicalize_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -86,6 +89,7 @@ define <2 x bfloat> @v_test_canonicalize_build_vector_v2bf16(bfloat %lo, bfloat
define amdgpu_kernel void @v_test_canonicalize_fabs_var_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_fabs_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -110,6 +114,7 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_bf16(ptr addrspace(1) %o
define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_fneg_fabs_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -134,6 +139,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_bf16(ptr addrspace(
define amdgpu_kernel void @v_test_canonicalize_fneg_var_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_fneg_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -157,6 +163,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_bf16(ptr addrspace(1) %o
define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_var_bf16(ptr addrspace(1) %out) #2 {
; GFX1250-LABEL: v_test_no_denormals_canonicalize_fneg_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -180,6 +187,7 @@ define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_var_bf16(ptr ad
define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_fabs_var_bf16(ptr addrspace(1) %out) #2 {
; GFX1250-LABEL: v_test_no_denormals_canonicalize_fneg_fabs_var_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -204,6 +212,7 @@ define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_fabs_var_bf16(p
define amdgpu_kernel void @test_fold_canonicalize_p0_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_p0_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -217,6 +226,7 @@ define amdgpu_kernel void @test_fold_canonicalize_p0_bf16(ptr addrspace(1) %out)
define amdgpu_kernel void @test_fold_canonicalize_n0_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_n0_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xffff8000
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -230,6 +240,7 @@ define amdgpu_kernel void @test_fold_canonicalize_n0_bf16(ptr addrspace(1) %out)
define amdgpu_kernel void @test_fold_canonicalize_p1_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_p1_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3f80
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -243,6 +254,7 @@ define amdgpu_kernel void @test_fold_canonicalize_p1_bf16(ptr addrspace(1) %out)
define amdgpu_kernel void @test_fold_canonicalize_n1_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_n1_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xffffbf80
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -256,6 +268,7 @@ define amdgpu_kernel void @test_fold_canonicalize_n1_bf16(ptr addrspace(1) %out)
define amdgpu_kernel void @test_fold_canonicalize_literal_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_literal_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x4180
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -269,6 +282,7 @@ define amdgpu_kernel void @test_fold_canonicalize_literal_bf16(ptr addrspace(1)
define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal0_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_default_denormals_fold_canonicalize_denormal0_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -282,6 +296,7 @@ define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal0_bf
define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_bf16(ptr addrspace(1) %out) #3 {
; GFX1250-LABEL: test_denormals_fold_canonicalize_denormal0_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -295,6 +310,7 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_bf16(ptr a
define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal1_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_default_denormals_fold_canonicalize_denormal1_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xffff83ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -308,6 +324,7 @@ define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal1_bf
define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_bf16(ptr addrspace(1) %out) #3 {
; GFX1250-LABEL: test_denormals_fold_canonicalize_denormal1_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xffff83ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -321,6 +338,7 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_bf16(ptr a
define amdgpu_kernel void @test_fold_canonicalize_qnan_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_qnan_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7c00
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -334,6 +352,7 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_bf16(ptr addrspace(1) %ou
define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_qnan_value_neg1_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7fc0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -347,6 +366,7 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_bf16(ptr addrs
define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_qnan_value_neg2_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7fc0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -360,6 +380,7 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_bf16(ptr addrs
define amdgpu_kernel void @test_fold_canonicalize_snan0_value_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan0_value_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7c01
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -373,6 +394,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_bf16(ptr addrspace
define amdgpu_kernel void @test_fold_canonicalize_snan1_value_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan1_value_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7dff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -386,6 +408,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_bf16(ptr addrspace
define amdgpu_kernel void @test_fold_canonicalize_snan2_value_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan2_value_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xfffffdff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -399,6 +422,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_bf16(ptr addrspace
define amdgpu_kernel void @test_fold_canonicalize_snan3_value_bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan3_value_bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xfffffc01
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -412,6 +436,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_bf16(ptr addrspace
define amdgpu_kernel void @v_test_canonicalize_var_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_var_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -437,6 +462,7 @@ define amdgpu_kernel void @v_test_canonicalize_var_v2bf16(ptr addrspace(1) %out)
define amdgpu_kernel void @v_test_canonicalize_fabs_var_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_fabs_var_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -467,6 +493,7 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_v2bf16(ptr addrspace(1)
define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_fneg_fabs_var_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -498,6 +525,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_v2bf16(ptr addrspac
define amdgpu_kernel void @v_test_canonicalize_fneg_var_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: v_test_canonicalize_fneg_var_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -528,6 +556,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_v2bf16(ptr addrspace(1)
define amdgpu_kernel void @s_test_canonicalize_var_v2bf16(ptr addrspace(1) %out, i32 zeroext %val.arg) #1 {
; GFX1250-LABEL: s_test_canonicalize_var_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -548,6 +577,7 @@ define amdgpu_kernel void @s_test_canonicalize_var_v2bf16(ptr addrspace(1) %out,
define amdgpu_kernel void @test_fold_canonicalize_p0_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_p0_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -561,6 +591,7 @@ define amdgpu_kernel void @test_fold_canonicalize_p0_v2bf16(ptr addrspace(1) %ou
define amdgpu_kernel void @test_fold_canonicalize_n0_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_n0_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x80008000
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -574,6 +605,7 @@ define amdgpu_kernel void @test_fold_canonicalize_n0_v2bf16(ptr addrspace(1) %ou
define amdgpu_kernel void @test_fold_canonicalize_p1_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_p1_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3f803f80
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -587,6 +619,7 @@ define amdgpu_kernel void @test_fold_canonicalize_p1_v2bf16(ptr addrspace(1) %ou
define amdgpu_kernel void @test_fold_canonicalize_n1_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_n1_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xbf80bf80
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -600,6 +633,7 @@ define amdgpu_kernel void @test_fold_canonicalize_n1_v2bf16(ptr addrspace(1) %ou
define amdgpu_kernel void @test_fold_canonicalize_literal_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_literal_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x41804180
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -613,6 +647,7 @@ define amdgpu_kernel void @test_fold_canonicalize_literal_v2bf16(ptr addrspace(1
define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_no_denormals_fold_canonicalize_denormal0_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff03ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -626,6 +661,7 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_v2bf16(
define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_v2bf16(ptr addrspace(1) %out) #3 {
; GFX1250-LABEL: test_denormals_fold_canonicalize_denormal0_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3ff03ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -639,6 +675,7 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_v2bf16(ptr
define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_no_denormals_fold_canonicalize_denormal1_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x83ff83ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -652,6 +689,7 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_v2bf16(
define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_v2bf16(ptr addrspace(1) %out) #3 {
; GFX1250-LABEL: test_denormals_fold_canonicalize_denormal1_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x83ff83ff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -665,6 +703,7 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_v2bf16(ptr
define amdgpu_kernel void @test_fold_canonicalize_qnan_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_qnan_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7c007c00
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -678,6 +717,7 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_v2bf16(ptr addrspace(1) %
define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_qnan_value_neg1_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7fc07fc0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -691,6 +731,7 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_v2bf16(ptr add
define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_qnan_value_neg2_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7fc07fc0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -704,6 +745,7 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_v2bf16(ptr add
define amdgpu_kernel void @test_fold_canonicalize_snan0_value_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan0_value_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7c017c01
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -717,6 +759,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_v2bf16(ptr addrspa
define amdgpu_kernel void @test_fold_canonicalize_snan1_value_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan1_value_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7dff7dff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -730,6 +773,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_v2bf16(ptr addrspa
define amdgpu_kernel void @test_fold_canonicalize_snan2_value_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan2_value_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xfdfffdff
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -743,6 +787,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_v2bf16(ptr addrspa
define amdgpu_kernel void @test_fold_canonicalize_snan3_value_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: test_fold_canonicalize_snan3_value_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xfc01fc01
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -793,6 +838,7 @@ define <4 x bfloat> @v_test_canonicalize_var_v4bf16(<4 x bfloat> %val) #1 {
define amdgpu_kernel void @s_test_canonicalize_undef_v2bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: s_test_canonicalize_undef_v2bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -928,6 +974,7 @@ define <2 x bfloat> @v_test_canonicalize_k_reg_v2bf16(bfloat %val) #1 {
define amdgpu_kernel void @s_test_canonicalize_undef_v4bf16(ptr addrspace(1) %out) #1 {
; GFX1250-LABEL: s_test_canonicalize_undef_v4bf16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)

1
llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll
View File

@ -13,6 +13,7 @@
define amdgpu_kernel void @test_move_load_address_to_vgpr(ptr addrspace(1) nocapture %arg1, ptr nocapture %arg2) {
; GCN-LABEL: test_move_load_address_to_vgpr:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: s_wait_kmcnt 0x0

166
llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
View File

File diff suppressed because it is too large Load Diff

212
llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
View File

File diff suppressed because it is too large Load Diff

103
llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
View File

@ -7,6 +7,7 @@
define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr(ptr inreg %sbase, ptr %voffset.ptr, i8 %data) {
; GFX1250-LABEL: flat_store_saddr_i8_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3]
@ -22,6 +23,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr(ptr inreg %sbase, ptr %voff
define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_2047(ptr inreg %sbase, ptr %voffset.ptr, i8 %data) {
; GFX1250-LABEL: flat_store_saddr_i8_zext_vgpr_offset_2047:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] offset:2047
@ -38,6 +40,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_2047(ptr inreg %sbas
define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_neg2048(ptr inreg %sbase, ptr %voffset.ptr, i8 %data) {
; GFX1250-LABEL: flat_store_saddr_i8_zext_vgpr_offset_neg2048:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] offset:-2048
@ -60,6 +63,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_neg2048(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_uniform_ptr_in_vgprs:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-SDAG-NEXT: ds_load_b64 v[2:3], v2
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -70,6 +74,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %d
;
; GFX1250-GISEL-LABEL: flat_store_saddr_uniform_ptr_in_vgprs:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-GISEL-NEXT: ds_load_b64 v[2:3], v2
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -89,6 +94,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %d
define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset, i8 %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-SDAG-NEXT: ds_load_b64 v[2:3], v2
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -99,6 +105,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voff
;
; GFX1250-GISEL-LABEL: flat_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-GISEL-NEXT: ds_load_b64 v[2:3], v2
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -122,6 +129,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voff
define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr(ptr inreg %sbase, i32 %voffset, i16 %data) {
; GFX1250-LABEL: flat_store_saddr_i16_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -133,6 +141,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i16 %data) {
; GFX1250-LABEL: flat_store_saddr_i16_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -145,6 +154,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr(ptr inreg %sbase, i32 %voffset, half %data) {
; GFX1250-LABEL: flat_store_saddr_f16_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -156,6 +166,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, half %data) {
; GFX1250-LABEL: flat_store_saddr_f16_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -168,6 +179,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %voffset, i32 %data) {
; GFX1250-LABEL: flat_store_saddr_i32_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -179,6 +191,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i32 %data) {
; GFX1250-LABEL: flat_store_saddr_i32_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -191,6 +204,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr(ptr inreg %sbase, i32 %voffset, float %data) {
; GFX1250-LABEL: flat_store_saddr_f32_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -202,6 +216,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, float %data) {
; GFX1250-LABEL: flat_store_saddr_f32_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -214,6 +229,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr(ptr inreg %sbase, i32 %voffset, ptr addrspace(3) %data) {
; GFX1250-LABEL: flat_store_saddr_p3_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -225,6 +241,7 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr(ptr inreg %sbase, i32 %voff
define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, ptr addrspace(3) %data) {
; GFX1250-LABEL: flat_store_saddr_p3_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -237,12 +254,14 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr_offset_neg128(ptr inreg %sb
define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i32 %voffset, i64 %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_i64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_i64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -255,12 +274,14 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i64 %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_i64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_i64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -274,12 +295,14 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr(ptr inreg %sbase, i32 %voffset, double %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_f64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_f64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -292,12 +315,14 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, double %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_f64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_f64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -311,12 +336,14 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x i32> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2i32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -329,12 +356,14 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x i32> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2i32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -348,12 +377,14 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x float> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2f32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -366,12 +397,14 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x float> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2f32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -385,12 +418,14 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr(ptr inreg %sbase, i32 %voffset, <4 x i16> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4i16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -403,12 +438,14 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <4 x i16> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4i16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -422,12 +459,14 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr(ptr inreg %sbase, i32 %voffset, <4 x half> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4f16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -440,12 +479,14 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <4 x half> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4f16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -459,12 +500,14 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr(ptr inreg %sbase, i32 %voffset, ptr %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_p1_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_p1_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
@ -477,12 +520,14 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr(ptr inreg %sbase, i32 %voff
define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, ptr %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_p1_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_p1_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
@ -496,6 +541,7 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr_offset_neg128(ptr inreg %sb
define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr(ptr inreg %sbase, i32 %voffset, <3 x i32> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v3i32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
@ -503,6 +549,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3i32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
@ -516,6 +563,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <3 x i32> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v3i32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
@ -523,6 +571,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3i32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
@ -537,6 +586,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr(ptr inreg %sbase, i32 %voffset, <3 x float> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v3f32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
@ -544,6 +594,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3f32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
@ -557,6 +608,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <3 x float> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v3f32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
@ -564,6 +616,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3f32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
@ -578,6 +631,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr(ptr inreg %sbase, i32 %voffset, <6 x i16> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v6i16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
@ -585,6 +639,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6i16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
@ -598,6 +653,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <6 x i16> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v6i16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
@ -605,6 +661,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6i16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
@ -619,6 +676,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr(ptr inreg %sbase, i32 %voffset, <6 x half> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v6f16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
@ -626,6 +684,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6f16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
@ -639,6 +698,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <6 x half> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v6f16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
@ -646,6 +706,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6f16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
@ -660,6 +721,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr(ptr inreg %sbase, i32 %voffset, <4 x i32> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4i32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -667,6 +729,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -680,6 +743,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <4 x i32> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4i32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -687,6 +751,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -701,6 +766,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr(ptr inreg %sbase, i32 %voffset, <4 x float> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4f32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -708,6 +774,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -721,6 +788,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <4 x float> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4f32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -728,6 +796,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -742,6 +811,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x i64> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2i64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -749,6 +819,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -762,6 +833,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x i64> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2i64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -769,6 +841,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -783,6 +856,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x double> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2f64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -790,6 +864,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -803,6 +878,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x double> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2f64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -810,6 +886,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -824,6 +901,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr(ptr inreg %sbase, i32 %voffset, <8 x i16> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v8i16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -831,6 +909,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8i16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -844,6 +923,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <8 x i16> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v8i16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -851,6 +931,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8i16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -865,6 +946,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr(ptr inreg %sbase, i32 %voffset, <8 x half> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v8f16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -872,6 +954,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr(ptr inreg %sbase, i32 %v
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8f16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -885,6 +968,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr(ptr inreg %sbase, i32 %v
define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <8 x half> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v8f16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -892,6 +976,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr inreg
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8f16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -906,6 +991,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr inreg
define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x ptr> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2p1_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -913,6 +999,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr(ptr inreg %sbase, i32 %vo
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2p1_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -926,6 +1013,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr(ptr inreg %sbase, i32 %vo
define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x ptr> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v2p1_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -933,6 +1021,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr inreg %
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2p1_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -947,6 +1036,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr inreg %
define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr(ptr inreg %sbase, i32 %voffset, <4 x ptr addrspace(3)> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4p3_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
@ -954,6 +1044,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr(ptr inreg %sbase, i32 %vo
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4p3_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
@ -967,6 +1058,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr(ptr inreg %sbase, i32 %vo
define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <4 x ptr addrspace(3)> %data) {
; GFX1250-SDAG-LABEL: flat_store_saddr_v4p3_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
@ -974,6 +1066,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr inreg %
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4p3_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
@ -992,6 +1085,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr inreg %
define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %voffset, i32 %data) {
; GFX1250-LABEL: atomic_flat_store_saddr_i32_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS
@ -1005,6 +1099,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i
define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i32 %data) {
; GFX1250-LABEL: atomic_flat_store_saddr_i32_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SYS
@ -1019,6 +1114,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr i
define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i32 %voffset, i64 %data) {
; GFX1250-SDAG-LABEL: atomic_flat_store_saddr_i64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0
@ -1027,6 +1123,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i
;
; GFX1250-GISEL-LABEL: atomic_flat_store_saddr_i64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0
@ -1041,6 +1138,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i
define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i64 %data) {
; GFX1250-SDAG-LABEL: atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0
@ -1049,6 +1147,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr i
;
; GFX1250-GISEL-LABEL: atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0
@ -1068,6 +1167,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr i
define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_d16_hi_b16 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -1080,6 +1180,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr(ptr inreg %sbase, i3
define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_d16_hi_b16 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -1093,6 +1194,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr in
define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_trunci8_zext_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_d16_hi_b8 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
@ -1106,6 +1208,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_store_d16_hi_b8 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64

6
llvm/test/CodeGen/AMDGPU/fmax3.ll
View File

@ -162,6 +162,7 @@ define amdgpu_kernel void @test_fmax3_olt_0_f32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: test_fmax3_olt_0_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_mov_b32 s2, -1
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000
@ -352,6 +353,7 @@ define amdgpu_kernel void @test_fmax3_olt_1_f32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: test_fmax3_olt_1_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_mov_b32 s2, -1
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000
@ -609,6 +611,7 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-TRUE16-LABEL: test_fmax3_olt_0_f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@ -639,6 +642,7 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-FAKE16-LABEL: test_fmax3_olt_0_f16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
@ -897,6 +901,7 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-TRUE16-LABEL: test_fmax3_olt_1_f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@ -927,6 +932,7 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-FAKE16-LABEL: test_fmax3_olt_1_f16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-FAKE16-NEXT: s_mov_b32 s3, 0x31016000

8
llvm/test/CodeGen/AMDGPU/fmin3.ll
View File

@ -162,6 +162,7 @@ define amdgpu_kernel void @test_fmin3_olt_0_f32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: test_fmin3_olt_0_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_mov_b32 s2, -1
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000
@ -352,6 +353,7 @@ define amdgpu_kernel void @test_fmin3_olt_1_f32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: test_fmin3_olt_1_f32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_mov_b32 s2, -1
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000
@ -609,6 +611,7 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-TRUE16-LABEL: test_fmin3_olt_0_f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@ -639,6 +642,7 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-FAKE16-LABEL: test_fmin3_olt_0_f16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
@ -897,6 +901,7 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-TRUE16-LABEL: test_fmin3_olt_1_f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@ -927,6 +932,7 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-FAKE16-LABEL: test_fmin3_olt_1_f16:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
@ -1217,6 +1223,7 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: test_fmin3_olt_0_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_mov_b32 s2, -1
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000
@ -1426,6 +1433,7 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: test_fmin3_olt_1_f64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
; GFX1250-NEXT: s_mov_b32 s2, -1
; GFX1250-NEXT: s_mov_b32 s3, 0x31016000

4
llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
View File

@ -34,6 +34,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat(ptr %ptr) {
;
; GFX1250-LABEL: flat_atomic_fadd_f32_noret_pat:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 4.0
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
@ -75,6 +76,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat_ieee(ptr %ptr) #0 {
;
; GFX1250-LABEL: flat_atomic_fadd_f32_noret_pat_ieee:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 4.0
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
@ -153,6 +155,7 @@ define amdgpu_kernel void @local_atomic_fadd_v2f16_noret(ptr addrspace(3) %ptr,
;
; GFX1250-LABEL: local_atomic_fadd_v2f16_noret:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@ -220,6 +223,7 @@ define amdgpu_kernel void @local_atomic_fadd_v2bf16_noret(ptr addrspace(3) %ptr,
;
; GFX1250-LABEL: local_atomic_fadd_v2bf16_noret:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1

49
llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
View File

@ -42,6 +42,7 @@ define amdgpu_kernel void @raw_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -72,6 +73,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -115,6 +117,7 @@ define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsr
;
; GFX1250-LABEL: raw_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -161,6 +164,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8)
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -191,6 +195,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -234,6 +239,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrsp
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -280,6 +286,7 @@ define amdgpu_kernel void @struct_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -310,6 +317,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -353,6 +361,7 @@ define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %
;
; GFX1250-LABEL: struct_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -398,6 +407,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_add_noret_f64(ptr addrspace(
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_add_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -428,6 +438,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_add_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -471,6 +482,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr add
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_add_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -516,6 +528,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -546,6 +559,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -589,6 +603,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %rsr
;
; GFX1250-LABEL: raw_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -635,6 +650,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8)
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -665,6 +681,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -708,6 +725,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrsp
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -754,6 +772,7 @@ define amdgpu_kernel void @struct_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -784,6 +803,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -827,6 +847,7 @@ define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %
;
; GFX1250-LABEL: struct_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -872,6 +893,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_min_noret_f64(ptr addrspace(
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_min_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -902,6 +924,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_min_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -945,6 +968,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr add
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_min_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -990,6 +1014,7 @@ define amdgpu_kernel void @raw_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1020,6 +1045,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
;
; GFX1250-LABEL: raw_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1063,6 +1089,7 @@ define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %rsr
;
; GFX1250-LABEL: raw_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1109,6 +1136,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8)
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1139,6 +1167,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1182,6 +1211,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrsp
;
; GFX1250-LABEL: raw_ptr_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1228,6 +1258,7 @@ define amdgpu_kernel void @struct_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1258,6 +1289,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
;
; GFX1250-LABEL: struct_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1301,6 +1333,7 @@ define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %
;
; GFX1250-LABEL: struct_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1346,6 +1379,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_max_noret_f64(ptr addrspace(
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_max_noret_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1376,6 +1410,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_max_rtn_f64:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
@ -1419,6 +1454,7 @@ define amdgpu_kernel void @struct_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr add
;
; GFX1250-LABEL: struct_ptr_buffer_atomic_max_rtn_f64_off4_slc:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x34
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -1468,6 +1504,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat(ptr addrspace(1) %pt
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1510,6 +1547,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent(ptr addrspace(
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_agent:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1554,6 +1592,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_system(ptr addrspace
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_system:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1596,6 +1635,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_flush(ptr addrspace(
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_flush:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1767,6 +1807,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent_safe(ptr addrs
;
; GFX1250-LABEL: global_atomic_fadd_f64_noret_pat_agent_safe:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1811,6 +1852,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(ptr %ptr) #1 {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1853,6 +1895,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent(ptr %ptr) #1 {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat_agent:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -1897,6 +1940,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(ptr %ptr) #1 {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat_system:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -2070,6 +2114,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent_safe(ptr %ptr) {
;
; GFX1250-LABEL: flat_atomic_fadd_f64_noret_pat_agent_safe:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -2110,6 +2155,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret(ptr addrspace(3) %ptr, do
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
@ -2181,6 +2227,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat(ptr addrspace(3) %ptr
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret_pat:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -2217,6 +2264,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat_flush(ptr addrspace(3
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret_pat_flush:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -2253,6 +2301,7 @@ define amdgpu_kernel void @local_atomic_fadd_f64_noret_pat_flush_safe(ptr addrsp
;
; GFX1250-LABEL: local_atomic_fadd_f64_noret_pat_flush_safe:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4.0
; GFX1250-NEXT: s_wait_kmcnt 0x0

108
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
View File

@ -199,6 +199,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -211,12 +212,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16(
; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX1250-SDAG-TRUE16-NEXT: s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -229,18 +232,21 @@ define amdgpu_kernel void @fptrunc_f32_to_f16(
; GFX1250-SDAG-FAKE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX1250-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@ -250,12 +256,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@ -454,6 +462,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r,
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -466,12 +475,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r,
; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX1250-SDAG-TRUE16-NEXT: s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -484,18 +495,21 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r,
; GFX1250-SDAG-FAKE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX1250-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@ -505,12 +519,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r,
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_afn:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@ -1216,6 +1232,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -1283,6 +1300,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -1350,6 +1368,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -1405,6 +1424,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -1665,6 +1685,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -1678,6 +1699,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -1685,6 +1707,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -1698,6 +1721,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -1705,6 +1729,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -1712,6 +1737,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -1719,6 +1745,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -1726,6 +1753,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -1950,6 +1978,7 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -1968,6 +1997,7 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -1986,6 +2016,7 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -2000,6 +2031,7 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -3235,6 +3267,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -3351,6 +3384,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -3467,6 +3501,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
@ -3566,6 +3601,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
@ -3910,6 +3946,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -3931,6 +3968,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -3952,6 +3990,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
@ -3961,6 +4000,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
@ -3971,6 +4011,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
@ -3980,6 +4021,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
@ -4179,6 +4221,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4192,6 +4235,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -4199,6 +4243,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
;
; GFX1250-SDAG-FAKE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4212,6 +4257,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -4219,6 +4265,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
;
; GFX1250-GISEL-TRUE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -4226,8 +4273,9 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_xor_b32 s2, s2, 0x80000000
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -4235,6 +4283,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fneg_fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -4242,8 +4291,9 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_xor_b32 s2, s2, 0x80000000
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -4441,6 +4491,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4454,6 +4505,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -4461,6 +4513,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
;
; GFX1250-SDAG-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4474,6 +4527,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -4481,6 +4535,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
;
; GFX1250-GISEL-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -4488,8 +4543,9 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_bitset0_b32 s2, 31
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -4497,6 +4553,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -4504,8 +4561,9 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_bitset0_b32 s2, 31
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -4703,6 +4761,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
;
; GFX1250-SDAG-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4716,6 +4775,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_or_b32_e32 v0, 0x80000000, v0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -4723,6 +4783,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
;
; GFX1250-SDAG-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4736,6 +4797,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, 0x80000000, v0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
@ -4743,6 +4805,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
;
; GFX1250-GISEL-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -4750,8 +4813,9 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_bitset1_b32 s2, 31
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -4759,6 +4823,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
;
; GFX1250-GISEL-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -4766,8 +4831,9 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_bitset1_b32 s2, 31
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@ -4973,6 +5039,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -4985,6 +5052,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@ -4993,6 +5061,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -5005,6 +5074,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX1250-SDAG-FAKE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@ -5013,12 +5083,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
@ -5029,12 +5101,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
@ -5243,6 +5317,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -5256,6 +5331,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@ -5264,6 +5340,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -5277,6 +5354,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@ -5285,6 +5363,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -5292,10 +5371,10 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_bitset0_b32 s2, 31
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null
@ -5303,6 +5382,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -5310,10 +5390,10 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_bitset0_b32 s2, 31
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], null
@ -5529,6 +5609,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
;
; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -5541,6 +5622,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
@ -5549,6 +5631,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
;
; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -5561,6 +5644,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX1250-SDAG-FAKE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX1250-SDAG-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
@ -5569,12 +5653,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
;
; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
@ -5585,12 +5671,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
;
; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2

13
llvm/test/CodeGen/AMDGPU/global-address.ll
View File

@ -27,8 +27,10 @@ define amdgpu_kernel void @caller_internal() {
;
; GFX1250-PAL-LABEL: caller_internal:
; GFX1250-PAL: ; %bb.0:
; GFX1250-PAL-NEXT: s_mov_b64 s[0:1], internal_func@abs64
; GFX1250-PAL-NEXT: s_mov_b32 s32, 0
; GFX1250-PAL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-PAL-NEXT: s_mov_b64 s[0:1], internal_func@abs64
; GFX1250-PAL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-PAL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
; GFX1250-PAL-NEXT: s_endpgm
;
@ -45,9 +47,10 @@ define amdgpu_kernel void @caller_internal() {
;
; GFX1250-HSA-LABEL: caller_internal:
; GFX1250-HSA: ; %bb.0:
; GFX1250-HSA-NEXT: s_mov_b32 s32, 0
; GFX1250-HSA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-HSA-NEXT: s_get_pc_i64 s[0:1]
; GFX1250-HSA-NEXT: s_add_nc_u64 s[0:1], s[0:1], internal_func@gotpcrel+4
; GFX1250-HSA-NEXT: s_mov_b32 s32, 0
; GFX1250-HSA-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-HSA-NEXT: s_wait_kmcnt 0x0
; GFX1250-HSA-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
@ -91,13 +94,14 @@ define amdgpu_kernel void @caller_exterinal() {
;
; GFX1250-PAL-LABEL: caller_exterinal:
; GFX1250-PAL: ; %bb.0:
; GFX1250-PAL-NEXT: s_mov_b32 s32, 0
; GFX1250-PAL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-PAL-NEXT: v_mov_b32_e32 v31, v0
; GFX1250-PAL-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX1250-PAL-NEXT: s_mov_b64 s[8:9], s[4:5]
; GFX1250-PAL-NEXT: s_mov_b64 s[12:13], external_func@abs64
; GFX1250-PAL-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX1250-PAL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1250-PAL-NEXT: s_mov_b32 s32, 0
; GFX1250-PAL-NEXT: s_swap_pc_i64 s[30:31], s[12:13]
; GFX1250-PAL-NEXT: s_endpgm
;
@ -120,6 +124,8 @@ define amdgpu_kernel void @caller_exterinal() {
;
; GFX1250-HSA-LABEL: caller_exterinal:
; GFX1250-HSA: ; %bb.0:
; GFX1250-HSA-NEXT: s_mov_b32 s32, 0
; GFX1250-HSA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-HSA-NEXT: v_mov_b32_e32 v31, v0
; GFX1250-HSA-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX1250-HSA-NEXT: s_mov_b64 s[8:9], s[4:5]
@ -127,7 +133,6 @@ define amdgpu_kernel void @caller_exterinal() {
; GFX1250-HSA-NEXT: s_add_nc_u64 s[12:13], s[12:13], external_func@rel64+4
; GFX1250-HSA-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX1250-HSA-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1250-HSA-NEXT: s_mov_b32 s32, 0
; GFX1250-HSA-NEXT: s_swap_pc_i64 s[30:31], s[12:13]
; GFX1250-HSA-NEXT: s_endpgm
call void @external_func()

2
llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
View File

@ -404,6 +404,7 @@ define i64 @test_v16i64_load_store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
define amdgpu_kernel void @test_v7i16_load_store_kernel(ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr2, ptr addrspace(1) %out) {
; GCN-SDAG-LABEL: test_v7i16_load_store_kernel:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GCN-SDAG-NEXT: v_and_b32_e32 v8, 0x3ff, v0
; GCN-SDAG-NEXT: s_wait_xcnt 0x0
@ -431,6 +432,7 @@ define amdgpu_kernel void @test_v7i16_load_store_kernel(ptr addrspace(1) %ptr1,
;
; GCN-GISEL-LABEL: test_v7i16_load_store_kernel:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GCN-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
; GCN-GISEL-NEXT: s_wait_xcnt 0x0

16
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
View File

@ -65,6 +65,7 @@ define amdgpu_kernel void @s_insertelement_v2bf16_0(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: s_insertelement_v2bf16_0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -139,6 +140,7 @@ define amdgpu_kernel void @s_insertelement_v2bf16_1(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: s_insertelement_v2bf16_1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -222,6 +224,7 @@ define amdgpu_kernel void @v_insertelement_v2bf16_0(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v2bf16_0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -308,6 +311,7 @@ define amdgpu_kernel void @v_insertelement_v2bf16_0_inlineimm(ptr addrspace(1) %
;
; GFX1250-LABEL: v_insertelement_v2bf16_0_inlineimm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -394,6 +398,7 @@ define amdgpu_kernel void @v_insertelement_v2bf16_1(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v2bf16_1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -480,6 +485,7 @@ define amdgpu_kernel void @v_insertelement_v2bf16_1_inlineimm(ptr addrspace(1) %
;
; GFX1250-LABEL: v_insertelement_v2bf16_1_inlineimm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -591,6 +597,7 @@ define amdgpu_kernel void @v_insertelement_v2bf16_dynamic_vgpr(ptr addrspace(1)
;
; GFX1250-LABEL: v_insertelement_v2bf16_dynamic_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x10
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
@ -693,6 +700,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_0(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v4bf16_0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -787,6 +795,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_1(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v4bf16_1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -883,6 +892,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_2(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v4bf16_2:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -977,6 +987,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_3(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v4bf16_3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -1094,6 +1105,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_dynamic_sgpr(ptr addrspace(1)
;
; GFX1250-LABEL: v_insertelement_v4bf16_dynamic_sgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -1194,6 +1206,7 @@ define amdgpu_kernel void @v_insertelement_v8bf16_3(ptr addrspace(1) %out, ptr a
;
; GFX1250-LABEL: v_insertelement_v8bf16_3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -1423,6 +1436,7 @@ define amdgpu_kernel void @v_insertelement_v8bf16_dynamic(ptr addrspace(1) %out,
;
; GFX1250-LABEL: v_insertelement_v8bf16_dynamic:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -1565,6 +1579,7 @@ define amdgpu_kernel void @v_insertelement_v16bf16_3(ptr addrspace(1) %out, ptr
;
; GFX1250-LABEL: v_insertelement_v16bf16_3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0
@ -1958,6 +1973,7 @@ define amdgpu_kernel void @v_insertelement_v16bf16_dynamic(ptr addrspace(1) %out
;
; GFX1250-LABEL: v_insertelement_v16bf16_dynamic:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_xcnt 0x0

24
llvm/test/CodeGen/AMDGPU/literal64.ll
View File

@ -5,6 +5,7 @@
define amdgpu_ps i64 @s_add_u64(i64 inreg %a) {
; GCN-LABEL: s_add_u64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0xf12345678
; GCN-NEXT: ; return to shader part epilog
%result = add i64 %a, 64729929336
@ -14,6 +15,7 @@ define amdgpu_ps i64 @s_add_u64(i64 inreg %a) {
define amdgpu_ps void @v_add_u64(i64 %a, ptr addrspace(1) %out) {
; GCN-LABEL: v_add_u64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_nc_u64_e32 v[0:1], 0xf12345678, v[0:1]
; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off
; GCN-NEXT: s_endpgm
@ -25,6 +27,7 @@ define amdgpu_ps void @v_add_u64(i64 %a, ptr addrspace(1) %out) {
define amdgpu_ps i64 @s_add_neg_u64(i64 inreg %a) {
; GCN-LABEL: s_add_neg_u64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0xfffffff0edcba988
; GCN-NEXT: ; return to shader part epilog
%result = sub i64 %a, 64729929336
@ -34,6 +37,7 @@ define amdgpu_ps i64 @s_add_neg_u64(i64 inreg %a) {
define amdgpu_ps void @v_add_neg_u64(i64 %a, ptr addrspace(1) %out) {
; GCN-LABEL: v_add_neg_u64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_add_nc_u64_e32 v[0:1], 0xfffffff0edcba988, v[0:1]
; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off
; GCN-NEXT: s_endpgm
@ -45,6 +49,7 @@ define amdgpu_ps void @v_add_neg_u64(i64 %a, ptr addrspace(1) %out) {
define amdgpu_ps i64 @s_sub_u64(i64 inreg %a) {
; GCN-LABEL: s_sub_u64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_sub_nc_u64 s[0:1], 0xf12345678, s[0:1]
; GCN-NEXT: ; return to shader part epilog
%result = sub i64 64729929336, %a
@ -54,6 +59,7 @@ define amdgpu_ps i64 @s_sub_u64(i64 inreg %a) {
define amdgpu_ps void @v_sub_u64(i64 %a, ptr addrspace(1) %out) {
; GCN-LABEL: v_sub_u64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_sub_nc_u64_e32 v[0:1], 0xf12345678, v[0:1]
; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off
; GCN-NEXT: s_endpgm
@ -140,6 +146,7 @@ define double @rsq_f64() {
define amdgpu_ps i64 @s_and_b64(i64 inreg %a) {
; GCN-LABEL: s_and_b64:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_and_b64 s[0:1], s[0:1], 0xf12345678
; GCN-NEXT: ; return to shader part epilog
%result = and i64 %a, 64729929336
@ -151,6 +158,7 @@ define amdgpu_ps i64 @s_and_b64(i64 inreg %a) {
define amdgpu_ps void @v_and_b64(i64 %a, ptr addrspace(1) %out) {
; GCN-SDAG-LABEL: v_and_b64:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-SDAG-NEXT: v_and_b32_e32 v1, 15, v1
; GCN-SDAG-NEXT: v_and_b32_e32 v0, 0x12345678, v0
; GCN-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off
@ -158,6 +166,7 @@ define amdgpu_ps void @v_and_b64(i64 %a, ptr addrspace(1) %out) {
;
; GCN-GISEL-LABEL: v_and_b64:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-GISEL-NEXT: v_and_b32_e32 v0, 0x12345678, v0
; GCN-GISEL-NEXT: v_and_b32_e32 v1, 15, v1
; GCN-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off
@ -170,6 +179,8 @@ define amdgpu_ps void @v_and_b64(i64 %a, ptr addrspace(1) %out) {
define amdgpu_ps <2 x float> @v_add_f64_200.1(double %a) {
; GCN-LABEL: v_add_f64_200.1:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GCN-NEXT: v_add_f64_e32 v[0:1], 0x4069033333333333, v[0:1]
; GCN-NEXT: ; return to shader part epilog
%add = fadd double %a, 200.1
@ -182,6 +193,8 @@ define amdgpu_ps <2 x float> @v_add_f64_200.1(double %a) {
define amdgpu_ps <2 x float> @v_add_f64_200.0(double %a) {
; GCN-LABEL: v_add_f64_200.0:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GCN-NEXT: v_add_f64_e32 v[0:1], 0x40690000, v[0:1]
; GCN-NEXT: ; return to shader part epilog
%add = fadd double %a, 200.0
@ -194,6 +207,7 @@ define amdgpu_ps <2 x float> @v_add_f64_200.0(double %a) {
define amdgpu_ps <2 x float> @v_lshl_add_u64(i64 %a) {
; GCN-SDAG-LABEL: v_lshl_add_u64:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-SDAG-NEXT: s_mov_b64 s[0:1], 0xf12345678
; GCN-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 1, s[0:1]
@ -201,6 +215,7 @@ define amdgpu_ps <2 x float> @v_lshl_add_u64(i64 %a) {
;
; GCN-GISEL-LABEL: v_lshl_add_u64:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-GISEL-NEXT: v_mov_b64_e32 v[2:3], 0xf12345678
; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 1, v[2:3]
@ -216,6 +231,7 @@ define amdgpu_ps <2 x float> @v_lshl_add_u64(i64 %a) {
define amdgpu_ps <2 x float> @v_fma_f64(double %a, double %b) {
; GCN-SDAG-LABEL: v_fma_f64:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-SDAG-NEXT: v_fmaak_f64 v[4:5], v[0:1], v[2:3], 0x4063233333333333
; GCN-SDAG-NEXT: v_mov_b64_e32 v[2:3], 0x4069033333333333
; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@ -227,6 +243,7 @@ define amdgpu_ps <2 x float> @v_fma_f64(double %a, double %b) {
;
; GCN-GISEL-LABEL: v_fma_f64:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-GISEL-NEXT: v_mov_b64_e32 v[4:5], 0x4063233333333333
; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GCN-GISEL-NEXT: v_fmac_f64_e32 v[4:5], v[0:1], v[2:3]
@ -246,15 +263,18 @@ define amdgpu_ps <2 x float> @v_fma_f64(double %a, double %b) {
define amdgpu_ps <2 x float> @v_add_neg_f64(double %a) {
; GCN-SDAG-LABEL: v_add_neg_f64:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-SDAG-NEXT: s_mov_b64 s[0:1], 0x4069033333333333
; GCN-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GCN-SDAG-NEXT: v_add_f64_e64 v[0:1], -v[0:1], s[0:1]
; GCN-SDAG-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: v_add_neg_f64:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GCN-GISEL-NEXT: v_mov_b64_e32 v[2:3], 0x4069033333333333
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-GISEL-NEXT: v_add_f64_e64 v[0:1], -v[0:1], v[2:3]
; GCN-GISEL-NEXT: ; return to shader part epilog
@ -267,6 +287,7 @@ define amdgpu_ps <2 x float> @v_add_neg_f64(double %a) {
define amdgpu_ps <2 x float> @v_cndmask(double %a) {
; GCN-SDAG-LABEL: v_cndmask:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-SDAG-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x40632000
; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x33333333, 0, vcc_lo
@ -276,6 +297,7 @@ define amdgpu_ps <2 x float> @v_cndmask(double %a) {
;
; GCN-GISEL-LABEL: v_cndmask:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-GISEL-NEXT: v_cmp_eq_f64_e32 vcc_lo, 0, v[0:1]
; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x40690333
; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, 0x33333333, 0, vcc_lo

55
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
View File

@ -10,20 +10,32 @@ declare i32 @llvm.amdgcn.bitop3.i32(i32, i32, i32, i32)
declare i16 @llvm.amdgcn.bitop3.i16(i16, i16, i16, i32)
define amdgpu_ps float @bitop3_b32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: bitop3_b32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: bitop3_b32_vvv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_vvv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 15)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps float @bitop3_b32_svv(i32 inreg %a, i32 %b, i32 %c) {
; GCN-LABEL: bitop3_b32_svv:
; GCN: ; %bb.0:
; GCN-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x10
; GCN-NEXT: ; return to shader part epilog
; GFX950-LABEL: bitop3_b32_svv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x10
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_svv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x10
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 16)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
@ -38,6 +50,7 @@ define amdgpu_ps float @bitop3_b32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
;
; GFX1250-LABEL: bitop3_b32_ssv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:0x11
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 17)
@ -55,6 +68,7 @@ define amdgpu_ps float @bitop3_b32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c)
;
; GFX1250-LABEL: bitop3_b32_sss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:0x12
@ -79,6 +93,7 @@ define amdgpu_ps float @bitop3_b32_vvi(i32 %a, i32 %b) {
;
; GFX1250-LABEL: bitop3_b32_vvi:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, 0x3e8 bitop3:0x13
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 1000, i32 19)
@ -103,6 +118,7 @@ define amdgpu_ps float @bitop3_b32_vii(i32 %a) {
;
; GFX1250-SDAG-LABEL: bitop3_b32_vii:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0x7d0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, s0, 0x3e8 bitop3:0x14
@ -110,6 +126,7 @@ define amdgpu_ps float @bitop3_b32_vii(i32 %a) {
;
; GFX1250-GISEL-LABEL: bitop3_b32_vii:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, 0x7d0, v1 bitop3:0x14
@ -140,6 +157,7 @@ define amdgpu_ps float @bitop3_b32_iii() {
;
; GFX1250-SDAG-LABEL: bitop3_b32_iii:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0xbb8
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
@ -148,6 +166,7 @@ define amdgpu_ps float @bitop3_b32_iii() {
;
; GFX1250-GISEL-LABEL: bitop3_b32_iii:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0x7d0
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -166,11 +185,13 @@ define amdgpu_ps half @bitop3_b16_vvv(i16 %a, i16 %b, i16 %c) {
;
; GFX1250-TRUE16-LABEL: bitop3_b16_vvv:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:0xf
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_vvv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 15)
@ -186,11 +207,13 @@ define amdgpu_ps half @bitop3_b16_svv(i16 inreg %a, i16 %b, i16 %c) {
;
; GFX1250-TRUE16-LABEL: bitop3_b16_svv:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, v0.l, v1.l bitop3:0x10
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_svv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 16)
@ -207,11 +230,13 @@ define amdgpu_ps half @bitop3_b16_ssv(i16 inreg %a, i16 inreg %b, i16 %c) {
;
; GFX1250-TRUE16-LABEL: bitop3_b16_ssv:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x11
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_ssv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x11
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 17)
@ -229,6 +254,7 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
;
; GFX1250-TRUE16-LABEL: bitop3_b16_sss:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
@ -236,6 +262,7 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
;
; GFX1250-FAKE16-LABEL: bitop3_b16_sss:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x12
@ -260,11 +287,13 @@ define amdgpu_ps half @bitop3_b16_vvi(i16 %a, i16 %b) {
;
; GFX1250-TRUE16-LABEL: bitop3_b16_vvi:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x13
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_vvi:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0x3e8 bitop3:0x13
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 1000, i32 19)
@ -289,6 +318,7 @@ define amdgpu_ps half @bitop3_b16_vii(i16 %a) {
;
; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_vii:
; GFX1250-SDG-TRUE16: ; %bb.0:
; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x7d0
; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x14
@ -296,6 +326,7 @@ define amdgpu_ps half @bitop3_b16_vii(i16 %a) {
;
; GFX1250-SDG-FAKE16-LABEL: bitop3_b16_vii:
; GFX1250-SDG-FAKE16: ; %bb.0:
; GFX1250-SDG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDG-FAKE16-NEXT: s_movk_i32 s0, 0x7d0
; GFX1250-SDG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDG-FAKE16-NEXT: v_bitop3_b16 v0, v0, s0, 0x3e8 bitop3:0x14
@ -303,6 +334,7 @@ define amdgpu_ps half @bitop3_b16_vii(i16 %a) {
;
; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_vii:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, 0x7d0, v0.h bitop3:0x14
@ -310,6 +342,7 @@ define amdgpu_ps half @bitop3_b16_vii(i16 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_vii:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, 0x7d0, v1 bitop3:0x14
@ -339,6 +372,7 @@ define amdgpu_ps half @bitop3_b16_iii() {
;
; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_iii:
; GFX1250-SDG-TRUE16: ; %bb.0:
; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7d0
; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0xbb8
; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -347,6 +381,7 @@ define amdgpu_ps half @bitop3_b16_iii() {
;
; GFX1250-SDG-FAKE16-LABEL: bitop3_b16_iii:
; GFX1250-SDG-FAKE16: ; %bb.0:
; GFX1250-SDG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDG-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX1250-SDG-FAKE16-NEXT: s_movk_i32 s0, 0xbb8
; GFX1250-SDG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
@ -355,6 +390,7 @@ define amdgpu_ps half @bitop3_b16_iii() {
;
; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_iii:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7d0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -363,6 +399,7 @@ define amdgpu_ps half @bitop3_b16_iii() {
;
; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_iii:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7d0
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -372,3 +409,5 @@ define amdgpu_ps half @bitop3_b16_iii() {
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}

12
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
View File

@ -11,6 +11,7 @@ declare i32 @llvm.amdgcn.cluster.id.z() #0
define amdgpu_kernel void @test_cluster_id_x(ptr addrspace(1) %out) {
; CHECK-UNKNOWN-LABEL: test_cluster_id_x:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
; CHECK-UNKNOWN-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -87,6 +88,7 @@ define amdgpu_kernel void @test_cluster_id_x(ptr addrspace(1) %out) {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; CHECK-MESA3D-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -95,6 +97,7 @@ define amdgpu_kernel void @test_cluster_id_x(ptr addrspace(1) %out) {
;
; CHECK-G-UNKNOWN-LABEL: test_cluster_id_x:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
; CHECK-G-UNKNOWN-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -171,6 +174,7 @@ define amdgpu_kernel void @test_cluster_id_x(ptr addrspace(1) %out) {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; CHECK-G-MESA3D-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -184,6 +188,7 @@ define amdgpu_kernel void @test_cluster_id_x(ptr addrspace(1) %out) {
define amdgpu_kernel void @test_cluster_id_y(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_cluster_id_y:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
; CHECK-UNKNOWN-NEXT: v_dual_mov_b32 v0, ttmp7 :: v_dual_mov_b32 v1, 0
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -260,6 +265,7 @@ define amdgpu_kernel void @test_cluster_id_y(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; CHECK-MESA3D-NEXT: v_dual_mov_b32 v0, ttmp7 :: v_dual_mov_b32 v1, 0
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -268,6 +274,7 @@ define amdgpu_kernel void @test_cluster_id_y(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_cluster_id_y:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
; CHECK-G-UNKNOWN-NEXT: v_dual_mov_b32 v0, ttmp7 :: v_dual_mov_b32 v1, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -344,6 +351,7 @@ define amdgpu_kernel void @test_cluster_id_y(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; CHECK-G-MESA3D-NEXT: v_dual_mov_b32 v0, ttmp7 :: v_dual_mov_b32 v1, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -357,6 +365,7 @@ define amdgpu_kernel void @test_cluster_id_y(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_cluster_id_z(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_cluster_id_z:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
; CHECK-UNKNOWN-NEXT: s_wait_xcnt 0x0
; CHECK-UNKNOWN-NEXT: s_lshr_b32 s0, ttmp7, 16
@ -436,6 +445,7 @@ define amdgpu_kernel void @test_cluster_id_z(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; CHECK-MESA3D-NEXT: s_lshr_b32 s2, ttmp7, 16
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -446,6 +456,7 @@ define amdgpu_kernel void @test_cluster_id_z(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_cluster_id_z:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24
; CHECK-G-UNKNOWN-NEXT: s_wait_xcnt 0x0
; CHECK-G-UNKNOWN-NEXT: s_lshr_b32 s0, ttmp7, 16
@ -525,6 +536,7 @@ define amdgpu_kernel void @test_cluster_id_z(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; CHECK-G-MESA3D-NEXT: s_lshr_b32 s2, ttmp7, 16
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)

23
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
View File

@ -10,6 +10,7 @@ declare void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gaddr
define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b8_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
@ -18,6 +19,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr(ptr addrspace(1) %gadd
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b8_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -34,6 +36,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr_imm_mask(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b8_vaddr_imm_mask:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: s_mov_b32 m0, 15
; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16
@ -41,6 +44,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr_imm_mask(ptr addrspace
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b8_vaddr_imm_mask:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -56,6 +60,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b8_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_async_to_lds_b8_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
@ -69,6 +74,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
@ -77,6 +83,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr(ptr addrspace(1) %gad
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -93,6 +100,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr_imm_mask(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_vaddr_imm_mask:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: s_mov_b32 m0, 15
; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16
@ -100,6 +108,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr_imm_mask(ptr addrspac
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_vaddr_imm_mask:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -115,6 +124,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr( ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_async_to_lds_b32_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
@ -128,6 +138,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
@ -136,6 +147,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr(ptr addrspace(1) %gad
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -152,6 +164,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr_imm_mask( ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_vaddr_imm_mask:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: s_movk_i32 m0, 0x7f
; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16
@ -159,6 +172,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr_imm_mask( ptr addrspa
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_vaddr_imm_mask:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -174,6 +188,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
@ -187,6 +202,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %mask) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b128_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
@ -195,6 +211,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr(ptr addrspace(1) %ga
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b128_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -211,6 +228,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr_imm_mask(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b128_vaddr_imm_mask:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: s_movk_i32 m0, 0x7f
; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16
@ -218,6 +236,7 @@ define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr_imm_mask(ptr addrspa
;
; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b128_vaddr_imm_mask:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -233,6 +252,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b128_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_async_to_lds_b128_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
@ -246,6 +266,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {
; GFX1250-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_endpgm
@ -259,6 +280,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {
; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_endpgm
@ -272,6 +294,7 @@ entry:
define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {
; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)

11
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
View File

@ -9,6 +9,7 @@ declare <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1), i32
define amdgpu_ps void @cluster_load_b32_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {
; GFX1250-LABEL: cluster_load_b32_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-NEXT: s_mov_b32 m0, s0
; GFX1250-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
@ -25,6 +26,7 @@ entry:
define amdgpu_ps void @cluster_load_b32_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: cluster_load_b32_vaddr_imm_mask:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, 7
; GFX1250-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -40,6 +42,7 @@ entry:
define amdgpu_ps void @cluster_load_b32_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_b32_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
@ -56,6 +59,7 @@ entry:
define amdgpu_ps void @cluster_load_monitor_b32_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask, i32 %idx) {
; GFX1250-LABEL: cluster_load_monitor_b32_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -72,6 +76,7 @@ entry:
define amdgpu_ps void @cluster_load_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {
; GFX1250-LABEL: cluster_load_b64_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-NEXT: s_mov_b32 m0, s0
; GFX1250-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT
@ -88,6 +93,7 @@ entry:
define amdgpu_ps void @cluster_load_b64_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: cluster_load_b64_vaddr_imm_mask:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, 0x10007
; GFX1250-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -103,6 +109,7 @@ entry:
define amdgpu_ps void @cluster_load_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
@ -119,6 +126,7 @@ entry:
define amdgpu_ps void @cluster_load_monitor_b64_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask, i32 %idx) {
; GFX1250-LABEL: cluster_load_monitor_b64_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -135,6 +143,7 @@ entry:
define amdgpu_ps void @cluster_load_b128_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {
; GFX1250-LABEL: cluster_load_b128_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-NEXT: s_mov_b32 m0, s0
; GFX1250-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT
@ -151,6 +160,7 @@ entry:
define amdgpu_ps void @cluster_load_b128_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: cluster_load_b128_vaddr_imm_mask:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 m0, 15
; GFX1250-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -166,6 +176,7 @@ entry:
define amdgpu_ps void @cluster_load_b128_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {
; GFX1250-LABEL: cluster_load_b128_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_mov_b32 m0, s2
; GFX1250-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS

28
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
View File

@ -11,6 +11,7 @@ declare i32 @llvm.amdgcn.cluster.workgroup.id.z() #0
define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_id_x:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_and_b32 s2, ttmp6, 15
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -89,6 +90,7 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_and_b32 s2, ttmp6, 15
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -99,6 +101,7 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_id_x:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_and_b32 s2, ttmp6, 15
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -177,6 +180,7 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_and_b32 s2, ttmp6, 15
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -192,6 +196,7 @@ define amdgpu_kernel void @test_workgroup_id_x(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_workgroup_id_x_optimized(ptr addrspace(1) %out) "amdgpu-cluster-dims"="1,2,2" {
; CHECK-UNKNOWN-LABEL: test_workgroup_id_x_optimized:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: v_mov_b32_e32 v0, 0
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -268,6 +273,7 @@ define amdgpu_kernel void @test_workgroup_id_x_optimized(ptr addrspace(1) %out)
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: v_mov_b32_e32 v0, 0
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -276,6 +282,7 @@ define amdgpu_kernel void @test_workgroup_id_x_optimized(ptr addrspace(1) %out)
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_id_x_optimized:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: v_mov_b32_e32 v0, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -352,6 +359,7 @@ define amdgpu_kernel void @test_workgroup_id_x_optimized(ptr addrspace(1) %out)
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: v_mov_b32_e32 v0, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -365,6 +373,7 @@ define amdgpu_kernel void @test_workgroup_id_x_optimized(ptr addrspace(1) %out)
define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_id_y:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40004
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -443,6 +452,7 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40004
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -453,6 +463,7 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_id_y:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40004
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -531,6 +542,7 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40004
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -546,6 +558,7 @@ define amdgpu_kernel void @test_workgroup_id_y(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_workgroup_id_y_optimized(ptr addrspace(1) %out) "amdgpu-cluster-dims"="2,1,2" {
; CHECK-UNKNOWN-LABEL: test_workgroup_id_y_optimized:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: v_mov_b32_e32 v0, 0
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -622,6 +635,7 @@ define amdgpu_kernel void @test_workgroup_id_y_optimized(ptr addrspace(1) %out)
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: v_mov_b32_e32 v0, 0
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -630,6 +644,7 @@ define amdgpu_kernel void @test_workgroup_id_y_optimized(ptr addrspace(1) %out)
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_id_y_optimized:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: v_mov_b32_e32 v0, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -706,6 +721,7 @@ define amdgpu_kernel void @test_workgroup_id_y_optimized(ptr addrspace(1) %out)
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: v_mov_b32_e32 v0, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -719,6 +735,7 @@ define amdgpu_kernel void @test_workgroup_id_y_optimized(ptr addrspace(1) %out)
define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_id_z:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40008
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -797,6 +814,7 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40008
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -807,6 +825,7 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_id_z:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40008
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -885,6 +904,7 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40008
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -900,6 +920,7 @@ define amdgpu_kernel void @test_workgroup_id_z(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_workgroup_flat_id(ptr addrspace(1) %out) {
; CHECK-UNKNOWN-LABEL: test_workgroup_flat_id:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 21, 4)
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -978,6 +999,7 @@ define amdgpu_kernel void @test_workgroup_flat_id(ptr addrspace(1) %out) {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 21, 4)
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -988,6 +1010,7 @@ define amdgpu_kernel void @test_workgroup_flat_id(ptr addrspace(1) %out) {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_flat_id:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 21, 4)
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -1066,6 +1089,7 @@ define amdgpu_kernel void @test_workgroup_flat_id(ptr addrspace(1) %out) {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 21, 4)
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -1081,6 +1105,7 @@ define amdgpu_kernel void @test_workgroup_flat_id(ptr addrspace(1) %out) {
define amdgpu_kernel void @test_workgroup_id_z_optimized(ptr addrspace(1) %out) "amdgpu-cluster-dims"="2,2,1" {
; CHECK-UNKNOWN-LABEL: test_workgroup_id_z_optimized:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: v_mov_b32_e32 v0, 0
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -1157,6 +1182,7 @@ define amdgpu_kernel void @test_workgroup_id_z_optimized(ptr addrspace(1) %out)
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: v_mov_b32_e32 v0, 0
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -1165,6 +1191,7 @@ define amdgpu_kernel void @test_workgroup_id_z_optimized(ptr addrspace(1) %out)
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_id_z_optimized:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: v_mov_b32_e32 v0, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -1241,6 +1268,7 @@ define amdgpu_kernel void @test_workgroup_id_z_optimized(ptr addrspace(1) %out)
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: v_mov_b32_e32 v0, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
View File

@ -9,6 +9,7 @@ declare i32 @llvm.amdgcn.cluster.workgroup.max.flat.id() #0
define amdgpu_kernel void @test_workgroup_max_flat_id(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_flat_id:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40018
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -87,6 +88,7 @@ define amdgpu_kernel void @test_workgroup_max_flat_id(ptr addrspace(1) %out) #1
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40018
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -97,6 +99,7 @@ define amdgpu_kernel void @test_workgroup_max_flat_id(ptr addrspace(1) %out) #1
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_flat_id:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40018
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -175,6 +178,7 @@ define amdgpu_kernel void @test_workgroup_max_flat_id(ptr addrspace(1) %out) #1
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40018
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)

24
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
View File

@ -11,6 +11,7 @@ declare i32 @llvm.amdgcn.cluster.workgroup.max.id.z() #0
define amdgpu_kernel void @test_workgroup_max_id_x(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_id_x:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x4000c
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -89,6 +90,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x4000c
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -99,6 +101,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_id_x:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x4000c
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -177,6 +180,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x4000c
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -192,6 +196,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_workgroup_max_id_x_optimized(ptr addrspace(1) %out) "amdgpu-cluster-dims"="5,6,7" {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_id_x_optimized:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 4
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -268,6 +273,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x_optimized(ptr addrspace(1) %o
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 4
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -276,6 +282,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x_optimized(ptr addrspace(1) %o
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_id_x_optimized:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -352,6 +359,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x_optimized(ptr addrspace(1) %o
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -365,6 +373,7 @@ define amdgpu_kernel void @test_workgroup_max_id_x_optimized(ptr addrspace(1) %o
define amdgpu_kernel void @test_workgroup_max_id_y(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_id_y:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40010
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -443,6 +452,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40010
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -453,6 +463,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_id_y:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40010
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -531,6 +542,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40010
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -546,6 +558,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_workgroup_max_id_y_optimized(ptr addrspace(1) %out) "amdgpu-cluster-dims"="5,6,7" {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_id_y_optimized:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 5
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -622,6 +635,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y_optimized(ptr addrspace(1) %o
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 5
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -630,6 +644,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y_optimized(ptr addrspace(1) %o
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_id_y_optimized:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: v_dual_mov_b32 v0, 5 :: v_dual_mov_b32 v1, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -706,6 +721,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y_optimized(ptr addrspace(1) %o
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: v_dual_mov_b32 v0, 5 :: v_dual_mov_b32 v1, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -719,6 +735,7 @@ define amdgpu_kernel void @test_workgroup_max_id_y_optimized(ptr addrspace(1) %o
define amdgpu_kernel void @test_workgroup_max_id_z(ptr addrspace(1) %out) #1 {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_id_z:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40014
; CHECK-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -797,6 +814,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z(ptr addrspace(1) %out) #1 {
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40014
; CHECK-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -807,6 +825,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z(ptr addrspace(1) %out) #1 {
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_id_z:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: s_bfe_u32 s2, ttmp6, 0x40014
; CHECK-G-UNKNOWN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -885,6 +904,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z(ptr addrspace(1) %out) #1 {
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: s_bfe_u32 s2, ttmp6, 0x40014
; CHECK-G-MESA3D-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@ -900,6 +920,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @test_workgroup_max_id_z_optimized(ptr addrspace(1) %out) "amdgpu-cluster-dims"="5,6,7" {
; CHECK-UNKNOWN-LABEL: test_workgroup_max_id_z_optimized:
; CHECK-UNKNOWN: ; %bb.0:
; CHECK-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-UNKNOWN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 6
; CHECK-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -976,6 +997,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z_optimized(ptr addrspace(1) %o
; CHECK-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-MESA3D-NEXT: ; %bb.0:
; CHECK-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-MESA3D-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 6
; CHECK-MESA3D-NEXT: s_wait_kmcnt 0x0
@ -984,6 +1006,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z_optimized(ptr addrspace(1) %o
;
; CHECK-G-UNKNOWN-LABEL: test_workgroup_max_id_z_optimized:
; CHECK-G-UNKNOWN: ; %bb.0:
; CHECK-G-UNKNOWN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-UNKNOWN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; CHECK-G-UNKNOWN-NEXT: v_dual_mov_b32 v0, 6 :: v_dual_mov_b32 v1, 0
; CHECK-G-UNKNOWN-NEXT: s_wait_kmcnt 0x0
@ -1060,6 +1083,7 @@ define amdgpu_kernel void @test_workgroup_max_id_z_optimized(ptr addrspace(1) %o
; CHECK-G-MESA3D-NEXT: runtime_loader_kernel_symbol = 0
; CHECK-G-MESA3D-NEXT: .end_amd_kernel_code_t
; CHECK-G-MESA3D-NEXT: ; %bb.0:
; CHECK-G-MESA3D-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; CHECK-G-MESA3D-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; CHECK-G-MESA3D-NEXT: v_dual_mov_b32 v0, 6 :: v_dual_mov_b32 v1, 0
; CHECK-G-MESA3D-NEXT: s_wait_kmcnt 0x0

54
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
View File

@ -12,6 +12,7 @@ declare <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16)
define amdgpu_ps float @test_cvt_f16_bf8_byte0(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte0:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, v0
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -19,6 +20,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte0(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte0:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -26,6 +28,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte0(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte0:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, v0
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -33,6 +36,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte0(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -45,6 +49,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte0(i32 %a) {
define amdgpu_ps float @test_cvt_f16_bf8_byte1(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte1:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:1
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -52,6 +57,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte1(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte1:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:1
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -59,6 +65,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte1(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte1:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:1
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -66,6 +73,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte1(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte1:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:1
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -78,6 +86,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte1(i32 %a) {
define amdgpu_ps float @test_cvt_f16_bf8_byte2(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte2:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:2
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -85,6 +94,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte2(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte2:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:2
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -92,6 +102,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte2(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte2:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:2
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -99,6 +110,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte2(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte2:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -111,6 +123,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte2(i32 %a) {
define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte3:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -118,6 +131,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte3:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -125,6 +139,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte3:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -132,6 +147,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte3:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -144,12 +160,14 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {
define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte3_hi:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.h, v0 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT: v_mov_b16_e32 v0.l, 0
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte3_hi:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, 0, 0x5040100
@ -157,6 +175,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte3_hi:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, 0
@ -164,6 +183,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte3_hi:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e64 v0, v0 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, 0
@ -178,6 +198,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
define amdgpu_ps float @test_cvt_f16_fp8_byte0(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte0:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, v0
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -185,6 +206,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte0(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte0:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -192,6 +214,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte0(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte0:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, v0
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -199,6 +222,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte0(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e32 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -211,6 +235,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte0(i32 %a) {
define amdgpu_ps float @test_cvt_f16_fp8_byte1(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte1:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:1
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -218,6 +243,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte1(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte1:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:1
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -225,6 +251,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte1(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte1:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:1
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -232,6 +259,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte1(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte1:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:1
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -244,6 +272,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte1(i32 %a) {
define amdgpu_ps float @test_cvt_f16_fp8_byte2(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte2:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:2
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -251,6 +280,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte2(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte2:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:2
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -258,6 +288,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte2(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte2:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:2
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -265,6 +296,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte2(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte2:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:2
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -277,6 +309,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte2(i32 %a) {
define amdgpu_ps float @test_cvt_f16_fp8_byte3(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte3:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -284,6 +317,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3(i32 %a) {
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte3:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -291,6 +325,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte3:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
@ -298,6 +333,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte3:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@ -310,12 +346,14 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3(i32 %a) {
define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte3_hi:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.h, v0 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT: v_mov_b16_e32 v0.l, 0
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte3_hi:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, 0, 0x5040100
@ -323,6 +361,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte3_hi:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, 0
@ -330,6 +369,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte3_hi:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e64 v0, v0 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, 0
@ -344,21 +384,25 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
define amdgpu_ps float @test_cvt_pk_f16_bf8_v(i16 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_bf8_v:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_bf8 v0, v0.l
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_bf8_v:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_bf8 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_bf8_v:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_bf8 v0, v0.l
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_bf8_v:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_bf8 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.bf8(i16 %a)
@ -369,6 +413,7 @@ define amdgpu_ps float @test_cvt_pk_f16_bf8_v(i16 %a) {
define amdgpu_ps float @test_cvt_pk_f16_bf8_s(i16 inreg %a) {
; GFX1250-LABEL: test_cvt_pk_f16_bf8_s:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_f16_bf8 v0, s0
; GFX1250-NEXT: ; return to shader part epilog
%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.bf8(i16 %a)
@ -379,21 +424,25 @@ define amdgpu_ps float @test_cvt_pk_f16_bf8_s(i16 inreg %a) {
define amdgpu_ps float @test_cvt_pk_f16_fp8_v(i16 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_fp8_v:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_fp8_v:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_fp8_v:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a)
@ -404,6 +453,7 @@ define amdgpu_ps float @test_cvt_pk_f16_fp8_v(i16 %a) {
define amdgpu_ps float @test_cvt_pk_f16_fp8_s(i16 inreg %a) {
; GFX1250-LABEL: test_cvt_pk_f16_fp8_s:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_pk_f16_fp8 v0, s0
; GFX1250-NEXT: ; return to shader part epilog
%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a)
@ -414,11 +464,13 @@ define amdgpu_ps float @test_cvt_pk_f16_fp8_s(i16 inreg %a) {
define amdgpu_ps float @test_cvt_pk_f16_fp8_v_hi(<2 x i16> %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_fp8_v_hi:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.h
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
@ -426,6 +478,7 @@ define amdgpu_ps float @test_cvt_pk_f16_fp8_v_hi(<2 x i16> %a) {
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_fp8_v_hi:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
@ -433,6 +486,7 @@ define amdgpu_ps float @test_cvt_pk_f16_fp8_v_hi(<2 x i16> %a) {
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0

9
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
View File

@ -10,6 +10,7 @@ define amdgpu_cs float @test_cvt_f32_bf8_byte0(i32 %a) {
;
; GFX1250-LABEL: test_cvt_f32_bf8_byte0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_bf8_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: ; return to shader part epilog
%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)
@ -25,6 +26,7 @@ define amdgpu_cs float @test_cvt_f32_bf8_byte1(i32 %a) {
;
; GFX1250-LABEL: test_cvt_f32_bf8_byte1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: ; return to shader part epilog
%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)
@ -40,6 +42,7 @@ define amdgpu_cs float @test_cvt_f32_bf8_byte2(i32 %a) {
;
; GFX1250-LABEL: test_cvt_f32_bf8_byte2:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: ; return to shader part epilog
%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)
@ -55,6 +58,7 @@ define amdgpu_cs float @test_cvt_f32_fp8_byte3(i32 %a) {
;
; GFX1250-LABEL: test_cvt_f32_fp8_byte3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_f32_fp8_e64_dpp v0, v0 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: ; return to shader part epilog
%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %a, i32 228, i32 15, i32 15, i1 1)
@ -71,6 +75,7 @@ define amdgpu_cs void @test_cvt_pk_bf8_f32_word0(i32 %a, float %y, i32 %old, ptr
;
; GFX1250-LABEL: test_cvt_pk_bf8_f32_word0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_cvt_pk_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: global_store_b32 v[4:5], v2, off
@ -93,6 +98,7 @@ define amdgpu_cs void @test_cvt_pk_fp8_f32_word1(i32 %a, float %y, i32 %old, ptr
;
; GFX1250-LABEL: test_cvt_pk_fp8_f32_word1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -115,6 +121,7 @@ define amdgpu_cs void @test_cvt_sr_bf8_f32_byte0(i32 %a, i32 %r, i32 %old, ptr a
;
; GFX1250-LABEL: test_cvt_sr_bf8_f32_byte0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_cvt_sr_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: global_store_b32 v[4:5], v2, off
@ -135,6 +142,7 @@ define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1(i32 %a, i32 %r, i32 %old, ptr a
;
; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: global_store_b32 v[4:5], v2, off
@ -155,6 +163,7 @@ define amdgpu_cs void @test_cvt_sr_fp8_f32_byte2(i32 %a, i32 %r, i32 %old, ptr a
;
; GFX1250-LABEL: test_cvt_sr_fp8_f32_byte2:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-NEXT: global_store_b32 v[4:5], v2, off

6
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
View File

@ -72,6 +72,7 @@ define i32 @test_cvt_pk_fp8_f32_word1(float %x, float %y, i32 %old) {
define amdgpu_cs void @test_cvt_pk_fp8_f32_word1_dpp(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) {
; GFX1250-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1_dpp:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -81,6 +82,7 @@ define amdgpu_cs void @test_cvt_pk_fp8_f32_word1_dpp(i32 %a, float %y, i32 %old,
;
; GFX1250-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1_dpp:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -90,6 +92,7 @@ define amdgpu_cs void @test_cvt_pk_fp8_f32_word1_dpp(i32 %a, float %y, i32 %old,
;
; GFX1250-GISEL-LABEL: test_cvt_pk_fp8_f32_word1_dpp:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -158,6 +161,7 @@ define i32 @test_cvt_sr_fp8_f32_byte3(float %x, i32 %r, i32 %old) {
define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1_dpp(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) {
; GFX1250-TRUE16-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-TRUE16-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-TRUE16-NEXT: global_store_b32 v[4:5], v2, off
@ -165,6 +169,7 @@ define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1_dpp(i32 %a, i32 %r, i32 %old, p
;
; GFX1250-FAKE16-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-FAKE16-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -172,6 +177,7 @@ define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1_dpp(i32 %a, i32 %r, i32 %old, p
;
; GFX1250-GISEL-LABEL: test_cvt_sr_fp8_f32_byte1_dpp:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 clamp quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v2, off

64
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
View File

@ -12,6 +12,7 @@ declare i32 @llvm.amdgcn.cvt.sr.fp8.f16(half, i32, i32, i32)
define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v0.l, v0
; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v0, off
@ -19,6 +20,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_bf8_f16 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[2:3], v0, off
@ -26,6 +28,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v0.l, v0
; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[4:5], v0, off
@ -33,6 +36,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_v:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_bf8_f16 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[4:5], v0, off
@ -45,24 +49,28 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
define amdgpu_ps void @test_cvt_pk_bf8_f16_s(<2 x half> inreg %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, s0
; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT: s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, s0
; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, s0
; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT: s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_s:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, s0
; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
@ -74,24 +82,28 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_s(<2 x half> inreg %a, ptr addrspace(
define amdgpu_ps void @test_cvt_pk_bf8_f16_l(ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, 0x56400000
; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT: s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, 0x56400000
; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, 0x56400000
; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT: s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_l:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_bf8_f16 v2, 0x56400000
; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
@ -103,6 +115,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_l(ptr addrspace(1) %out) {
define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v0.l, v0
; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v0, off
@ -110,6 +123,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_fp8_f16 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[2:3], v0, off
@ -117,6 +131,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v0.l, v0
; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[4:5], v0, off
@ -124,6 +139,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_v:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_fp8_f16 v0, v0
; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[4:5], v0, off
@ -136,24 +152,28 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %ou
define amdgpu_ps void @test_cvt_pk_fp8_f16_s(<2 x half> inreg %a, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, s0
; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT: s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, s0
; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, s0
; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT: s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_s:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, s0
; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
@ -165,24 +185,28 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_s(<2 x half> inreg %a, ptr addrspace(
define amdgpu_ps void @test_cvt_pk_fp8_f16_l(ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, 0x56400000
; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-REAL16-NEXT: s_endpgm
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, 0x56400000
; GFX1250-SDAG-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, 0x56400000
; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-REAL16-NEXT: s_endpgm
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_l:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_fp8_f16 v2, 0x56400000
; GFX1250-GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
@ -194,6 +218,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_l(ptr addrspace(1) %out) {
define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -201,6 +226,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -208,6 +234,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -215,6 +242,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -227,6 +255,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -234,6 +263,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -241,6 +271,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -248,6 +279,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:1
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -260,6 +292,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -267,6 +300,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -274,6 +308,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -281,6 +316,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte2:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:2
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -293,6 +329,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -300,6 +337,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -307,6 +345,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -314,6 +353,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_byte3:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -326,6 +366,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.h, v1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -333,6 +374,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0
; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -342,6 +384,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -351,6 +394,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -366,6 +410,7 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -373,6 +418,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -380,6 +426,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -387,6 +434,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -399,6 +447,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -406,6 +455,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -413,6 +463,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:1
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -420,6 +471,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:1
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -432,6 +484,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -439,6 +492,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -446,6 +500,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:2
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -453,6 +508,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte2:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:2
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -465,6 +521,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte2(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -472,6 +529,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3
; GFX1250-SDAG-FAKE16-NEXT: global_store_b32 v[4:5], v2, off
@ -479,6 +537,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: global_store_b32 v[6:7], v2, off
@ -486,6 +545,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_byte3:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1 byte_sel:3
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
@ -498,6 +558,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte3(half %a, i32 %sr, i32 %old, ptr
define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-SDAG-REAL16: ; %bb.0:
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.h, v1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
@ -505,6 +566,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-SDAG-FAKE16: ; %bb.0:
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0
; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v4, v3
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -514,6 +576,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
;
; GFX1250-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-REAL16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@ -523,6 +586,7 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-FAKE16-NEXT: v_dual_lshrrev_b32 v0, 16, v0 :: v_dual_mov_b32 v6, v3
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)

5
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
View File

@ -7,6 +7,7 @@ declare <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float, float, i32) #0
define amdgpu_ps float @cvt_sr_pk_f16_f32_vvv(float %src0, float %src1, i32 %src2) #1 {
; GCN-LABEL: cvt_sr_pk_f16_f32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 %src2) #0
@ -17,6 +18,7 @@ define amdgpu_ps float @cvt_sr_pk_f16_f32_vvv(float %src0, float %src1, i32 %src
define amdgpu_ps float @cvt_sr_pk_f16_f32_sss(float inreg %src0, float inreg %src1, i32 inreg %src2) #1 {
; GCN-LABEL: cvt_sr_pk_f16_f32_sss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, s0, s1, v0
@ -29,6 +31,7 @@ define amdgpu_ps float @cvt_sr_pk_f16_f32_sss(float inreg %src0, float inreg %sr
define amdgpu_ps float @cvt_sr_pk_f16_f32_vvi(float %src0, float %src1) #1 {
; GCN-LABEL: cvt_sr_pk_f16_f32_vvi:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, v0, v1, 0x10002
; GCN-NEXT: ; return to shader part epilog
%cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 65538) #0
@ -39,6 +42,7 @@ define amdgpu_ps float @cvt_sr_pk_f16_f32_vvi(float %src0, float %src1) #1 {
define amdgpu_ps float @cvt_sr_pk_f16_f32_vvi_mods(float %src0, float %src1) #1 {
; GCN-LABEL: cvt_sr_pk_f16_f32_vvi_mods:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, -v0, |v1|, 1
; GCN-NEXT: ; return to shader part epilog
%s0 = fneg float %src0
@ -51,6 +55,7 @@ define amdgpu_ps float @cvt_sr_pk_f16_f32_vvi_mods(float %src0, float %src1) #1
define amdgpu_ps float @cvt_sr_pk_f16_f32_ssi(float inreg %src0, float inreg %src1) #1 {
; GCN-LABEL: cvt_sr_pk_f16_f32_ssi:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_f16_f32 v0, s0, s1, 1
; GCN-NEXT: ; return to shader part epilog
%cvt = call <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float %src0, float %src1, i32 1) #0

24
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
View File

@ -10,6 +10,7 @@ declare i16 @llvm.amdgcn.sat.pk4.u4.u8(i32) #0
define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_clause 0x1
; SDAG-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -21,6 +22,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_clause 0x1
; SDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -32,6 +34,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-REAL16-NEXT: s_clause 0x1
; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -43,6 +46,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-FAKE16-NEXT: s_clause 0x1
; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -59,6 +63,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -68,6 +73,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s8
@ -77,6 +83,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-REAL16-NEXT: s_clause 0x1
; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -88,6 +95,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-FAKE16-NEXT: s_clause 0x1
; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -104,6 +112,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -113,6 +122,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, 0x64
@ -122,6 +132,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -131,6 +142,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, 0x64
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -145,6 +157,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_clause 0x1
; SDAG-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -156,6 +169,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_clause 0x1
; SDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -167,6 +181,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-REAL16-NEXT: s_clause 0x1
; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -178,6 +193,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-FAKE16-NEXT: s_clause 0x1
; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -194,6 +210,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -203,6 +220,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s8
@ -212,6 +230,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-REAL16-NEXT: s_clause 0x1
; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -223,6 +242,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-FAKE16-NEXT: s_clause 0x1
; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -239,6 +259,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -248,6 +269,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, 0x64
@ -257,6 +279,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -266,6 +289,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, 0x64
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0

30
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
View File

@ -21,6 +21,7 @@ declare <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> %src, i32 %sc
define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_fp8_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3
; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_fp8 v[4:7], v[0:1], v2 scale_sel:1
; GFX1250-SDAG-NEXT: global_store_b128 v[8:9], v[4:7], off
@ -28,6 +29,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale,
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_fp8_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_fp8 v[4:7], v[0:1], v2 scale_sel:1
; GFX1250-GISEL-NEXT: global_store_b128 v[8:9], v[4:7], off
@ -40,6 +42,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale,
define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_bf8_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3
; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_bf8 v[4:7], v[0:1], v2
; GFX1250-SDAG-NEXT: global_store_b128 v[8:9], v[4:7], off
@ -47,6 +50,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale,
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_bf8_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_bf8 v[4:7], v[0:1], v2
; GFX1250-GISEL-NEXT: global_store_b128 v[8:9], v[4:7], off
@ -59,6 +63,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale,
define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp8_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3
; GFX1250-NEXT: v_cvt_scale_pk8_bf16_fp8 v[4:7], v[0:1], v2 scale_sel:1
; GFX1250-NEXT: global_store_b128 v[8:9], v[4:7], off
@ -71,6 +76,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp8_vv(<2 x i32> %src, i32 %scale
define amdgpu_ps void @test_cvt_scale_pk8_bf16_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_bf16_bf8_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3
; GFX1250-NEXT: v_cvt_scale_pk8_bf16_bf8 v[4:7], v[0:1], v2 scale_sel:2
; GFX1250-NEXT: global_store_b128 v[8:9], v[4:7], off
@ -83,6 +89,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_bf16_bf8_vv(<2 x i32> %src, i32 %scale
define amdgpu_ps void @test_cvt_scale_pk8_f16_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_f16_fp4_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scale_pk8_f16_fp4 v[4:7], v0, v1 scale_sel:3
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
; GFX1250-NEXT: s_endpgm
@ -94,6 +101,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp4_vv(i32 %src, i32 %scale, ptr a
define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp4_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scale_pk8_bf16_fp4 v[4:7], v0, v1 scale_sel:4
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
; GFX1250-NEXT: s_endpgm
@ -105,6 +113,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp4_vv(i32 %src, i32 %scale, ptr
define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp8_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_fp8 v[4:11], v[0:1], v2 scale_sel:8
; GFX1250-SDAG-NEXT: s_clause 0x1
@ -114,6 +123,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_vv(<2 x i32> %src, i32 %scale,
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_fp8_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v13, v4
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp8 v[4:11], v[0:1], v2 scale_sel:8
; GFX1250-GISEL-NEXT: s_clause 0x1
@ -128,6 +138,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_vv(<2 x i32> %src, i32 %scale,
define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_bf8_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_bf8 v[4:11], v[0:1], v2
; GFX1250-SDAG-NEXT: s_clause 0x1
@ -137,6 +148,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_vv(<2 x i32> %src, i32 %scale,
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_bf8_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v13, v4
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_bf8 v[4:11], v[0:1], v2
; GFX1250-GISEL-NEXT: s_clause 0x1
@ -151,6 +163,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_vv(<2 x i32> %src, i32 %scale,
define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp4_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_fp4 v[4:11], v0, v1 scale_sel:1
; GFX1250-SDAG-NEXT: s_clause 0x1
; GFX1250-SDAG-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16
@ -159,6 +172,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr a
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_fp4_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp4 v[4:11], v0, v1 scale_sel:1
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[2:3], v[4:7], off
@ -172,6 +186,7 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr a
define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_fp6 v[6:13], v[0:2], v3
; GFX1250-SDAG-NEXT: s_clause 0x1
; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
@ -180,6 +195,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[6:13], v[0:2], v3
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off
@ -193,6 +209,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale
define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -204,6 +221,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -220,6 +238,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr
define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk16_bf16_fp6_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scale_pk16_bf16_fp6 v[6:13], v[0:2], v3 scale_sel:2
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
@ -233,6 +252,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_vv(<3 x i32> %src, i32 %scal
define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk16_bf16_fp6_sl:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
; GFX1250-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -249,6 +269,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_sl(<3 x i32> inreg %src, ptr
define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_bf6 v[6:13], v[0:2], v3 scale_sel:4
; GFX1250-SDAG-NEXT: s_clause 0x1
; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
@ -257,6 +278,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_vv(<3 x i32> %src, i32 %scale
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[6:13], v[0:2], v3 scale_sel:4
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off
@ -270,6 +292,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_vv(<3 x i32> %src, i32 %scale
define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -281,6 +304,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -297,6 +321,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr
define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk16_bf16_bf6_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scale_pk16_bf16_bf6 v[6:13], v[0:2], v3 scale_sel:6
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16
@ -310,6 +335,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_vv(<3 x i32> %src, i32 %scal
define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk16_bf16_bf6_sl:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
; GFX1250-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -326,6 +352,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_sl(<3 x i32> inreg %src, ptr
define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_fp6_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_fp6 v[6:21], v[0:2], v3 scale_sel:5
; GFX1250-SDAG-NEXT: s_clause 0x3
; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48
@ -336,6 +363,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_vv(<3 x i32> %src, i32 %scale
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_fp6_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_fp6 v[6:21], v[0:2], v3 scale_sel:5
; GFX1250-GISEL-NEXT: s_clause 0x3
; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off
@ -351,6 +379,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_vv(<3 x i32> %src, i32 %scale
define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_bf6_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_bf6 v[6:21], v[0:2], v3 scale_sel:6
; GFX1250-SDAG-NEXT: s_clause 0x3
; GFX1250-SDAG-NEXT: global_store_b128 v[4:5], v[18:21], off offset:48
@ -361,6 +390,7 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_vv(<3 x i32> %src, i32 %scale
;
; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_bf6_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_bf6 v[6:21], v[0:2], v3 scale_sel:6
; GFX1250-GISEL-NEXT: s_clause 0x3
; GFX1250-GISEL-NEXT: global_store_b128 v[4:5], v[6:9], off

24
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
View File

@ -13,6 +13,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %s
; GFX1210-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v17
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v16
; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off
@ -20,6 +21,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %s
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v18
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v16
; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off
@ -32,6 +34,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %s
define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -47,6 +50,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, pt
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
@ -67,6 +71,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, pt
define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v17
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v16
; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off
@ -74,6 +79,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %s
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v18
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v16
; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off
@ -86,6 +92,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %s
define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -101,6 +108,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, pt
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
@ -121,6 +129,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, pt
define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -128,6 +137,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_vv(<16 x bfloat> %src, float
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -140,6 +150,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_vv(<16 x bfloat> %src, float
define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -151,6 +162,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -167,6 +179,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src,
define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -174,6 +187,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %sc
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -186,6 +200,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %sc
define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -197,6 +212,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -213,6 +229,7 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr
define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -220,6 +237,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_vv(<16 x bfloat> %src, float
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -232,6 +250,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_vv(<16 x bfloat> %src, float
define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -243,6 +262,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -259,6 +279,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src,
define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -266,6 +287,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %sc
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
@ -278,6 +300,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %sc
define amdgpu_ps void @test_scalef32_pk16_fp6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -289,6 +312,7 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f16_sl(<16 x half> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]

36
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
View File

@ -15,6 +15,7 @@ declare i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.bf16(<8 x bfloat> %src, float %sca
define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
@ -22,6 +23,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_vv(<8 x bfloat> %src, float %s
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_bf16 v[8:9], v[0:3], v4
; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off
@ -34,6 +36,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_vv(<8 x bfloat> %src, float %s
define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -43,6 +46,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, pt
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -57,6 +61,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, pt
define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
@ -64,6 +69,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_vv(<8 x bfloat> %src, float %s
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_bf16 v[8:9], v[0:3], v4
; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off
@ -76,6 +82,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_vv(<8 x bfloat> %src, float %s
define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -85,6 +92,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, pt
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -99,6 +107,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, pt
define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
@ -106,6 +115,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scal
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[0:3], v4
; GFX1250-GISEL-NEXT: global_store_b64 v[8:9], v[6:7], off
@ -118,6 +128,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scal
define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -127,6 +138,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr a
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -141,6 +153,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr a
define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[8:9], v[0:3], v4
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
@ -148,6 +161,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scal
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[0:3], v4
; GFX1250-GISEL-NEXT: global_store_b64 v[8:9], v[6:7], off
@ -160,6 +174,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scal
define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -169,6 +184,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr a
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -183,6 +199,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr a
define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[12:13], v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off
@ -190,6 +207,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %sca
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b64 v[12:13], v[10:11], off
@ -202,6 +220,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %sca
define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -213,6 +232,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -229,6 +249,7 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr
define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[12:13], v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off
@ -236,6 +257,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %sca
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b64 v[12:13], v[10:11], off
@ -248,6 +270,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %sca
define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -259,6 +282,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -275,6 +299,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr
define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v9
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8
; GFX1250-SDAG-NEXT: global_store_b32 v[10:11], v9, off
@ -282,6 +307,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %sca
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v10
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f32 v9, v[0:7], v8
; GFX1250-GISEL-NEXT: global_store_b32 v[12:13], v9, off
@ -294,6 +320,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %sca
define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -305,6 +332,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -321,6 +349,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr
define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4
; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v5, off
@ -328,6 +357,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scal
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f16 v5, v[0:3], v4
; GFX1250-GISEL-NEXT: global_store_b32 v[8:9], v5, off
@ -340,6 +370,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scal
define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -349,6 +380,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr a
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -363,6 +395,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr a
define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_vv(<8 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4
; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v5, off
@ -370,6 +403,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_vv(<8 x bfloat> %src, float %s
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_bf16 v5, v[0:3], v4
; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v5, off
@ -382,6 +416,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_vv(<8 x bfloat> %src, float %s
define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -391,6 +426,7 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, pt
;
; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)

36
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
View File

@ -15,12 +15,14 @@ declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.bf16(<8 x bfloat> %src, i32 %sr
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[8:9], v[0:3], v4, v5
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_bf16 v[8:9], v[0:3], v4, v5
; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-GISEL-NEXT: s_endpgm
@ -32,6 +34,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_vv(<8 x bfloat> %src, i32 %
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -41,6 +44,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -55,12 +59,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_bf16_sl(<8 x bfloat> inreg %src,
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[8:9], v[0:3], v4, v5
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_bf16 v[8:9], v[0:3], v4, v5
; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-GISEL-NEXT: s_endpgm
@ -72,6 +78,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_vv(<8 x bfloat> %src, i32 %
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -81,6 +88,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -95,12 +103,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_bf16_sl(<8 x bfloat> inreg %src,
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[8:9], v[0:3], v4, v5
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[8:9], v[0:3], v4, v5
; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-GISEL-NEXT: s_endpgm
@ -112,6 +122,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_vv(<8 x half> %src, i32 %sr,
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -121,6 +132,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_sl(<8 x half> inreg %src, i3
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -135,12 +147,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_sl(<8 x half> inreg %src, i3
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[8:9], v[0:3], v4, v5
; GFX1250-SDAG-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[8:9], v[0:3], v4, v5
; GFX1250-GISEL-NEXT: global_store_b64 v[6:7], v[8:9], off
; GFX1250-GISEL-NEXT: s_endpgm
@ -152,6 +166,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_vv(<8 x half> %src, i32 %sr,
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -161,6 +176,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_sl(<8 x half> inreg %src, i3
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -175,12 +191,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_sl(<8 x half> inreg %src, i3
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[12:13], v[0:7], v8, v9
; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[12:13], v[0:7], v8, v9
; GFX1250-GISEL-NEXT: global_store_b64 v[10:11], v[12:13], off
; GFX1250-GISEL-NEXT: s_endpgm
@ -192,6 +210,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_vv(<8 x float> %src, i32 %sr
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -203,6 +222,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_sl(<8 x float> inreg %src, i
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -219,12 +239,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_sl(<8 x float> inreg %src, i
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[12:13], v[0:7], v8, v9
; GFX1250-SDAG-NEXT: global_store_b64 v[10:11], v[12:13], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[12:13], v[0:7], v8, v9
; GFX1250-GISEL-NEXT: global_store_b64 v[10:11], v[12:13], off
; GFX1250-GISEL-NEXT: s_endpgm
@ -236,6 +258,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_vv(<8 x float> %src, i32 %sr
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -247,6 +270,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_sl(<8 x float> inreg %src, i
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -263,12 +287,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_sl(<8 x float> inreg %src, i
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_vv(<8 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v12, v[0:7], v8, v9
; GFX1250-SDAG-NEXT: global_store_b32 v[10:11], v12, off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v12, v[0:7], v8, v9
; GFX1250-GISEL-NEXT: global_store_b32 v[10:11], v12, off
; GFX1250-GISEL-NEXT: s_endpgm
@ -280,6 +306,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_vv(<8 x float> %src, i32 %sr
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -291,6 +318,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_sl(<8 x float> inreg %src, i
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -307,12 +335,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_sl(<8 x float> inreg %src, i
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_vv(<8 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v8, v[0:3], v4, v5
; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v8, off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v8, v[0:3], v4, v5
; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v8, off
; GFX1250-GISEL-NEXT: s_endpgm
@ -324,6 +354,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_vv(<8 x half> %src, i32 %sr,
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -333,6 +364,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_sl(<8 x half> inreg %src, i3
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -347,12 +379,14 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_sl(<8 x half> inreg %src, i3
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_vv(<8 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_bf16_vv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v8, v[0:3], v4, v5
; GFX1250-SDAG-NEXT: global_store_b32 v[6:7], v8, off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_bf16_vv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_bf16 v8, v[0:3], v4, v5
; GFX1250-GISEL-NEXT: global_store_b32 v[6:7], v8, off
; GFX1250-GISEL-NEXT: s_endpgm
@ -364,6 +398,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_vv(<8 x bfloat> %src, i32 %
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_bf16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
@ -373,6 +408,7 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_bf16_sl(<8 x bfloat> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_bf16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)

16
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
View File

@ -12,6 +12,7 @@ declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_bf16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT: s_endpgm
@ -23,6 +24,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_vv(<16 x bfloat> %src, i32
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_bf16_sl:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -39,6 +41,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_bf16_sl(<16 x bfloat> inreg %sr
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT: s_endpgm
@ -50,6 +53,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_vv(<16 x half> %src, i32 %s
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -61,6 +65,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -77,6 +82,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src,
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_vv(<16 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_bf16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT: s_endpgm
@ -88,6 +94,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_vv(<16 x bfloat> %src, i32
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_bf16_sl:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -104,6 +111,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_bf16_sl(<16 x bfloat> inreg %sr
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_vv(<16 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[12:14], v[0:7], v8, v9
; GFX1250-NEXT: global_store_b96 v[10:11], v[12:14], off
; GFX1250-NEXT: s_endpgm
@ -115,6 +123,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_vv(<16 x half> %src, i32 %s
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -126,6 +135,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
@ -142,6 +152,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src,
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_bf6_f32_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[20:22], v[0:15], v16, v17
; GFX1250-NEXT: global_store_b96 v[18:19], v[20:22], off
; GFX1250-NEXT: s_endpgm
@ -153,6 +164,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_vv(<16 x float> %src, i32 %
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -168,6 +180,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
@ -188,6 +201,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src,
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_vv(<16 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_scalef32_sr_pk16_fp6_f32_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[20:22], v[0:15], v16, v17
; GFX1250-NEXT: global_store_b96 v[18:19], v[20:22], off
; GFX1250-NEXT: s_endpgm
@ -199,6 +213,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_vv(<16 x float> %src, i32 %
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
@ -214,6 +229,7 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_sl(<16 x float> inreg %src,
;
; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]

5
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
View File

@ -9,6 +9,7 @@ declare <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float, float, i32) #0
define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvv(float %src0, float %src1, i32 %src2) #1 {
; GCN-LABEL: cvt_sr_pk_bf16_f32_vvv:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, v0, v1, v2
; GCN-NEXT: ; return to shader part epilog
%cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 %src2) #0
@ -19,6 +20,7 @@ define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvv(float %src0, float %src1, i32 %sr
define amdgpu_ps float @cvt_sr_pk_bf16_f32_sss(float inreg %src0, float inreg %src1, i32 inreg %src2) #1 {
; GCN-LABEL: cvt_sr_pk_bf16_f32_sss:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, s0, s1, v0
@ -31,6 +33,7 @@ define amdgpu_ps float @cvt_sr_pk_bf16_f32_sss(float inreg %src0, float inreg %s
define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvi(float %src0, float %src1) #1 {
; GCN-LABEL: cvt_sr_pk_bf16_f32_vvi:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, v0, v1, 0x10002
; GCN-NEXT: ; return to shader part epilog
%cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 65538) #0
@ -41,6 +44,7 @@ define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvi(float %src0, float %src1) #1 {
define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvi_mods(float %src0, float %src1) #1 {
; GCN-LABEL: cvt_sr_pk_bf16_f32_vvi_mods:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, -v0, |v1|, 1
; GCN-NEXT: ; return to shader part epilog
%s0 = fneg float %src0
@ -53,6 +57,7 @@ define amdgpu_ps float @cvt_sr_pk_bf16_f32_vvi_mods(float %src0, float %src1) #1
define amdgpu_ps float @cvt_sr_pk_bf16_f32_ssi(float inreg %src0, float inreg %src1) #1 {
; GCN-LABEL: cvt_sr_pk_bf16_f32_ssi:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_cvt_sr_pk_bf16_f32 v0, s0, s1, 1
; GCN-NEXT: ; return to shader part epilog
%cvt = call <2 x bfloat> @llvm.amdgcn.cvt.sr.pk.bf16.f32(float %src0, float %src1, i32 1) #0

9
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
View File

@ -7,6 +7,7 @@ declare void @llvm.amdgcn.flat.prefetch(ptr %ptr, i32 %col)
define amdgpu_ps void @flat_prefetch(ptr %ptr) {
; GCN-LABEL: flat_prefetch:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v[0:1]
; GCN-NEXT: s_endpgm
entry:
@ -17,6 +18,7 @@ entry:
define amdgpu_ps void @flat_prefetch_sgpr(ptr inreg %ptr) {
; GCN-LABEL: flat_prefetch_sgpr:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: flat_prefetch_b8 v0, s[0:1]
; GCN-NEXT: s_endpgm
@ -28,6 +30,7 @@ entry:
define amdgpu_ps void @flat_prefetch_offset(ptr %ptr) {
; GCN-LABEL: flat_prefetch_offset:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v[0:1] offset:512
; GCN-NEXT: s_endpgm
entry:
@ -39,6 +42,7 @@ entry:
define amdgpu_ps void @flat_prefetch_sgpr_voffset(ptr inreg %ptr, i32 %offset) {
; GCN-LABEL: flat_prefetch_sgpr_voffset:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v0, s[0:1]
; GCN-NEXT: s_endpgm
entry:
@ -50,6 +54,7 @@ entry:
define amdgpu_ps void @flat_prefetch_sgpr_voffset_offset(ptr inreg %ptr, i32 %offset) {
; GCN-LABEL: flat_prefetch_sgpr_voffset_offset:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v0, s[0:1] offset:128
; GCN-NEXT: s_endpgm
entry:
@ -62,6 +67,7 @@ entry:
define amdgpu_ps void @flat_prefetch_se(ptr %ptr) {
; GCN-LABEL: flat_prefetch_se:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SE
; GCN-NEXT: s_endpgm
entry:
@ -72,6 +78,7 @@ entry:
define amdgpu_ps void @flat_prefetch_se_nt(ptr %ptr) {
; GCN-LABEL: flat_prefetch_se_nt:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v[0:1] th:TH_LOAD_NT scope:SCOPE_SE
; GCN-NEXT: s_endpgm
entry:
@ -82,6 +89,7 @@ entry:
define amdgpu_ps void @flat_prefetch_dev_ht(ptr %ptr) {
; GCN-LABEL: flat_prefetch_dev_ht:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v[0:1] th:TH_LOAD_HT scope:SCOPE_DEV
; GCN-NEXT: s_endpgm
entry:
@ -92,6 +100,7 @@ entry:
define amdgpu_ps void @flat_prefetch_sys_lu(ptr %ptr) {
; GCN-LABEL: flat_prefetch_sys_lu:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: flat_prefetch_b8 v[0:1] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GCN-NEXT: s_endpgm
entry:

15
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
View File

@ -10,12 +10,14 @@ declare void @llvm.amdgcn.global.load.async.to.lds.b128(ptr addrspace(1) %gaddr,
define amdgpu_ps void @global_load_async_to_lds_b8_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_load_async_to_lds_b8_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_load_async_to_lds_b8 v2, v[0:1], off offset:16 th:TH_LOAD_NT
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_load_async_to_lds_b8_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -30,6 +32,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b8_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_load_async_to_lds_b8_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -42,12 +45,14 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b32_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_load_async_to_lds_b32_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_load_async_to_lds_b32 v2, v[0:1], off offset:16 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_load_async_to_lds_b32_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -62,6 +67,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b32_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_load_async_to_lds_b32_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -74,12 +80,14 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b64_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_load_async_to_lds_b64_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_load_async_to_lds_b64 v2, v[0:1], off offset:16 th:TH_LOAD_NT_HT scope:SCOPE_DEV
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_load_async_to_lds_b64_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -94,6 +102,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b64_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_load_async_to_lds_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -106,12 +115,14 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b128_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_load_async_to_lds_b128_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_load_async_to_lds_b128 v2, v[0:1], off offset:16 th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_load_async_to_lds_b128_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -126,6 +137,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b128_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_load_async_to_lds_b128_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -138,6 +150,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b32_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 %idx) {
; GFX1250-LABEL: global_load_async_to_lds_b32_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_endpgm
entry:
@ -150,6 +163,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b64_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 %idx) {
; GFX1250-LABEL: global_load_async_to_lds_b64_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_endpgm
entry:
@ -162,6 +176,7 @@ entry:
define amdgpu_ps void @global_load_async_to_lds_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 %idx) {
; GFX1250-LABEL: global_load_async_to_lds_b64_saddr_no_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2

9
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
View File

@ -7,6 +7,7 @@ declare void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 %col)
define amdgpu_ps void @global_prefetch(ptr addrspace(1) %ptr) {
; GCN-LABEL: global_prefetch:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v[0:1], off
; GCN-NEXT: s_endpgm
entry:
@ -17,6 +18,7 @@ entry:
define amdgpu_ps void @global_prefetch_sgpr(ptr addrspace(1) inreg %ptr) {
; GCN-LABEL: global_prefetch_sgpr:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_prefetch_b8 v0, s[0:1]
; GCN-NEXT: s_endpgm
@ -28,6 +30,7 @@ entry:
define amdgpu_ps void @global_prefetch_offset(ptr addrspace(1) %ptr) {
; GCN-LABEL: global_prefetch_offset:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v[0:1], off offset:512
; GCN-NEXT: s_endpgm
entry:
@ -39,6 +42,7 @@ entry:
define amdgpu_ps void @global_prefetch_sgpr_voffset(ptr addrspace(1) inreg %ptr, i32 %offset) {
; GCN-LABEL: global_prefetch_sgpr_voffset:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v0, s[0:1]
; GCN-NEXT: s_endpgm
entry:
@ -50,6 +54,7 @@ entry:
define amdgpu_ps void @global_prefetch_sgpr_voffset_offset(ptr addrspace(1) inreg %ptr, i32 %offset) {
; GCN-LABEL: global_prefetch_sgpr_voffset_offset:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v0, s[0:1] offset:128
; GCN-NEXT: s_endpgm
entry:
@ -62,6 +67,7 @@ entry:
define amdgpu_ps void @global_prefetch_se(ptr addrspace(1) %ptr) {
; GCN-LABEL: global_prefetch_se:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v[0:1], off scope:SCOPE_SE
; GCN-NEXT: s_endpgm
entry:
@ -72,6 +78,7 @@ entry:
define amdgpu_ps void @global_prefetch_se_nt(ptr addrspace(1) %ptr) {
; GCN-LABEL: global_prefetch_se_nt:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v[0:1], off th:TH_LOAD_NT scope:SCOPE_SE
; GCN-NEXT: s_endpgm
entry:
@ -82,6 +89,7 @@ entry:
define amdgpu_ps void @global_prefetch_dev_ht(ptr addrspace(1) %ptr) {
; GCN-LABEL: global_prefetch_dev_ht:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v[0:1], off th:TH_LOAD_HT scope:SCOPE_DEV
; GCN-NEXT: s_endpgm
entry:
@ -92,6 +100,7 @@ entry:
define amdgpu_ps void @global_prefetch_sys_lu(ptr addrspace(1) %ptr) {
; GCN-LABEL: global_prefetch_sys_lu:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: global_prefetch_b8 v[0:1], off th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GCN-NEXT: s_endpgm
entry:

15
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
View File

@ -10,12 +10,14 @@ declare void @llvm.amdgcn.global.store.async.from.lds.b128(ptr addrspace(1) %gad
define amdgpu_ps void @global_store_async_from_lds_b8_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_store_async_from_lds_b8_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_store_async_from_lds_b8 v[0:1], v2, off offset:16 th:TH_STORE_NT
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_store_async_from_lds_b8_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -30,6 +32,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b8_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_store_async_from_lds_b8_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_store_async_from_lds_b8 v1, v0, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -42,12 +45,14 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b32(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_store_async_from_lds_b32:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_store_async_from_lds_b32 v[0:1], v2, off offset:16 th:TH_STORE_HT scope:SCOPE_SE
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_store_async_from_lds_b32:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -62,6 +67,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b32_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_store_async_from_lds_b32_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_store_async_from_lds_b32 v1, v0, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -74,12 +80,14 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b64_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_store_async_from_lds_b64_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_store_async_from_lds_b64 v[0:1], v2, off offset:16 th:TH_STORE_NT_HT scope:SCOPE_DEV
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_store_async_from_lds_b64_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -94,6 +102,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b64_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_store_async_from_lds_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_store_async_from_lds_b64 v1, v0, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -106,12 +115,14 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b128_vaddr(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-SDAG-LABEL: global_store_async_from_lds_b128_vaddr:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
; GFX1250-SDAG-NEXT: global_store_async_from_lds_b128 v[0:1], v2, off offset:16 th:TH_STORE_BYPASS scope:SCOPE_SYS
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: global_store_async_from_lds_b128_vaddr:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@ -126,6 +137,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b128_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr) {
; GFX1250-LABEL: global_store_async_from_lds_b128_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, 32
; GFX1250-NEXT: global_store_async_from_lds_b128 v1, v0, s[0:1] offset:16
; GFX1250-NEXT: s_endpgm
@ -138,6 +150,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b32_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 %idx) {
; GFX1250-LABEL: global_store_async_from_lds_b32_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_store_async_from_lds_b32 v1, v0, s[0:1] offset:16 scale_offset th:TH_STORE_NT
; GFX1250-NEXT: s_endpgm
entry:
@ -150,6 +163,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b64_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 %idx) {
; GFX1250-LABEL: global_store_async_from_lds_b64_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_store_async_from_lds_b64 v1, v0, s[0:1] offset:16 scale_offset th:TH_STORE_NT
; GFX1250-NEXT: s_endpgm
entry:
@ -162,6 +176,7 @@ entry:
define amdgpu_ps void @global_store_async_from_lds_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 %idx) {
; GFX1250-LABEL: global_store_async_from_lds_b64_saddr_no_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2

3
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
View File

@ -61,6 +61,7 @@ define amdgpu_kernel void @is_private_vgpr(ptr addrspace(1) %ptr.ptr) {
;
; GFX1250-LABEL: is_private_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -187,6 +188,7 @@ define amdgpu_kernel void @is_private_sgpr(ptr %ptr) {
;
; GFX1250-SDAG-LABEL: is_private_sgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x4
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT: s_xor_b32 s0, s0, src_flat_scratch_base_hi
@ -264,6 +266,7 @@ define amdgpu_kernel void @is_private_sgpr(ptr %ptr) {
;
; GFX1250-GISEL-LABEL: is_private_sgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: s_xor_b32 s0, s1, src_flat_scratch_base_hi

3
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
View File

@ -94,6 +94,7 @@ define amdgpu_kernel void @is_local_vgpr(ptr addrspace(1) %ptr.ptr) {
;
; GFX1250-LABEL: is_local_vgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: s_mov_b64 s[0:1], src_shared_base
@ -253,6 +254,7 @@ define amdgpu_kernel void @is_local_sgpr(ptr %ptr) {
;
; GFX1250-SDAG-LABEL: is_local_sgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], src_shared_base
; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x4
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -330,6 +332,7 @@ define amdgpu_kernel void @is_local_sgpr(ptr %ptr) {
;
; GFX1250-GISEL-LABEL: is_local_sgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-GISEL-NEXT: s_mov_b64 s[0:1], src_shared_base
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0

12
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
View File

@ -12,6 +12,7 @@ declare <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr, i32)
define amdgpu_ps void @global_load_monitor_b32_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_monitor_b32_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_monitor_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b32 v[2:3], v0, off
@ -26,6 +27,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b32_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_monitor_b32_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -41,6 +43,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_monitor_b64_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_monitor_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
@ -55,6 +58,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_monitor_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -70,6 +74,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b128_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_monitor_b128_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_monitor_b128 v[4:7], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
@ -84,6 +89,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b128_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_monitor_b128_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_monitor_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -99,6 +105,7 @@ entry:
define amdgpu_ps void @flat_load_monitor_b32(ptr %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: flat_load_monitor_b32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_load_monitor_b32 v0, v[0:1] offset:32 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_store_b32 v[2:3], v0, off
@ -113,6 +120,7 @@ entry:
define amdgpu_ps void @flat_load_monitor_b64(ptr %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: flat_load_monitor_b64:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_load_monitor_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
@ -127,6 +135,7 @@ entry:
define amdgpu_ps void @flat_load_monitor_b128(ptr %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: flat_load_monitor_b128:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_load_monitor_b128 v[4:7], v[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
@ -141,6 +150,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b32_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) {
; GFX1250-LABEL: global_load_monitor_b32_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
@ -156,6 +166,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b64_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) {
; GFX1250-LABEL: global_load_monitor_b64_saddr_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
@ -171,6 +182,7 @@ entry:
define amdgpu_ps void @global_load_monitor_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) {
; GFX1250-LABEL: global_load_monitor_b64_saddr_no_scale_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]

23
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
View File

@ -20,6 +20,7 @@ declare <8 x bfloat> @llvm.amdgcn.ds.load.tr16.b128.v8bf16.p3(ptr addrspace(3))
define amdgpu_ps void @global_load_tr4_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr4_b64_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_tr4_b64 v[0:1], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
@ -34,6 +35,7 @@ entry:
define amdgpu_ps void @global_load_tr4_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr4_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_tr4_b64 v[2:3], v2, s[0:1] offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -49,6 +51,7 @@ entry:
define amdgpu_ps void @global_load_tr8_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr8_b64_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_tr8_b64 v[0:1], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
@ -63,6 +66,7 @@ entry:
define amdgpu_ps void @global_load_tr8_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr8_b64_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_tr8_b64 v[2:3], v2, s[0:1] offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -78,6 +82,7 @@ entry:
define amdgpu_ps void @global_load_tr6_b96_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr6_b96_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_tr6_b96 v[4:6], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b96 v[2:3], v[4:6], off
@ -92,6 +97,7 @@ entry:
define amdgpu_ps void @global_load_tr6_b96_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr6_b96_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_tr6_b96 v[2:4], v2, s[0:1] offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -107,6 +113,7 @@ entry:
define amdgpu_ps void @global_load_tr16_b128_v8i16_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr16_b128_v8i16_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_tr16_b128 v[4:7], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
@ -121,6 +128,7 @@ entry:
define amdgpu_ps void @global_load_tr16_b128_v8i16_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr16_b128_v8i16_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_tr16_b128 v[2:5], v2, s[0:1] offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -136,6 +144,7 @@ entry:
define amdgpu_ps void @global_load_tr16_b128_v8f16_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr16_b128_v8f16_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_tr16_b128 v[4:7], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
@ -150,6 +159,7 @@ entry:
define amdgpu_ps void @global_load_tr16_b128_v8f16_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr16_b128_v8f16_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_tr16_b128 v[2:5], v2, s[0:1] offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -165,6 +175,7 @@ entry:
define amdgpu_ps void @global_load_tr16_b128_v8b16_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr16_b128_v8b16_vaddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_tr16_b128 v[4:7], v[0:1], off offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
@ -179,6 +190,7 @@ entry:
define amdgpu_ps void @global_load_tr16_b128_v8bf16_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: global_load_tr16_b128_v8bf16_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: global_load_tr16_b128 v[2:5], v2, s[0:1] offset:32
; GFX1250-NEXT: s_wait_loadcnt 0x0
@ -194,6 +206,7 @@ entry:
define amdgpu_ps void @ds_load_tr4_b64(ptr addrspace(3) %addr, ptr addrspace(1) %use) {
; GFX1250-SDAG-LABEL: ds_load_tr4_b64:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: ds_load_tr4_b64 v[0:1], v0 offset:32
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -202,6 +215,7 @@ define amdgpu_ps void @ds_load_tr4_b64(ptr addrspace(3) %addr, ptr addrspace(1)
;
; GFX1250-GISEL-LABEL: ds_load_tr4_b64:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: ds_load_tr4_b64 v[0:1], v0 offset:32
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -217,6 +231,7 @@ entry:
define amdgpu_ps void @ds_load_tr8_b64(ptr addrspace(3) %addr, ptr addrspace(1) %use) {
; GFX1250-SDAG-LABEL: ds_load_tr8_b64:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-SDAG-NEXT: ds_load_tr8_b64 v[0:1], v0 offset:32
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -225,6 +240,7 @@ define amdgpu_ps void @ds_load_tr8_b64(ptr addrspace(3) %addr, ptr addrspace(1)
;
; GFX1250-GISEL-LABEL: ds_load_tr8_b64:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: ds_load_tr8_b64 v[0:1], v0 offset:32
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -240,6 +256,7 @@ entry:
define amdgpu_ps void @ds_load_tr6_b96(ptr addrspace(3) %addr, ptr addrspace(1) %use) {
; GFX1250-SDAG-LABEL: ds_load_tr6_b96:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX1250-SDAG-NEXT: ds_load_tr6_b96 v[0:2], v0 offset:32
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -248,6 +265,7 @@ define amdgpu_ps void @ds_load_tr6_b96(ptr addrspace(3) %addr, ptr addrspace(1)
;
; GFX1250-GISEL-LABEL: ds_load_tr6_b96:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: ds_load_tr6_b96 v[0:2], v0 offset:32
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -263,6 +281,7 @@ entry:
define amdgpu_ps void @ds_load_tr16_b128_v8i16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {
; GFX1250-SDAG-LABEL: ds_load_tr16_b128_v8i16:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX1250-SDAG-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -271,6 +290,7 @@ define amdgpu_ps void @ds_load_tr16_b128_v8i16(ptr addrspace(3) %addr, ptr addrs
;
; GFX1250-GISEL-LABEL: ds_load_tr16_b128_v8i16:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -286,6 +306,7 @@ entry:
define amdgpu_ps void @ds_load_tr16_b128_v8f16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {
; GFX1250-SDAG-LABEL: ds_load_tr16_b128_v8f16:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX1250-SDAG-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
@ -294,6 +315,7 @@ define amdgpu_ps void @ds_load_tr16_b128_v8f16(ptr addrspace(3) %addr, ptr addrs
;
; GFX1250-GISEL-LABEL: ds_load_tr16_b128_v8f16:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
@ -309,6 +331,7 @@ entry:
define amdgpu_ps void @ds_load_tr16_b128_v8bf16(ptr addrspace(3) %addr, ptr addrspace(1) %use) {
; GFX1250-LABEL: ds_load_tr16_b128_v8bf16:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; GFX1250-NEXT: ds_load_tr16_b128 v[0:3], v0 offset:32
; GFX1250-NEXT: s_wait_dscnt 0x0

24
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.gfx1250.ll
View File

@ -5,6 +5,7 @@
define amdgpu_kernel void @v_permlane_bcast_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_bcast_b32_vss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
@ -22,6 +23,7 @@ define amdgpu_kernel void @v_permlane_bcast_b32_vss(ptr addrspace(1) %out, i32 %
define amdgpu_kernel void @v_permlane_bcast_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_bcast_b32_vii:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -37,6 +39,7 @@ define amdgpu_kernel void @v_permlane_bcast_b32_vii(ptr addrspace(1) %out, i32 %
define amdgpu_kernel void @v_permlane_bcast_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_bcast_b32_vll:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -53,6 +56,7 @@ define amdgpu_kernel void @v_permlane_bcast_b32_vll(ptr addrspace(1) %out, i32 %
define amdgpu_kernel void @v_permlane_bcast_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_bcast_b32_vvv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -69,6 +73,7 @@ define amdgpu_kernel void @v_permlane_bcast_b32_vvv(ptr addrspace(1) %out, i32 %
;
; GFX1250-GISEL-LABEL: v_permlane_bcast_b32_vvv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -92,6 +97,7 @@ define amdgpu_kernel void @v_permlane_bcast_b32_vvv(ptr addrspace(1) %out, i32 %
define amdgpu_kernel void @v_permlane_down_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_down_b32_vss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
@ -109,6 +115,7 @@ define amdgpu_kernel void @v_permlane_down_b32_vss(ptr addrspace(1) %out, i32 %s
define amdgpu_kernel void @v_permlane_down_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_down_b32_vii:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -124,6 +131,7 @@ define amdgpu_kernel void @v_permlane_down_b32_vii(ptr addrspace(1) %out, i32 %s
define amdgpu_kernel void @v_permlane_down_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_down_b32_vll:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -140,6 +148,7 @@ define amdgpu_kernel void @v_permlane_down_b32_vll(ptr addrspace(1) %out, i32 %s
define amdgpu_kernel void @v_permlane_down_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_down_b32_vvv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -156,6 +165,7 @@ define amdgpu_kernel void @v_permlane_down_b32_vvv(ptr addrspace(1) %out, i32 %s
;
; GFX1250-GISEL-LABEL: v_permlane_down_b32_vvv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -179,6 +189,7 @@ define amdgpu_kernel void @v_permlane_down_b32_vvv(ptr addrspace(1) %out, i32 %s
define amdgpu_kernel void @v_permlane_up_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_up_b32_vss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
@ -196,6 +207,7 @@ define amdgpu_kernel void @v_permlane_up_b32_vss(ptr addrspace(1) %out, i32 %src
define amdgpu_kernel void @v_permlane_up_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_up_b32_vii:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -211,6 +223,7 @@ define amdgpu_kernel void @v_permlane_up_b32_vii(ptr addrspace(1) %out, i32 %src
define amdgpu_kernel void @v_permlane_up_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_up_b32_vll:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -227,6 +240,7 @@ define amdgpu_kernel void @v_permlane_up_b32_vll(ptr addrspace(1) %out, i32 %src
define amdgpu_kernel void @v_permlane_up_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_up_b32_vvv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -243,6 +257,7 @@ define amdgpu_kernel void @v_permlane_up_b32_vvv(ptr addrspace(1) %out, i32 %src
;
; GFX1250-GISEL-LABEL: v_permlane_up_b32_vvv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -266,6 +281,7 @@ define amdgpu_kernel void @v_permlane_up_b32_vvv(ptr addrspace(1) %out, i32 %src
define amdgpu_kernel void @v_permlane_xor_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_xor_b32_vss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
@ -283,6 +299,7 @@ define amdgpu_kernel void @v_permlane_xor_b32_vss(ptr addrspace(1) %out, i32 %sr
define amdgpu_kernel void @v_permlane_xor_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_xor_b32_vii:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -298,6 +315,7 @@ define amdgpu_kernel void @v_permlane_xor_b32_vii(ptr addrspace(1) %out, i32 %sr
define amdgpu_kernel void @v_permlane_xor_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_xor_b32_vll:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -314,6 +332,7 @@ define amdgpu_kernel void @v_permlane_xor_b32_vll(ptr addrspace(1) %out, i32 %sr
define amdgpu_kernel void @v_permlane_xor_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_xor_b32_vvv:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -330,6 +349,7 @@ define amdgpu_kernel void @v_permlane_xor_b32_vvv(ptr addrspace(1) %out, i32 %sr
;
; GFX1250-GISEL-LABEL: v_permlane_xor_b32_vvv:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10
@ -353,6 +373,7 @@ define amdgpu_kernel void @v_permlane_xor_b32_vvv(ptr addrspace(1) %out, i32 %sr
define amdgpu_kernel void @v_permlane_idx_gen_b32_vs(ptr addrspace(1) %out, i32 %src0, i32 %src1) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -368,6 +389,7 @@ define amdgpu_kernel void @v_permlane_idx_gen_b32_vs(ptr addrspace(1) %out, i32
define amdgpu_kernel void @v_permlane_idx_gen_b32_vi(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vi:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -383,6 +405,7 @@ define amdgpu_kernel void @v_permlane_idx_gen_b32_vi(ptr addrspace(1) %out, i32
define amdgpu_kernel void @v_permlane_idx_gen_b32_vl(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vl:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
@ -398,6 +421,7 @@ define amdgpu_kernel void @v_permlane_idx_gen_b32_vl(ptr addrspace(1) %out, i32
define amdgpu_kernel void @v_permlane_idx_gen_b32_vv(ptr addrspace(1) %out) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: v_bfe_u32 v1, v0, 10, 10
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0

13
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
View File

@ -31,6 +31,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_i32(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -79,6 +80,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_i32_off(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_i32_off:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -126,6 +128,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_i32_soff(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_i32_soff:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -174,6 +177,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_i32_dlc(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_i32_dlc:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -223,6 +227,7 @@ define amdgpu_kernel void @raw_nonatomic_buffer_load_i32(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_nonatomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
@ -272,6 +277,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_i64(<4 x i32> %addr) {
;
; GFX12-SDAG-TRUE16-LABEL: raw_atomic_buffer_load_i64:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
@ -292,6 +298,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_i64(<4 x i32> %addr) {
;
; GFX12-GISEL-TRUE16-LABEL: raw_atomic_buffer_load_i64:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@ -342,6 +349,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_v2i16(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_v2i16:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -453,6 +461,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_v4i16(<4 x i32> %addr) {
;
; GFX12-SDAG-TRUE16-LABEL: raw_atomic_buffer_load_v4i16:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
@ -473,6 +482,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_v4i16(<4 x i32> %addr) {
;
; GFX12-FAKE16-LABEL: raw_atomic_buffer_load_v4i16:
; GFX12-FAKE16: ; %bb.0: ; %bb
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-FAKE16-NEXT: s_wait_xcnt 0x0
@ -495,6 +505,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_v4i16(<4 x i32> %addr) {
;
; GFX12-GISEL-TRUE16-LABEL: raw_atomic_buffer_load_v4i16:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
@ -546,6 +557,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_v4i32(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_v4i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -597,6 +609,7 @@ define amdgpu_kernel void @raw_atomic_buffer_load_ptr(<4 x i32> %addr) {
;
; GFX12-LABEL: raw_atomic_buffer_load_ptr:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0

336
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
View File

@ -5,8 +5,8 @@
; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefixes=GFX910,GFX9
; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefixes=GFX910,GFX10
; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX11
; RUN: llc -mcpu=gfx1200 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -mcpu=gfx1250 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -mcpu=gfx1200 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX1200
; RUN: llc -mcpu=gfx1250 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX1250
define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %data_addr, ptr addrspace(1) %tfe_addr) {
; GFX67-LABEL: raw_buffer_load_i8_tfe:
@ -54,16 +54,28 @@ define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_i8_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_u8 v[4:5], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b8 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_i8_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_u8 v[4:5], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b8 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_i8_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_u8 v[4:5], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b8 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { i8, i32 } @llvm.amdgcn.raw.buffer.load.sl_i8i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { i8, i32 } %res, 0
store i8 %data, ptr addrspace(1) %data_addr
@ -118,16 +130,28 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_i16_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_u16 v[4:5], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b16 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_i16_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_u16 v[4:5], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b16 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_i16_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_u16 v[4:5], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b16 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { i16, i32 } @llvm.amdgcn.raw.buffer.load.sl_i16i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { i16, i32 } %res, 0
store i16 %data, ptr addrspace(1) %data_addr
@ -182,16 +206,28 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_f16_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_u16 v[4:5], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b16 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_f16_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_u16 v[4:5], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b16 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_f16_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_u16 v[4:5], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b16 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { half, i32 } @llvm.amdgcn.raw.buffer.load.sl_f16i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { half, i32 } %res, 0
store half %data, ptr addrspace(1) %data_addr
@ -246,16 +282,28 @@ define amdgpu_ps void @raw_buffer_load_i32_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_b32 v[4:5], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b32 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_b32 v[4:5], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b32 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_b32 v[4:5], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b32 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { i32, i32 } @llvm.amdgcn.raw.buffer.load.sl_i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { i32, i32 } %res, 0
store i32 %data, ptr addrspace(1) %data_addr
@ -330,16 +378,28 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v6, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_v2i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: buffer_load_b64 v[4:6], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX12-NEXT: global_store_b32 v[2:3], v6, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_v2i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: buffer_load_b64 v[4:6], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1200-NEXT: global_store_b32 v[2:3], v6, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_v2i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: buffer_load_b64 v[4:6], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1250-NEXT: global_store_b32 v[2:3], v6, off
; GFX1250-NEXT: s_endpgm
%res = call { <2 x i32>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { <2 x i32>, i32 } %res, 0
store <2 x i32> %data, ptr addrspace(1) %data_addr
@ -414,16 +474,28 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v6, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_v2f32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: buffer_load_b64 v[4:6], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX12-NEXT: global_store_b32 v[2:3], v6, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_v2f32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: buffer_load_b64 v[4:6], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1200-NEXT: global_store_b32 v[2:3], v6, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_v2f32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: buffer_load_b64 v[4:6], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1250-NEXT: global_store_b32 v[2:3], v6, off
; GFX1250-NEXT: s_endpgm
%res = call { <2 x float>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { <2 x float>, i32 } %res, 0
store <2 x float> %data, ptr addrspace(1) %data_addr
@ -503,17 +575,30 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v7, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_v3i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v7, v4
; GFX12-NEXT: buffer_load_b96 v[4:7], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX12-NEXT: global_store_b32 v[2:3], v7, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_v3i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-NEXT: buffer_load_b96 v[4:7], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1200-NEXT: global_store_b32 v[2:3], v7, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_v3i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-NEXT: buffer_load_b96 v[4:7], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1250-NEXT: global_store_b32 v[2:3], v7, off
; GFX1250-NEXT: s_endpgm
%res = call { <3 x i32>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { <3 x i32>, i32 } %res, 0
store <3 x i32> %data, ptr addrspace(1) %data_addr
@ -593,17 +678,30 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v7, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_v3f32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v7, v4
; GFX12-NEXT: buffer_load_b96 v[4:7], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX12-NEXT: global_store_b32 v[2:3], v7, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_v3f32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-NEXT: buffer_load_b96 v[4:7], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1200-NEXT: global_store_b32 v[2:3], v7, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_v3f32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-NEXT: buffer_load_b96 v[4:7], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1250-NEXT: global_store_b32 v[2:3], v7, off
; GFX1250-NEXT: s_endpgm
%res = call { <3 x float>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { <3 x float>, i32 } %res, 0
store <3 x float> %data, ptr addrspace(1) %data_addr
@ -670,17 +768,30 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v8, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_v4i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX12-NEXT: buffer_load_b128 v[4:8], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX12-NEXT: global_store_b32 v[2:3], v8, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_v4i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1200-NEXT: buffer_load_b128 v[4:8], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1200-NEXT: global_store_b32 v[2:3], v8, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_v4i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1250-NEXT: buffer_load_b128 v[4:8], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1250-NEXT: global_store_b32 v[2:3], v8, off
; GFX1250-NEXT: s_endpgm
%res = call { <4 x i32>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { <4 x i32>, i32 } %res, 0
store <4 x i32> %data, ptr addrspace(1) %data_addr
@ -747,17 +858,30 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v8, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: raw_buffer_load_v4f32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX12-NEXT: buffer_load_b128 v[4:8], off, s[0:3], null tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX12-NEXT: global_store_b32 v[2:3], v8, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: raw_buffer_load_v4f32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1200-NEXT: buffer_load_b128 v[4:8], off, s[0:3], null tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1200-NEXT: global_store_b32 v[2:3], v8, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_load_v4f32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1250-NEXT: buffer_load_b128 v[4:8], off, s[0:3], null tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1250-NEXT: global_store_b32 v[2:3], v8, off
; GFX1250-NEXT: s_endpgm
%res = call { <4 x float>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%data = extractvalue { <4 x float>, i32 } %res, 0
store <4 x float> %data, ptr addrspace(1) %data_addr

389
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
View File

@ -2,8 +2,8 @@
; RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefixes=GFX68,VERDE %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=GFX68,GFX8 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck -check-prefixes=GFX11 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GFX12 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 | FileCheck -check-prefixes=GFX12 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck -check-prefixes=GFX1200 %s
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 | FileCheck -check-prefixes=GFX1250 %s
define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
; GFX68-LABEL: buffer_store:
@ -20,6 +20,23 @@ define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <
; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 glc
; GFX11-NEXT: buffer_store_b128 v[8:11], off, s[0:3], 0 slc
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: s_clause 0x2
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX1200-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null th:TH_STORE_NT
; GFX1200-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null th:TH_STORE_HT
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x2
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX1250-NEXT: buffer_store_b128 v[4:7], off, s[0:3], null th:TH_STORE_NT
; GFX1250-NEXT: buffer_store_b128 v[8:11], off, s[0:3], null th:TH_STORE_HT
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 1)
@ -37,6 +54,17 @@ define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:42
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_immoffs:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:42
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_immoffs:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:42
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)
ret void
@ -52,6 +80,17 @@ define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_ofs:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_ofs:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0)
ret void
@ -83,6 +122,24 @@ define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32,
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_wait:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen
; GFX1200-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], null offen
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_wait:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen
; GFX1250-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], null offen
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0)
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0)
@ -100,6 +157,17 @@ define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x1:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x1:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)
ret void
@ -115,6 +183,17 @@ define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data,
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x2:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x2:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)
ret void
@ -133,6 +212,28 @@ define amdgpu_ps void @buffer_store_x1_offen_merged_and(<4 x i32> inreg %rsrc, i
; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], 0 offen offset:28
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x1_offen_merged_and:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_clause 0x1
; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4
; GFX1200-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], null offen offset:28
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x1_offen_merged_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_add_nc_u32 v7, 4, v0 :: v_dual_add_nc_u32 v8, 8, v0
; GFX1250-NEXT: v_dual_add_nc_u32 v9, 12, v0 :: v_dual_add_nc_u32 v10, 16, v0
; GFX1250-NEXT: v_dual_add_nc_u32 v11, 28, v0 :: v_dual_add_nc_u32 v0, 32, v0
; GFX1250-NEXT: s_clause 0x5
; GFX1250-NEXT: buffer_store_b32 v1, v7, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v2, v8, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v3, v9, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v4, v10, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v5, v11, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v6, v0, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
%a1 = add i32 %a, 4
%a2 = add i32 %a, 8
%a3 = add i32 %a, 12
@ -163,6 +264,26 @@ define amdgpu_ps void @buffer_store_x1_offen_merged_or(<4 x i32> inreg %rsrc, i3
; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], 0 offen offset:28
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x1_offen_merged_or:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_lshlrev_b32_e32 v0, 6, v0
; GFX1200-NEXT: s_clause 0x1
; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4
; GFX1200-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], null offen offset:28
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x1_offen_merged_or:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v6, v5
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 6, v0
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: buffer_store_b128 v[2:5], v0, s[0:3], null offen offset:4
; GFX1250-NEXT: buffer_store_b64 v[6:7], v0, s[0:3], null offen offset:28
; GFX1250-NEXT: s_endpgm
%a = shl i32 %inp, 6
%a1 = add i32 %a, 4
%a2 = add i32 %a, 8
@ -194,6 +315,29 @@ define amdgpu_ps void @buffer_store_x1_offen_merged_glc_slc(<4 x i32> inreg %rsr
; GFX11-NEXT: buffer_store_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc
; GFX11-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x1_offen_merged_glc_slc:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_clause 0x2
; GFX1200-NEXT: buffer_store_b64 v[1:2], v0, s[0:3], null offen offset:4
; GFX1200-NEXT: buffer_store_b64 v[3:4], v0, s[0:3], null offen offset:12 th:TH_STORE_NT
; GFX1200-NEXT: buffer_store_b64 v[5:6], v0, s[0:3], null offen offset:28 th:TH_STORE_WB
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x1_offen_merged_glc_slc:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_add_nc_u32 v7, 4, v0 :: v_dual_add_nc_u32 v8, 8, v0
; GFX1250-NEXT: v_dual_add_nc_u32 v9, 12, v0 :: v_dual_add_nc_u32 v10, 16, v0
; GFX1250-NEXT: v_dual_add_nc_u32 v11, 28, v0 :: v_dual_add_nc_u32 v0, 32, v0
; GFX1250-NEXT: s_clause 0x5
; GFX1250-NEXT: buffer_store_b32 v1, v7, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v2, v8, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b32 v3, v9, s[0:3], null offen th:TH_STORE_NT
; GFX1250-NEXT: buffer_store_b32 v4, v10, s[0:3], null offen th:TH_STORE_NT
; GFX1250-NEXT: buffer_store_b32 v5, v11, s[0:3], null offen th:TH_STORE_WB
; GFX1250-NEXT: buffer_store_b32 v6, v0, s[0:3], null offen th:TH_STORE_WB
; GFX1250-NEXT: s_endpgm
%a1 = add i32 %a, 4
%a2 = add i32 %a, 8
%a3 = add i32 %a, 12
@ -219,6 +363,22 @@ define amdgpu_ps void @buffer_store_x2_offen_merged_and(<4 x i32> inreg %rsrc, i
; GFX11: ; %bb.0:
; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x2_offen_merged_and:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x2_offen_merged_and:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_dual_add_nc_u32 v1, 4, v0 :: v_dual_add_nc_u32 v0, 12, v0
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: buffer_store_b64 v[2:3], v1, s[0:3], null offen
; GFX1250-NEXT: buffer_store_b64 v[4:5], v0, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
%a1 = add i32 %a, 4
%a2 = add i32 %a, 12
call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
@ -238,6 +398,21 @@ define amdgpu_ps void @buffer_store_x2_offen_merged_or(<4 x i32> inreg %rsrc, i3
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX11-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x2_offen_merged_or:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX1200-NEXT: buffer_store_b128 v[1:4], v0, s[0:3], null offen offset:4
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x2_offen_merged_or:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX1250-NEXT: buffer_store_b128 v[2:5], v0, s[0:3], null offen offset:4
; GFX1250-NEXT: s_endpgm
%a = shl i32 %inp, 4
%a1 = add i32 %a, 4
%a2 = add i32 %a, 12
@ -259,6 +434,21 @@ define amdgpu_ps void @buffer_store_x1_offset_merged(<4 x i32> inreg %rsrc, floa
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 offset:28
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x1_offset_merged:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_clause 0x1
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4
; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x1_offset_merged:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4
; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28
; GFX1250-NEXT: s_endpgm
call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 0)
@ -278,6 +468,17 @@ define amdgpu_ps void @buffer_store_x2_offset_merged(<4 x i32> inreg %rsrc, <2 x
; GFX11: ; %bb.0:
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_x2_offset_merged:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_x2_offset_merged:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4
; GFX1250-NEXT: s_endpgm
call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 12, i32 0, i32 0)
ret void
@ -298,6 +499,23 @@ define amdgpu_ps void @buffer_store_int(<4 x i32> inreg, <4 x i32>, <2 x i32>, i
; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 glc
; GFX11-NEXT: buffer_store_b32 v6, off, s[0:3], 0 slc
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_int:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: s_clause 0x2
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null th:TH_STORE_NT
; GFX1200-NEXT: buffer_store_b32 v6, off, s[0:3], null th:TH_STORE_HT
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_int:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x2
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null th:TH_STORE_NT
; GFX1250-NEXT: buffer_store_b32 v6, off, s[0:3], null th:TH_STORE_HT
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> %1, <4 x i32> %0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %2, <4 x i32> %0, i32 0, i32 0, i32 1)
@ -317,6 +535,19 @@ define amdgpu_ps void @raw_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1) {
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: buffer_store_b8 v0, off, s[0:3], 0
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_byte:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX1200-NEXT: buffer_store_b8 v0, off, s[0:3], null
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_byte:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX1250-NEXT: buffer_store_b8 v0, off, s[0:3], null
; GFX1250-NEXT: s_endpgm
main_body:
%v2 = fptoui float %v1 to i32
%v3 = trunc i32 %v2 to i8
@ -336,6 +567,19 @@ define amdgpu_ps void @raw_buffer_store_short(<4 x i32> inreg %rsrc, float %v1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_short:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX1200-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_short:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX1250-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-NEXT: s_endpgm
main_body:
%v2 = fptoui float %v1 to i32
%v3 = trunc i32 %v2 to i16
@ -353,6 +597,17 @@ define amdgpu_ps void @raw_buffer_store_f16(<4 x i32> inreg %rsrc, i32 %v1) {
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_f16:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_f16:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-NEXT: s_endpgm
main_body:
%trunc = trunc i32 %v1 to i16
%cast = bitcast i16 %trunc to half
@ -379,6 +634,17 @@ define amdgpu_ps void @buffer_store_v2f16(<4 x i32> inreg %rsrc, <2 x half> %dat
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_v2f16:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_v2f16:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)
ret void
@ -407,6 +673,17 @@ define amdgpu_ps void @buffer_store_v4f16(<4 x i32> inreg %rsrc, <4 x half> %dat
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_v4f16:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_v4f16:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)
ret void
@ -422,6 +699,17 @@ define amdgpu_ps void @raw_buffer_store_i16(<4 x i32> inreg %rsrc, i32 %v1) {
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_i16:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_i16:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-NEXT: s_endpgm
main_body:
%trunc = trunc i32 %v1 to i16
call void @llvm.amdgcn.raw.buffer.store.i16(i16 %trunc, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
@ -446,6 +734,17 @@ define amdgpu_ps void @buffer_store_v2i16(<4 x i32> inreg %rsrc, <2 x i16> %data
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_v2i16:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_v2i16:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v2i16(<2 x i16> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)
ret void
@ -472,6 +771,17 @@ define amdgpu_ps void @buffer_store_v4i16(<4 x i32> inreg %rsrc, <4 x i16> %data
; GFX11: ; %bb.0: ; %main_body
; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: buffer_store_v4i16:
; GFX1200: ; %bb.0: ; %main_body
; GFX1200-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: buffer_store_v4i16:
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX1250-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.buffer.store.v4i16(<4 x i16> %data, <4 x i32> %rsrc, i32 %offset, i32 0, i32 0)
ret void
@ -490,6 +800,21 @@ define amdgpu_ps void @raw_buffer_store_x1_offset_merged(<4 x i32> inreg %rsrc,
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 offset:28
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_x1_offset_merged:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_clause 0x1
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4
; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_x1_offset_merged:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4
; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28
; GFX1250-NEXT: s_endpgm
call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 0)
@ -520,6 +845,21 @@ define amdgpu_ps void @raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12(<
; GFX11-NEXT: buffer_store_b32 v4, off, s[0:3], 0 offset:28
; GFX11-NEXT: buffer_store_b32 v5, off, s[0:3], 0 offset:32
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_clause 0x1
; GFX1200-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4 scope:SCOPE_SE
; GFX1200-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28 scope:SCOPE_SE
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null offset:4 scope:SCOPE_SE
; GFX1250-NEXT: buffer_store_b64 v[4:5], off, s[0:3], null offset:28 scope:SCOPE_SE
; GFX1250-NEXT: s_endpgm
call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 8)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 8)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 8)
@ -530,16 +870,41 @@ define amdgpu_ps void @raw_buffer_store_x1_offset_swizzled_not_merged_pregfx12(<
}
define amdgpu_ps void @raw_buffer_store_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
; GFX12-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: buffer_store_b32 v0, off, s[0:3], null offset:4
; GFX12-NEXT: buffer_store_b32 v1, off, s[0:3], null offset:8
; GFX12-NEXT: buffer_store_b32 v2, off, s[0:3], null offset:12
; GFX12-NEXT: buffer_store_b32 v3, off, s[0:3], null offset:16
; GFX12-NEXT: buffer_store_b32 v4, off, s[0:3], null offset:28
; GFX12-NEXT: buffer_store_b32 v5, off, s[0:3], null offset:32
; GFX12-NEXT: s_endpgm
; GFX68-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:
; GFX68: ; %bb.0:
; GFX68-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; GFX68-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:28
; GFX68-NEXT: s_endpgm
;
; GFX11-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT: buffer_store_b64 v[4:5], off, s[0:3], 0 offset:28
; GFX11-NEXT: s_endpgm
;
; GFX1200-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: s_clause 0x5
; GFX1200-NEXT: buffer_store_b32 v0, off, s[0:3], null offset:4
; GFX1200-NEXT: buffer_store_b32 v1, off, s[0:3], null offset:8
; GFX1200-NEXT: buffer_store_b32 v2, off, s[0:3], null offset:12
; GFX1200-NEXT: buffer_store_b32 v3, off, s[0:3], null offset:16
; GFX1200-NEXT: buffer_store_b32 v4, off, s[0:3], null offset:28
; GFX1200-NEXT: buffer_store_b32 v5, off, s[0:3], null offset:32
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: raw_buffer_store_x1_offset_swizzled_not_merged:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x5
; GFX1250-NEXT: buffer_store_b32 v0, off, s[0:3], null offset:4
; GFX1250-NEXT: buffer_store_b32 v1, off, s[0:3], null offset:8
; GFX1250-NEXT: buffer_store_b32 v2, off, s[0:3], null offset:12
; GFX1250-NEXT: buffer_store_b32 v3, off, s[0:3], null offset:16
; GFX1250-NEXT: buffer_store_b32 v4, off, s[0:3], null offset:28
; GFX1250-NEXT: buffer_store_b32 v5, off, s[0:3], null offset:32
; GFX1250-NEXT: s_endpgm
call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 4, i32 0, i32 64)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 8, i32 0, i32 64)
call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 12, i32 0, i32 64)

13
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
View File

@ -31,6 +31,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_ptr_load_i32(ptr addrspace(8) %
;
; GFX12-LABEL: raw_ptr_atomic_buffer_ptr_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -79,6 +80,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i32_off(ptr addrspace(8) %
;
; GFX12-LABEL: raw_ptr_atomic_buffer_load_i32_off:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -126,6 +128,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i32_soff(ptr addrspace(8)
;
; GFX12-LABEL: raw_ptr_atomic_buffer_load_i32_soff:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -174,6 +177,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i32_dlc(ptr addrspace(8) %
;
; GFX12-LABEL: raw_ptr_atomic_buffer_load_i32_dlc:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -223,6 +227,7 @@ define amdgpu_kernel void @raw_nonptr_atomic_buffer_load_i32(ptr addrspace(8) %p
;
; GFX12-LABEL: raw_nonptr_atomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
@ -272,6 +277,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i64(ptr addrspace(8) %ptr)
;
; GFX12-SDAG-TRUE16-LABEL: raw_ptr_atomic_buffer_load_i64:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
@ -292,6 +298,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_i64(ptr addrspace(8) %ptr)
;
; GFX12-GISEL-TRUE16-LABEL: raw_ptr_atomic_buffer_load_i64:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@ -342,6 +349,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v2i16(ptr addrspace(8) %pt
;
; GFX12-LABEL: raw_ptr_atomic_buffer_load_v2i16:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -453,6 +461,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i16(ptr addrspace(8) %pt
;
; GFX12-SDAG-TRUE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
@ -473,6 +482,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i16(ptr addrspace(8) %pt
;
; GFX12-FAKE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
; GFX12-FAKE16: ; %bb.0: ; %bb
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-FAKE16-NEXT: s_wait_xcnt 0x0
@ -495,6 +505,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i16(ptr addrspace(8) %pt
;
; GFX12-GISEL-TRUE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
@ -546,6 +557,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i32(ptr addrspace(8) %pt
;
; GFX12-LABEL: raw_ptr_atomic_buffer_load_v4i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0
@ -597,6 +609,7 @@ define amdgpu_kernel void @raw_ptr_atomic_buffer_load_ptr(ptr addrspace(8) %ptr)
;
; GFX12-LABEL: raw_ptr_atomic_buffer_load_ptr:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: s_wait_xcnt 0x0

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
View File

@ -36,6 +36,7 @@ define amdgpu_ps void @buffer_store_bf16(ptr addrspace(8) inreg %rsrc, bfloat %d
;
; GFX12-LABEL: buffer_store_bf16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b16 v0, v1, s[0:3], null offen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.raw.ptr.buffer.store.bf16(bfloat %data, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)
@ -74,6 +75,7 @@ define amdgpu_ps void @buffer_store_v2bf16(ptr addrspace(8) inreg %rsrc, <2 x bf
;
; GFX12-LABEL: buffer_store_v2bf16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.raw.ptr.buffer.store.v2bf16(<2 x bfloat> %data, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)
@ -116,6 +118,7 @@ define amdgpu_ps void @buffer_store_v4bf16(ptr addrspace(8) inreg %rsrc, <4 x bf
;
; GFX12-LABEL: buffer_store_v4bf16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null offen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.raw.ptr.buffer.store.v4bf16(<4 x bfloat> %data, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)
@ -172,6 +175,7 @@ define amdgpu_ps void @buffer_store_v8bf16(ptr addrspace(8) inreg %rsrc, <8 x bf
;
; GFX12-LABEL: buffer_store_v8bf16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null offen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.raw.ptr.buffer.store.v8bf16(<8 x bfloat> %data, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)

8
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
View File

@ -11,6 +11,7 @@ declare bfloat @llvm.amdgcn.rcp.bf16(bfloat) #0
define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; SDAG-TRUE16-LABEL: rcp_bf16:
; SDAG-TRUE16: ; %bb.0:
; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
@ -20,6 +21,7 @@ define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; SDAG-FAKE16-LABEL: rcp_bf16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -34,6 +36,7 @@ define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
; SDAG-TRUE16-LABEL: rcp_bf16_constant_4:
; SDAG-TRUE16: ; %bb.0:
; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3e80
@ -43,6 +46,7 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: rcp_bf16_constant_4:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3e80
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -56,6 +60,7 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 {
; SDAG-TRUE16-LABEL: rcp_bf16_constant_100:
; SDAG-TRUE16: ; %bb.0:
; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c24
@ -65,6 +70,7 @@ define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: rcp_bf16_constant_100:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3c24
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -78,6 +84,7 @@ define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @rcp_undef_bf16(ptr addrspace(1) %out) #1 {
; SDAG-TRUE16-LABEL: rcp_undef_bf16:
; SDAG-TRUE16: ; %bb.0:
; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7fc0
@ -87,6 +94,7 @@ define amdgpu_kernel void @rcp_undef_bf16(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: rcp_undef_bf16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7fc0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0

8
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
View File

@ -11,6 +11,7 @@ declare bfloat @llvm.amdgcn.rsq.bf16(bfloat) #0
define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; SDAG-REAL16-LABEL: rsq_bf16:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
@ -20,6 +21,7 @@ define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; SDAG-FAKE16-LABEL: rsq_bf16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -34,6 +36,7 @@ define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: rsq_bf16_constant_4:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 4.0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -43,6 +46,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: rsq_bf16_constant_4:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_rsq_bf16_e32 v0, 4.0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -57,6 +61,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: rsq_bf16_constant_100:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 0x42c8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -66,6 +71,7 @@ define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: rsq_bf16_constant_100:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_rsq_bf16_e32 v0, 0x42c8
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -80,10 +86,12 @@ define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @rsq_undef_bf16(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: rsq_undef_bf16:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: rsq_undef_bf16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_endpgm
%rsq = call bfloat @llvm.amdgcn.rsq.bf16(bfloat undef)
store bfloat %rsq, ptr addrspace(1) %out, align 2

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
View File

@ -5,6 +5,7 @@
define amdgpu_ps void @test_asynccnt() {
; GFX12-LABEL: test_asynccnt:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_wait_asynccnt 0x0
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.s.wait.asynccnt(i16 0)
@ -14,6 +15,7 @@ define amdgpu_ps void @test_asynccnt() {
define amdgpu_ps void @test_tensorcnt() {
; GFX12-LABEL: test_tensorcnt:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_wait_tensorcnt 0x0
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.s.wait.tensorcnt(i16 0)

13
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
View File

@ -25,6 +25,7 @@ define amdgpu_kernel void @test_get_doorbell(ptr addrspace(1) %out) {
;
; GFX1250-SDAG-LABEL: test_get_doorbell:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DOORBELL)
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -34,6 +35,7 @@ define amdgpu_kernel void @test_get_doorbell(ptr addrspace(1) %out) {
;
; GFX1250-GISEL-LABEL: test_get_doorbell:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DOORBELL)
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
@ -66,6 +68,7 @@ define amdgpu_kernel void @test_get_ddid(ptr addrspace(1) %out) {
;
; GFX1250-SDAG-LABEL: test_get_ddid:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DDID)
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -75,6 +78,7 @@ define amdgpu_kernel void @test_get_ddid(ptr addrspace(1) %out) {
;
; GFX1250-GISEL-LABEL: test_get_ddid:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_GET_DDID)
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
@ -99,6 +103,7 @@ define amdgpu_kernel void @test_get_tma(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: test_get_tma:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TMA)
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -124,6 +129,7 @@ define amdgpu_kernel void @test_get_realtime(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: test_get_realtime:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -157,6 +163,7 @@ define amdgpu_kernel void @test_savewave(ptr addrspace(1) %out) {
;
; GFX1250-SDAG-LABEL: test_savewave:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_SAVE_WAVE)
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -166,6 +173,7 @@ define amdgpu_kernel void @test_savewave(ptr addrspace(1) %out) {
;
; GFX1250-GISEL-LABEL: test_savewave:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(MSG_RTN_SAVE_WAVE)
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
@ -190,6 +198,7 @@ define amdgpu_kernel void @test_get_tba(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: test_get_tba:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TBA)
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -223,6 +232,7 @@ define amdgpu_kernel void @test_get_0_i32(ptr addrspace(1) %out) {
;
; GFX1250-SDAG-LABEL: test_get_0_i32:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-SDAG-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(0, 0, 0)
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
@ -232,6 +242,7 @@ define amdgpu_kernel void @test_get_0_i32(ptr addrspace(1) %out) {
;
; GFX1250-GISEL-LABEL: test_get_0_i32:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-GISEL-NEXT: s_sendmsg_rtn_b32 s2, sendmsg(0, 0, 0)
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
@ -256,6 +267,7 @@ define amdgpu_kernel void @test_get_99999_i64(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: test_get_99999_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], 99999
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
@ -281,6 +293,7 @@ define amdgpu_kernel void @test_get_136_i64(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: test_get_136_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE)
; GFX1250-NEXT: v_mov_b32_e32 v2, 0

14
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
View File

@ -34,6 +34,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i32(<4 x i32> %addr, i32 %i
;
; GFX12-LABEL: struct_atomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -85,6 +86,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i32_const_idx(<4 x i32> %ad
;
; GFX12-LABEL: struct_atomic_buffer_load_i32_const_idx:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: v_mov_b32_e32 v1, 15
@ -137,6 +139,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i32_off(<4 x i32> %addr, i3
;
; GFX12-LABEL: struct_atomic_buffer_load_i32_off:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -191,6 +194,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i32_soff(<4 x i32> %addr, i
;
; GFX12-LABEL: struct_atomic_buffer_load_i32_soff:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -245,6 +249,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i32_dlc(<4 x i32> %addr, i3
;
; GFX12-LABEL: struct_atomic_buffer_load_i32_dlc:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -299,6 +304,7 @@ define amdgpu_kernel void @struct_nonatomic_buffer_load_i32(<4 x i32> %addr, i32
;
; GFX12-LABEL: struct_nonatomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -354,6 +360,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i64(<4 x i32> %addr, i32 %i
;
; GFX12-SDAG-TRUE16-LABEL: struct_atomic_buffer_load_i64:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX12-SDAG-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -377,6 +384,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_i64(<4 x i32> %addr, i32 %i
;
; GFX12-GISEL-TRUE16-LABEL: struct_atomic_buffer_load_i64:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_clause 0x1
; GFX12-GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -433,6 +441,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_v2i16(<4 x i32> %addr, i32
;
; GFX12-LABEL: struct_atomic_buffer_load_v2i16:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -559,6 +568,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_v4i16(<4 x i32> %addr, i32
;
; GFX12-SDAG-TRUE16-LABEL: struct_atomic_buffer_load_v4i16:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX12-SDAG-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -582,6 +592,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_v4i16(<4 x i32> %addr, i32
;
; GFX12-FAKE16-LABEL: struct_atomic_buffer_load_v4i16:
; GFX12-FAKE16: ; %bb.0: ; %bb
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -607,6 +618,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_v4i16(<4 x i32> %addr, i32
;
; GFX12-GISEL-TRUE16-LABEL: struct_atomic_buffer_load_v4i16:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_clause 0x1
; GFX12-GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -664,6 +676,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_v4i32(<4 x i32> %addr, i32
;
; GFX12-LABEL: struct_atomic_buffer_load_v4i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -721,6 +734,7 @@ define amdgpu_kernel void @struct_atomic_buffer_load_ptr(<4 x i32> %addr, i32 %i
;
; GFX12-LABEL: struct_atomic_buffer_load_ptr:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24

336
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
View File

@ -5,8 +5,8 @@
; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefixes=GFX910,GFX9
; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefixes=GFX910,GFX10
; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX11
; RUN: llc -mcpu=gfx1200 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -mcpu=gfx1250 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX12
; RUN: llc -mcpu=gfx1200 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX1200
; RUN: llc -mcpu=gfx1250 -mtriple=amdgcn-- < %s | FileCheck %s -check-prefix=GFX1250
define amdgpu_ps void @struct_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %data_addr, ptr addrspace(1) %tfe_addr) {
; GFX67-LABEL: struct_buffer_load_i8_tfe:
@ -54,16 +54,28 @@ define amdgpu_ps void @struct_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_i8_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_u8 v[4:5], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b8 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_i8_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_u8 v[4:5], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b8 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_i8_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_u8 v[4:5], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b8 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { i8, i32 } @llvm.amdgcn.struct.buffer.load.sl_i8i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { i8, i32 } %res, 0
store i8 %data, ptr addrspace(1) %data_addr
@ -118,16 +130,28 @@ define amdgpu_ps void @struct_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr add
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_i16_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_u16 v[4:5], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b16 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_i16_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_u16 v[4:5], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b16 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_i16_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_u16 v[4:5], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b16 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { i16, i32 } @llvm.amdgcn.struct.buffer.load.sl_i16i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { i16, i32 } %res, 0
store i16 %data, ptr addrspace(1) %data_addr
@ -182,16 +206,28 @@ define amdgpu_ps void @struct_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr add
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_f16_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_u16 v[4:5], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b16 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_f16_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_u16 v[4:5], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b16 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_f16_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_u16 v[4:5], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b16 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { half, i32 } @llvm.amdgcn.struct.buffer.load.sl_f16i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { half, i32 } %res, 0
store half %data, ptr addrspace(1) %data_addr
@ -246,16 +282,28 @@ define amdgpu_ps void @struct_buffer_load_i32_tfe(<4 x i32> inreg %rsrc, ptr add
; GFX11-NEXT: global_store_b32 v[2:3], v5, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v5, v4
; GFX12-NEXT: buffer_load_b32 v[4:5], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b32 v[0:1], v4, off
; GFX12-NEXT: global_store_b32 v[2:3], v5, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v4
; GFX1200-NEXT: buffer_load_b32 v[4:5], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b32 v[0:1], v4, off
; GFX1200-NEXT: global_store_b32 v[2:3], v5, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_mov_b32_e32 v5, v4
; GFX1250-NEXT: buffer_load_b32 v[4:5], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b32 v[0:1], v4, off
; GFX1250-NEXT: global_store_b32 v[2:3], v5, off
; GFX1250-NEXT: s_endpgm
%res = call { i32, i32 } @llvm.amdgcn.struct.buffer.load.sl_i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { i32, i32 } %res, 0
store i32 %data, ptr addrspace(1) %data_addr
@ -330,16 +378,28 @@ define amdgpu_ps void @struct_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v[2:3], v6, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_v2i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: buffer_load_b64 v[4:6], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX12-NEXT: global_store_b32 v[2:3], v6, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_v2i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: buffer_load_b64 v[4:6], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1200-NEXT: global_store_b32 v[2:3], v6, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_v2i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: buffer_load_b64 v[4:6], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1250-NEXT: global_store_b32 v[2:3], v6, off
; GFX1250-NEXT: s_endpgm
%res = call { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <2 x i32>, i32 } %res, 0
store <2 x i32> %data, ptr addrspace(1) %data_addr
@ -414,16 +474,28 @@ define amdgpu_ps void @struct_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v[2:3], v6, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_v2f32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: buffer_load_b64 v[4:6], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX12-NEXT: global_store_b32 v[2:3], v6, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_v2f32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: buffer_load_b64 v[4:6], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1200-NEXT: global_store_b32 v[2:3], v6, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_v2f32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: buffer_load_b64 v[4:6], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b64 v[0:1], v[4:5], off
; GFX1250-NEXT: global_store_b32 v[2:3], v6, off
; GFX1250-NEXT: s_endpgm
%res = call { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <2 x float>, i32 } %res, 0
store <2 x float> %data, ptr addrspace(1) %data_addr
@ -503,17 +575,30 @@ define amdgpu_ps void @struct_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v[2:3], v7, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_v3i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v7, v4
; GFX12-NEXT: buffer_load_b96 v[4:7], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX12-NEXT: global_store_b32 v[2:3], v7, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_v3i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-NEXT: buffer_load_b96 v[4:7], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1200-NEXT: global_store_b32 v[2:3], v7, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_v3i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-NEXT: buffer_load_b96 v[4:7], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1250-NEXT: global_store_b32 v[2:3], v7, off
; GFX1250-NEXT: s_endpgm
%res = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <3 x i32>, i32 } %res, 0
store <3 x i32> %data, ptr addrspace(1) %data_addr
@ -593,17 +678,30 @@ define amdgpu_ps void @struct_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v[2:3], v7, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_v3f32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v7, v4
; GFX12-NEXT: buffer_load_b96 v[4:7], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX12-NEXT: global_store_b32 v[2:3], v7, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_v3f32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-NEXT: buffer_load_b96 v[4:7], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1200-NEXT: global_store_b32 v[2:3], v7, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_v3f32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_mov_b32_e32 v7, v4
; GFX1250-NEXT: buffer_load_b96 v[4:7], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b96 v[0:1], v[4:6], off
; GFX1250-NEXT: global_store_b32 v[2:3], v7, off
; GFX1250-NEXT: s_endpgm
%res = call { <3 x float>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <3 x float>, i32 } %res, 0
store <3 x float> %data, ptr addrspace(1) %data_addr
@ -670,17 +768,30 @@ define amdgpu_ps void @struct_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v[2:3], v8, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_v4i32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX12-NEXT: buffer_load_b128 v[4:8], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX12-NEXT: global_store_b32 v[2:3], v8, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_v4i32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1200-NEXT: buffer_load_b128 v[4:8], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1200-NEXT: global_store_b32 v[2:3], v8, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_v4i32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1250-NEXT: buffer_load_b128 v[4:8], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1250-NEXT: global_store_b32 v[2:3], v8, off
; GFX1250-NEXT: s_endpgm
%res = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <4 x i32>, i32 } %res, 0
store <4 x i32> %data, ptr addrspace(1) %data_addr
@ -747,17 +858,30 @@ define amdgpu_ps void @struct_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr a
; GFX11-NEXT: global_store_b32 v[2:3], v8, off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: struct_buffer_load_v4f32_tfe:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX12-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX12-NEXT: buffer_load_b128 v[4:8], v4, s[0:3], null idxen tfe
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX12-NEXT: global_store_b32 v[2:3], v8, off
; GFX12-NEXT: s_endpgm
; GFX1200-LABEL: struct_buffer_load_v4f32_tfe:
; GFX1200: ; %bb.0:
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1200-NEXT: buffer_load_b128 v[4:8], v4, s[0:3], null idxen tfe
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1200-NEXT: global_store_b32 v[2:3], v8, off
; GFX1200-NEXT: s_endpgm
;
; GFX1250-LABEL: struct_buffer_load_v4f32_tfe:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4
; GFX1250-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4
; GFX1250-NEXT: buffer_load_b128 v[4:8], v4, s[0:3], null idxen tfe
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX1250-NEXT: global_store_b32 v[2:3], v8, off
; GFX1250-NEXT: s_endpgm
%res = call { <4 x float>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <4 x float>, i32 } %res, 0
store <4 x float> %data, ptr addrspace(1) %data_addr

20
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
View File

@ -26,6 +26,7 @@ define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <
;
; GFX12-LABEL: buffer_store:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_mov_b32_e32 v12, 0
; GFX12-NEXT: s_clause 0x2
; GFX12-NEXT: buffer_store_b128 v[0:3], v12, s[0:3], null idxen
@ -54,6 +55,7 @@ define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
;
; GFX12-LABEL: buffer_store_immoffs:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null idxen offset:42
; GFX12-NEXT: s_endpgm
@ -75,6 +77,7 @@ define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) {
;
; GFX12-LABEL: buffer_store_idx:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
main_body:
@ -101,6 +104,7 @@ define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {
;
; GFX12-LABEL: buffer_store_ofs:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, 0
; GFX12-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], null idxen offen
; GFX12-NEXT: s_endpgm
@ -122,6 +126,7 @@ define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32)
;
; GFX12-LABEL: buffer_store_both:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], null idxen offen
; GFX12-NEXT: s_endpgm
main_body:
@ -144,6 +149,7 @@ define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>,
;
; GFX12-LABEL: buffer_store_both_reversed:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v4
; GFX12-NEXT: buffer_store_b128 v[0:3], v[6:7], s[0:3], null idxen offen
; GFX12-NEXT: s_endpgm
@ -181,6 +187,7 @@ define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32,
;
; GFX12-LABEL: buffer_store_wait:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], null idxen
; GFX12-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], null idxen
@ -207,6 +214,7 @@ define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %
;
; GFX12-LABEL: buffer_store_x1:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
main_body:
@ -227,6 +235,7 @@ define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data,
;
; GFX12-LABEL: buffer_store_x2:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
main_body:
@ -254,6 +263,7 @@ define amdgpu_ps void @buffer_store_int(<4 x i32> inreg, <4 x i32>, <2 x i32>, i
;
; GFX12-LABEL: buffer_store_int:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_mov_b32_e32 v7, 0
; GFX12-NEXT: s_clause 0x2
; GFX12-NEXT: buffer_store_b128 v[0:3], v7, s[0:3], null idxen
@ -282,6 +292,7 @@ define amdgpu_ps void @struct_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1
;
; GFX12-LABEL: struct_buffer_store_byte:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX12-NEXT: buffer_store_b8 v0, v1, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
@ -313,12 +324,16 @@ define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1,
;
; GFX12-TRUE16-LABEL: struct_buffer_store_f16:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: struct_buffer_store_f16:
; GFX12-FAKE16: ; %bb.0:
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX12-FAKE16-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen
; GFX12-FAKE16-NEXT: s_endpgm
@ -349,6 +364,7 @@ define amdgpu_ps void @struct_buffer_store_v2f16(<4 x i32> inreg %rsrc, <2 x hal
;
; GFX12-LABEL: struct_buffer_store_v2f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
@ -381,6 +397,7 @@ define amdgpu_ps void @struct_buffer_store_v4f16(<4 x i32> inreg %rsrc, <4 x hal
;
; GFX12-LABEL: struct_buffer_store_v4f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
@ -402,6 +419,7 @@ define amdgpu_ps void @struct_buffer_store_i16(<4 x i32> inreg %rsrc, float %v1,
;
; GFX12-LABEL: struct_buffer_store_i16:
; GFX12: ; %bb.0: ; %main_body
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX12-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
@ -433,6 +451,7 @@ define amdgpu_ps void @struct_buffer_store_vif16(<4 x i32> inreg %rsrc, <2 x i16
;
; GFX12-LABEL: struct_buffer_store_vif16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b32 v0, v1, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
@ -463,6 +482,7 @@ define amdgpu_ps void @struct_buffer_store_v4i16(<4 x i32> inreg %rsrc, <4 x i16
;
; GFX12-LABEL: struct_buffer_store_v4i16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], null idxen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)

14
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
View File

@ -34,6 +34,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i32(ptr addrspace(8) %p
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -85,6 +86,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i32_const_idx(ptr addrs
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_i32_const_idx:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: v_mov_b32_e32 v1, 15
@ -137,6 +139,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i32_off(ptr addrspace(8
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_i32_off:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -191,6 +194,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i32_soff(ptr addrspace(
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_i32_soff:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -245,6 +249,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i32_dlc(ptr addrspace(8
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_i32_dlc:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -299,6 +304,7 @@ define amdgpu_kernel void @struct_ptr_nonatomic_buffer_load_i32(ptr addrspace(8)
;
; GFX12-LABEL: struct_ptr_nonatomic_buffer_load_i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -354,6 +360,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i64(ptr addrspace(8) %p
;
; GFX12-SDAG-TRUE16-LABEL: struct_ptr_atomic_buffer_load_i64:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX12-SDAG-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -377,6 +384,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i64(ptr addrspace(8) %p
;
; GFX12-GISEL-TRUE16-LABEL: struct_ptr_atomic_buffer_load_i64:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_clause 0x1
; GFX12-GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -433,6 +441,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_v2i16(ptr addrspace(8)
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_v2i16:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -559,6 +568,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_v4i16(ptr addrspace(8)
;
; GFX12-SDAG-TRUE16-LABEL: struct_ptr_atomic_buffer_load_v4i16:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX12-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-SDAG-TRUE16-NEXT: s_clause 0x1
; GFX12-SDAG-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -582,6 +592,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_v4i16(ptr addrspace(8)
;
; GFX12-FAKE16-LABEL: struct_ptr_atomic_buffer_load_v4i16:
; GFX12-FAKE16: ; %bb.0: ; %bb
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_clause 0x1
; GFX12-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -607,6 +618,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_v4i16(ptr addrspace(8)
;
; GFX12-GISEL-TRUE16-LABEL: struct_ptr_atomic_buffer_load_v4i16:
; GFX12-GISEL-TRUE16: ; %bb.0: ; %bb
; GFX12-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-GISEL-TRUE16-NEXT: s_clause 0x1
; GFX12-GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -664,6 +676,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_v4i32(ptr addrspace(8)
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_v4i32:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@ -721,6 +734,7 @@ define amdgpu_kernel void @struct_ptr_atomic_buffer_load_ptr(ptr addrspace(8) %p
;
; GFX12-LABEL: struct_ptr_atomic_buffer_load_ptr:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24

24
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
View File

@ -13,6 +13,7 @@ declare bfloat @llvm.amdgcn.tanh.bf16(bfloat) #0
define amdgpu_kernel void @tanh_f32(ptr addrspace(1) %out, float %src) #1 {
; SDAG-REAL16-LABEL: tanh_f32:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
@ -22,6 +23,7 @@ define amdgpu_kernel void @tanh_f32(ptr addrspace(1) %out, float %src) #1 {
;
; SDAG-FAKE16-LABEL: tanh_f32:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -37,6 +39,7 @@ define amdgpu_kernel void @tanh_f32(ptr addrspace(1) %out, float %src) #1 {
define amdgpu_kernel void @tanh_f32_constant_4.0(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_f32_constant_4.0:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_tanh_f32_e32 v0, 4.0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -46,6 +49,7 @@ define amdgpu_kernel void @tanh_f32_constant_4.0(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: tanh_f32_constant_4.0:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_tanh_f32_e32 v0, 4.0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -60,6 +64,7 @@ define amdgpu_kernel void @tanh_f32_constant_4.0(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_f32_constant_100.0(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_f32_constant_100.0:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_tanh_f32_e32 v0, 0x42c80000
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -69,6 +74,7 @@ define amdgpu_kernel void @tanh_f32_constant_100.0(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: tanh_f32_constant_100.0:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_tanh_f32_e32 v0, 0x42c80000
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -83,10 +89,12 @@ define amdgpu_kernel void @tanh_f32_constant_100.0(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_undef_f32(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_undef_f32:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: tanh_undef_f32:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_endpgm
%tanh = call float @llvm.amdgcn.tanh.f32(float undef)
store float %tanh, ptr addrspace(1) %out, align 4
@ -96,6 +104,7 @@ define amdgpu_kernel void @tanh_undef_f32(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_f16(ptr addrspace(1) %out, half %src) #1 {
; SDAG-REAL16-LABEL: tanh_f16:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
@ -105,6 +114,7 @@ define amdgpu_kernel void @tanh_f16(ptr addrspace(1) %out, half %src) #1 {
;
; SDAG-FAKE16-LABEL: tanh_f16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -119,6 +129,7 @@ define amdgpu_kernel void @tanh_f16(ptr addrspace(1) %out, half %src) #1 {
define amdgpu_kernel void @tanh_f16_constant_4.0(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_f16_constant_4.0:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 4.0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -128,6 +139,7 @@ define amdgpu_kernel void @tanh_f16_constant_4.0(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: tanh_f16_constant_4.0:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 4.0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -142,6 +154,7 @@ define amdgpu_kernel void @tanh_f16_constant_4.0(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_f16_constant_100.0(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_f16_constant_100.0:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 0x5640
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -151,6 +164,7 @@ define amdgpu_kernel void @tanh_f16_constant_100.0(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: tanh_f16_constant_100.0:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 0x5640
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -165,10 +179,12 @@ define amdgpu_kernel void @tanh_f16_constant_100.0(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_undef_f16(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_undef_f16:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: tanh_undef_f16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_endpgm
%tanh = call half @llvm.amdgcn.tanh.f16(half undef)
store half %tanh, ptr addrspace(1) %out, align 2
@ -178,6 +194,7 @@ define amdgpu_kernel void @tanh_undef_f16(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; SDAG-REAL16-LABEL: tanh_bf16:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
@ -187,6 +204,7 @@ define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; SDAG-FAKE16-LABEL: tanh_bf16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
@ -201,6 +219,7 @@ define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_bf16_constant_4:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -210,6 +229,7 @@ define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: tanh_bf16_constant_4:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, 4.0
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -224,6 +244,7 @@ define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_bf16_constant_100:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 0x42c8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
@ -233,6 +254,7 @@ define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; SDAG-FAKE16-LABEL: tanh_bf16_constant_100:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, 0x42c8
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@ -247,10 +269,12 @@ define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @tanh_undef_bf16(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-LABEL: tanh_undef_bf16:
; SDAG-REAL16: ; %bb.0:
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: tanh_undef_bf16:
; SDAG-FAKE16: ; %bb.0:
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SDAG-FAKE16-NEXT: s_endpgm
%tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat undef)
store bfloat %tanh, ptr addrspace(1) %out, align 2

12
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
View File

@ -10,6 +10,7 @@ declare void @llvm.amdgcn.tensor.store.from.lds.d2(<4 x i32> %D0, <8 x i32> %D1,
define amdgpu_ps void @tensor_load_to_lds(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
; GFX1250-LABEL: tensor_load_to_lds:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
; GFX1250-NEXT: s_endpgm
entry:
@ -20,6 +21,7 @@ entry:
define amdgpu_ps void @tensor_load_to_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {
; GFX1250-SDAG-LABEL: tensor_load_to_lds_vector:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6
@ -46,6 +48,7 @@ define amdgpu_ps void @tensor_load_to_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <
;
; GFX1250-GISEL-LABEL: tensor_load_to_lds_vector:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
@ -78,6 +81,7 @@ entry:
define amdgpu_ps void @tensor_load_to_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
; GFX1250-LABEL: tensor_load_to_lds_d2:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
entry:
@ -88,6 +92,7 @@ entry:
define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {
; GFX1250-SDAG-LABEL: tensor_load_to_lds_d2_vector:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1
@ -106,6 +111,7 @@ define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1
;
; GFX1250-GISEL-LABEL: tensor_load_to_lds_d2_vector:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
@ -129,6 +135,7 @@ entry:
define amdgpu_ps void @tensor_store_from_lds(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
; GFX1250-LABEL: tensor_store_from_lds:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
; GFX1250-NEXT: s_endpgm
entry:
@ -139,6 +146,7 @@ entry:
define amdgpu_ps void @tensor_store_from_lds_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {
; GFX1250-SDAG-LABEL: tensor_store_from_lds_vector:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6
@ -165,6 +173,7 @@ define amdgpu_ps void @tensor_store_from_lds_vector(<4 x i32> %D0, <8 x i32> %D1
;
; GFX1250-GISEL-LABEL: tensor_store_from_lds_vector:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
@ -196,6 +205,7 @@ entry:
define amdgpu_ps void @tensor_store_from_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
; GFX1250-LABEL: tensor_store_from_lds_d2:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11]
; GFX1250-NEXT: s_endpgm
entry:
@ -206,6 +216,7 @@ entry:
define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {
; GFX1250-SDAG-LABEL: tensor_store_from_lds_d2_vector:
; GFX1250-SDAG: ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1
@ -224,6 +235,7 @@ define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32>
;
; GFX1250-GISEL-LABEL: tensor_store_from_lds_d2_vector:
; GFX1250-GISEL: ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2

1
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
View File

@ -29,6 +29,7 @@ define amdgpu_cs void @test_wave_id(ptr addrspace(1) %out) {
;
; GFX1250-LABEL: test_wave_id:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_mov_b32_e32 v2, s0

246
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
View File

File diff suppressed because it is too large Load Diff

174
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
View File

File diff suppressed because it is too large Load Diff

220
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
View File

File diff suppressed because it is too large Load Diff

46
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
View File

@ -5,6 +5,7 @@
define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16(<16 x bfloat> %A, <32 x bfloat> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x64_bf16:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v32, v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 index_key:1
@ -15,6 +16,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16(<16 x bfloat> %A, <32 x bfl
;
; GISEL-LABEL: test_swmmac_f32_16x16x64_bf16:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b32 v32, v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 index_key:1
@ -34,6 +36,7 @@ bb:
define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16(<16 x bfloat> %A, <32 x bfloat> %B, <8 x bfloat> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_bf16_16x16x64_bf16:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v28, v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 index_key:1
@ -42,6 +45,7 @@ define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16(<16 x bfloat> %A, <32 x bf
;
; GISEL-LABEL: test_swmmac_bf16_16x16x64_bf16:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b32 v28, v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 index_key:1
@ -59,6 +63,7 @@ bb:
define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16(<16 x bfloat> %A, <32 x bfloat> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v32, v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 index_key:1
@ -69,6 +74,7 @@ define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16(<16 x bfloat> %A, <32 x
;
; GISEL-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b32 v32, v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 index_key:1
@ -88,6 +94,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_fp8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -99,6 +106,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_fp8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -120,6 +128,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_fp8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -131,6 +140,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_fp8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -151,6 +161,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_bf8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_fp8_bf8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_fp8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -162,6 +173,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_bf8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_fp8_bf8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_fp8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -183,6 +195,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_bf8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_fp8_bf8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_fp8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -194,6 +207,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_bf8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_fp8_bf8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_fp8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -214,6 +228,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_fp8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_bf8_fp8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_bf8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -225,6 +240,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_fp8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_bf8_fp8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_bf8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -246,6 +262,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_fp8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_bf8_fp8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_bf8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -257,6 +274,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_fp8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_bf8_fp8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_bf8_fp8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -277,6 +295,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_bf8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_bf8_bf8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_bf8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -288,6 +307,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_bf8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_bf8_bf8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_bf8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -309,6 +329,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_bf8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x128_bf8_bf8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x128_bf8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -320,6 +341,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x128_bf8_bf8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f32_16x16x128_bf8_bf8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x128_bf8_bf8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -340,6 +362,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_fp8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_fp8_fp8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -349,6 +372,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_fp8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_fp8_fp8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -368,6 +392,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_fp8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_fp8_fp8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -377,6 +402,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_fp8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_fp8_fp8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -395,6 +421,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_bf8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_fp8_bf8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -404,6 +431,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_bf8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_fp8_bf8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -423,6 +451,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_bf8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_fp8_bf8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -432,6 +461,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_bf8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_fp8_bf8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -450,6 +480,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_fp8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_bf8_fp8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -459,6 +490,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_fp8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_bf8_fp8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -478,6 +510,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_fp8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_bf8_fp8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -487,6 +520,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_fp8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_bf8_fp8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -505,6 +539,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_bf8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_bf8_bf8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -514,6 +549,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_bf8_i32_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_bf8_bf8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -533,6 +569,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_bf8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x128_bf8_bf8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[28:29], v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -542,6 +579,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_bf8_i64_index(<8 x i32> %A,
;
; GISEL-LABEL: test_swmmac_f16_16x16x128_bf8_bf8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[28:29], v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] index_key:1
@ -560,6 +598,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x128_iu8_i32_index(<8 x i32> %A, <16 x i32> %B, <8 x i32> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_i32_16x16x128_iu8_i32_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_i32_16x16x128_iu8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -571,6 +610,7 @@ define amdgpu_ps void @test_swmmac_i32_16x16x128_iu8_i32_index(<8 x i32> %A, <16
;
; GISEL-LABEL: test_swmmac_i32_16x16x128_iu8_i32_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_i32_16x16x128_iu8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -592,6 +632,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x128_iu8_i64_index(<8 x i32> %A, <16 x i32> %B, <8 x i32> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %IndexVecOutPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_i32_16x16x128_iu8_i64_index:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b64 v[32:33], v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_i32_16x16x128_iu8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -603,6 +644,7 @@ define amdgpu_ps void @test_swmmac_i32_16x16x128_iu8_i64_index(<8 x i32> %A, <16
;
; GISEL-LABEL: test_swmmac_i32_16x16x128_iu8_i64_index:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b64 v[32:33], v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_i32_16x16x128_iu8 v[24:31], v[0:7], v[8:23], v[32:33] index_key:1
@ -623,6 +665,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x64_f16(<16 x half> %A, <32 x half> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f32_16x16x64_f16:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v32, v[32:33], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 index_key:1
@ -633,6 +676,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_f16(<16 x half> %A, <32 x half>
;
; GISEL-LABEL: test_swmmac_f32_16x16x64_f16:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b32 v32, v[32:33], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 index_key:1
@ -652,6 +696,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x64_f16(<16 x half> %A, <32 x half> %B, <8 x half> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_swmmac_f16_16x16x64_f16:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_load_b32 v28, v[28:29], off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 index_key:1
@ -660,6 +705,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x64_f16(<16 x half> %A, <32 x half>
;
; GISEL-LABEL: test_swmmac_f16_16x16x64_f16:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GISEL-NEXT: global_load_b32 v28, v[28:29], off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 index_key:1

4
llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
View File

@ -9,10 +9,12 @@ declare bfloat @llvm.cos.bf16(bfloat) #0
define amdgpu_kernel void @cos_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; GCN-LABEL: cos_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GCN-NEXT: s_mov_b32 s3, 0x3e230000
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GCN-NEXT: v_fma_mixlo_bf16 v0, s2, s3, 0 op_sel_hi:[1,0,0]
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_cos_bf16_e32 v0, v0
@ -26,6 +28,7 @@ define amdgpu_kernel void @cos_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
define amdgpu_kernel void @cos_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GCN-LABEL: cos_bf16_constant_4:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GCN-NEXT: v_cos_bf16_e32 v0, 0x3f23
; GCN-NEXT: v_mov_b32_e32 v1, 0
@ -40,6 +43,7 @@ define amdgpu_kernel void @cos_bf16_constant_4(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @cos_bf16_constant_100(ptr addrspace(1) %out) #1 {
; GCN-LABEL: cos_bf16_constant_100:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GCN-NEXT: v_cos_bf16_e32 v0, 0x417f
; GCN-NEXT: v_mov_b32_e32 v1, 0

262
llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
View File

@ -17,18 +17,25 @@
define amdgpu_ps void @prefetch_data_sgpr(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_data_sgpr:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_sgpr:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_sgpr:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p4(ptr addrspace(4) %ptr, i32 0, i32 0, i32 1)
ret void
@ -37,18 +44,25 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] offset:512 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_data_sgpr_offset:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x200, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x200, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_sgpr_offset:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_sgpr_offset:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x200, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
%gep = getelementptr float, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 1)
@ -60,18 +74,25 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_max_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_max_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] offset:8388607 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_data_sgpr_max_offset:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x7fffff, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_max_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x7fffff, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_sgpr_max_offset:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_sgpr_max_offset:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x7fffff, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 8388607
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 1)
@ -81,12 +102,14 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_min_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_min_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] offset:-8388608 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-SDAG-LABEL: prefetch_data_sgpr_min_offset:
; GFX1250-SPREFETCH-SDAG: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-SDAG-NEXT: s_mov_b64 s[2:3], 0xffffffffff800000
; GFX1250-SPREFETCH-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
@ -108,6 +131,7 @@ define amdgpu_ps void @prefetch_data_sgpr_min_offset(ptr addrspace(4) inreg %ptr
;
; GFX1250-SPREFETCH-GISEL-LABEL: prefetch_data_sgpr_min_offset:
; GFX1250-SPREFETCH-GISEL: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_u32 s0, s0, 0xff800000
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1
; GFX1250-SPREFETCH-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
@ -128,12 +152,14 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_too_large_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_too_large_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-SDAG-LABEL: prefetch_data_sgpr_too_large_offset:
; GFX1250-SPREFETCH-SDAG: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x800000
; GFX1250-SPREFETCH-SDAG-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-SDAG-NEXT: s_endpgm
@ -150,6 +176,7 @@ define amdgpu_ps void @prefetch_data_sgpr_too_large_offset(ptr addrspace(4) inre
;
; GFX1250-SPREFETCH-GISEL-LABEL: prefetch_data_sgpr_too_large_offset:
; GFX1250-SPREFETCH-GISEL: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_u32 s0, s0, 0x800000
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
; GFX1250-SPREFETCH-GISEL-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
@ -172,11 +199,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_global(ptr addrspace(1) %ptr) {
; GFX1250-LABEL: prefetch_data_vgpr_global:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_prefetch_b8 v[0:1], off scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_global:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v[0:1], off scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -195,11 +224,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_flat(ptr %ptr) {
; GFX1250-LABEL: prefetch_data_vgpr_flat:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_flat:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -218,11 +249,13 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_vgpr_offset_global(ptr addrspace(1) inreg %ptr, i32 %offset) {
; GFX1250-LABEL: prefetch_data_sgpr_vgpr_offset_global:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_vgpr_offset_global:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -248,11 +281,13 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_vgpr_offset_flat(ptr inreg %ptr, i32 %offset) {
; GFX1250-LABEL: prefetch_data_sgpr_vgpr_offset_flat:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_prefetch_b8 v0, s[0:1] offset:128 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_vgpr_offset_flat:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v0, s[0:1] offset:128 scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -279,18 +314,46 @@ entry:
; Check LDS and Scratch, we cannot prefetch it
define amdgpu_ps void @prefetch_data_lds(ptr addrspace(3) inreg %ptr) {
; GCN-LABEL: prefetch_data_lds:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_endpgm
; GFX1250-LABEL: prefetch_data_lds:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_lds:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_lds:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_lds:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p3(ptr addrspace(3) %ptr, i32 0, i32 0, i32 1)
ret void
}
define amdgpu_ps void @prefetch_data_scratch(ptr addrspace(5) inreg %ptr) {
; GCN-LABEL: prefetch_data_scratch:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_endpgm
; GFX1250-LABEL: prefetch_data_scratch:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_scratch:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_scratch:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_scratch:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p5(ptr addrspace(5) %ptr, i32 0, i32 0, i32 1)
ret void
@ -301,18 +364,25 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_flat(ptr inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_flat:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: flat_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_data_sgpr_flat:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_flat:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_sgpr_flat:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_sgpr_flat:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.pf(ptr %ptr, i32 0, i32 0, i32 1)
ret void
@ -321,18 +391,25 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_global(ptr addrspace(1) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_global:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_data_sgpr_global:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_global:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_sgpr_global:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_sgpr_global:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p1(ptr addrspace(1) %ptr, i32 0, i32 0, i32 1)
ret void
@ -341,17 +418,25 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_constant_32bit(ptr addrspace(6) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_constant_32bit:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_data_sgpr_constant_32bit:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_mov_b32 s1, 0
; SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_constant_32bit:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_mov_b32 s1, 0
; GFX1250-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_data_sgpr_constant_32bit:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_data_sgpr_constant_32bit:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_mov_b32 s1, 0
; GFX12-SPREFETCH-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p6(ptr addrspace(6) %ptr, i32 0, i32 0, i32 1)
ret void
@ -362,16 +447,23 @@ entry:
define amdgpu_ps void @prefetch_inst_sgpr(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_inst_sgpr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_inst_sgpr:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_inst_sgpr:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_inst_sgpr:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_inst_sgpr:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p4(ptr addrspace(4) %ptr, i32 0, i32 0, i32 0)
ret void
@ -380,16 +472,23 @@ entry:
define amdgpu_ps void @prefetch_inst_sgpr_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_inst_sgpr_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_inst_sgpr_offset:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x80, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_inst_sgpr_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x80, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_inst_sgpr_offset:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_inst_sgpr_offset:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x80, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 128
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 0)
@ -401,16 +500,23 @@ entry:
define amdgpu_ps void @prefetch_inst_sgpr_max_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_inst_sgpr_max_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; SPREFETCH-LABEL: prefetch_inst_sgpr_max_offset:
; SPREFETCH: ; %bb.0: ; %entry
; SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x7fffff, null, 0
; SPREFETCH-NEXT: s_endpgm
; GFX1250-SPREFETCH-LABEL: prefetch_inst_sgpr_max_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x7fffff, null, 0
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_inst_sgpr_max_offset:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_inst_sgpr_max_offset:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_prefetch_inst s[0:1], 0x7fffff, null, 0
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
%gep = getelementptr i8, ptr addrspace(4) %ptr, i32 8388607
tail call void @llvm.prefetch.p4(ptr addrspace(4) %gep, i32 0, i32 0, i32 0)
@ -420,10 +526,12 @@ entry:
define amdgpu_ps void @prefetch_inst_sgpr_min_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_inst_sgpr_min_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-SDAG-LABEL: prefetch_inst_sgpr_min_offset:
; GFX1250-SPREFETCH-SDAG: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-SDAG-NEXT: s_mov_b64 s[2:3], 0xffffffffff800000
; GFX1250-SPREFETCH-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
@ -445,6 +553,7 @@ define amdgpu_ps void @prefetch_inst_sgpr_min_offset(ptr addrspace(4) inreg %ptr
;
; GFX1250-SPREFETCH-GISEL-LABEL: prefetch_inst_sgpr_min_offset:
; GFX1250-SPREFETCH-GISEL: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_u32 s0, s0, 0xff800000
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1
; GFX1250-SPREFETCH-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
@ -465,10 +574,12 @@ entry:
define amdgpu_ps void @prefetch_inst_sgpr_too_large_offset(ptr addrspace(4) inreg %ptr) {
; GFX1250-LABEL: prefetch_inst_sgpr_too_large_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-SDAG-LABEL: prefetch_inst_sgpr_too_large_offset:
; GFX1250-SPREFETCH-SDAG: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x800000
; GFX1250-SPREFETCH-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
; GFX1250-SPREFETCH-SDAG-NEXT: s_endpgm
@ -485,6 +596,7 @@ define amdgpu_ps void @prefetch_inst_sgpr_too_large_offset(ptr addrspace(4) inre
;
; GFX1250-SPREFETCH-GISEL-LABEL: prefetch_inst_sgpr_too_large_offset:
; GFX1250-SPREFETCH-GISEL: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_u32 s0, s0, 0x800000
; GFX1250-SPREFETCH-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
; GFX1250-SPREFETCH-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
@ -507,11 +619,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_flat_dev(ptr %ptr) {
; GFX1250-LABEL: prefetch_data_vgpr_flat_dev:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_DEV
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_flat_dev:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_DEV
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -530,11 +644,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_flat_se(ptr %ptr) {
; GFX1250-LABEL: prefetch_data_vgpr_flat_se:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_flat_se:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SE
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -553,16 +669,19 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_flat_cu(ptr %ptr) {
; GL2-ONLY-LABEL: prefetch_data_vgpr_flat_cu:
; GL2-ONLY: ; %bb.0: ; %entry
; GL2-ONLY-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GL2-ONLY-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SE
; GL2-ONLY-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_flat_cu:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v[0:1] scope:SCOPE_SE
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; SAFE-CU-LABEL: prefetch_data_vgpr_flat_cu:
; SAFE-CU: ; %bb.0: ; %entry
; SAFE-CU-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; SAFE-CU-NEXT: flat_prefetch_b8 v[0:1]
; SAFE-CU-NEXT: s_endpgm
;
@ -583,11 +702,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_flat_offset(ptr %ptr) {
; GFX1250-LABEL: prefetch_data_vgpr_flat_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: flat_prefetch_b8 v[0:1] offset:512 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_flat_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v[0:1] offset:512 scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -607,11 +728,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_global_offset(ptr addrspace(1) %ptr) {
; GFX1250-LABEL: prefetch_data_vgpr_global_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_prefetch_b8 v[0:1], off offset:512 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_global_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v[0:1], off offset:512 scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -631,11 +754,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_global_saddr(ptr addrspace(1) inreg %ptr, i32 %voffset) {
; GFX1250-LABEL: prefetch_data_vgpr_global_saddr:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_global_saddr:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -655,11 +780,13 @@ entry:
define amdgpu_ps void @prefetch_data_vgpr_global_saddr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset) {
; GFX1250-LABEL: prefetch_data_vgpr_global_saddr_offset:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] offset:128 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_vgpr_global_saddr_offset:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v0, s[0:1] offset:128 scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
@ -680,18 +807,46 @@ entry:
; Cannot prefetch I$ with flat or global instructions.
define amdgpu_ps void @prefetch_inst_vgpr_global(ptr addrspace(1) %ptr) {
; GCN-LABEL: prefetch_inst_vgpr_global:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_endpgm
; GFX1250-LABEL: prefetch_inst_vgpr_global:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_inst_vgpr_global:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_inst_vgpr_global:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_inst_vgpr_global:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.p1(ptr addrspace(1) %ptr, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @prefetch_inst_vgpr_flat(ptr %ptr) {
; GCN-LABEL: prefetch_inst_vgpr_flat:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_endpgm
; GFX1250-LABEL: prefetch_inst_vgpr_flat:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_inst_vgpr_flat:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: s_endpgm
;
; NOSPREFETCH-LABEL: prefetch_inst_vgpr_flat:
; NOSPREFETCH: ; %bb.0: ; %entry
; NOSPREFETCH-NEXT: s_endpgm
;
; GFX12-SPREFETCH-LABEL: prefetch_inst_vgpr_flat:
; GFX12-SPREFETCH: ; %bb.0: ; %entry
; GFX12-SPREFETCH-NEXT: s_endpgm
entry:
tail call void @llvm.prefetch.pf(ptr %ptr, i32 0, i32 0, i32 0)
ret void
@ -702,12 +857,14 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_flat_force_vector(ptr inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_flat_force_vector:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: flat_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_flat_force_vector:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-SPREFETCH-NEXT: flat_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
@ -728,12 +885,14 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_global_force_vector(ptr addrspace(1) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_global_force_vector:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_global_force_vector:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
@ -754,12 +913,14 @@ entry:
define amdgpu_ps void @prefetch_data_sgpr_global_saddr_force_vector(ptr addrspace(1) inreg %ptr) {
; GFX1250-LABEL: prefetch_data_sgpr_global_saddr_force_vector:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] offset:1024 scope:SCOPE_SYS
; GFX1250-NEXT: s_endpgm
;
; GFX1250-SPREFETCH-LABEL: prefetch_data_sgpr_global_saddr_force_vector:
; GFX1250-SPREFETCH: ; %bb.0: ; %entry
; GFX1250-SPREFETCH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SPREFETCH-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-SPREFETCH-NEXT: global_prefetch_b8 v0, s[0:1] offset:1024 scope:SCOPE_SYS
; GFX1250-SPREFETCH-NEXT: s_endpgm
@ -784,3 +945,6 @@ declare void @llvm.prefetch.p3(ptr addrspace(3) nocapture readonly, i32, i32, i3
declare void @llvm.prefetch.p4(ptr addrspace(4) nocapture readonly, i32, i32, i32)
declare void @llvm.prefetch.p5(ptr addrspace(5) nocapture readonly, i32, i32, i32)
declare void @llvm.prefetch.p6(ptr addrspace(6) nocapture readonly, i32, i32, i32)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
; SPREFETCH: {{.*}}

4
llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
View File

@ -9,10 +9,12 @@ declare bfloat @llvm.sin.bf16(bfloat) #0
define amdgpu_kernel void @sin_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
; GCN-LABEL: sin_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b96 s[0:2], s[4:5], 0x0
; GCN-NEXT: s_mov_b32 s3, 0x3e230000
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_wait_kmcnt 0x0
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GCN-NEXT: v_fma_mixlo_bf16 v0, s2, s3, 0 op_sel_hi:[1,0,0]
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_sin_bf16_e32 v0, v0
@ -26,6 +28,7 @@ define amdgpu_kernel void @sin_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
define amdgpu_kernel void @sin_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GCN-LABEL: sin_bf16_constant_4:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GCN-NEXT: v_sin_bf16_e32 v0, 0x3f23
; GCN-NEXT: v_mov_b32_e32 v1, 0
@ -40,6 +43,7 @@ define amdgpu_kernel void @sin_bf16_constant_4(ptr addrspace(1) %out) #1 {
define amdgpu_kernel void @sin_bf16_constant_100(ptr addrspace(1) %out) #1 {
; GCN-LABEL: sin_bf16_constant_100:
; GCN: ; %bb.0:
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GCN-NEXT: v_sin_bf16_e32 v0, 0x417f
; GCN-NEXT: v_mov_b32_e32 v1, 0

4
llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
View File

@ -8,6 +8,7 @@ declare <2 x bfloat> @llvm.sqrt.v2bf16(<2 x bfloat> %a)
define amdgpu_kernel void @sqrt_bf16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-LABEL: sqrt_bf16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -26,6 +27,7 @@ define amdgpu_kernel void @sqrt_bf16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
;
; GFX12-FAKE16-LABEL: sqrt_bf16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
@ -51,6 +53,7 @@ entry:
define amdgpu_kernel void @sqrt_v2bf16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-LABEL: sqrt_v2bf16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
@ -72,6 +75,7 @@ define amdgpu_kernel void @sqrt_v2bf16(ptr addrspace(1) %r, ptr addrspace(1) %a)
;
; GFX12-FAKE16-LABEL: sqrt_v2bf16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000

44
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
View File

@ -78,6 +78,7 @@ define amdgpu_kernel void @constant_load_i1(ptr addrspace(1) %out, ptr addrspace
;
; GFX1250-LABEL: constant_load_i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -161,6 +162,7 @@ define amdgpu_kernel void @constant_load_v2i1(ptr addrspace(1) %out, ptr addrspa
;
; GFX1250-LABEL: constant_load_v2i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -241,6 +243,7 @@ define amdgpu_kernel void @constant_load_v3i1(ptr addrspace(1) %out, ptr addrspa
;
; GFX1250-LABEL: constant_load_v3i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -322,6 +325,7 @@ define amdgpu_kernel void @constant_load_v4i1(ptr addrspace(1) %out, ptr addrspa
;
; GFX1250-LABEL: constant_load_v4i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -403,6 +407,7 @@ define amdgpu_kernel void @constant_load_v8i1(ptr addrspace(1) %out, ptr addrspa
;
; GFX1250-LABEL: constant_load_v8i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -484,6 +489,7 @@ define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v16i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -549,6 +555,7 @@ define amdgpu_kernel void @constant_load_v32i1(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v32i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -617,6 +624,7 @@ define amdgpu_kernel void @constant_load_v64i1(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v64i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -689,6 +697,7 @@ define amdgpu_kernel void @constant_zextload_i1_to_i32(ptr addrspace(1) %out, pt
;
; GFX1250-LABEL: constant_zextload_i1_to_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -766,6 +775,7 @@ define amdgpu_kernel void @constant_sextload_i1_to_i32(ptr addrspace(1) %out, pt
;
; GFX1250-LABEL: constant_sextload_i1_to_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -840,6 +850,7 @@ define amdgpu_kernel void @constant_zextload_v1i1_to_v1i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v1i1_to_v1i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -917,6 +928,7 @@ define amdgpu_kernel void @constant_sextload_v1i1_to_v1i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v1i1_to_v1i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -1002,6 +1014,7 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v2i1_to_v2i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1088,6 +1101,7 @@ define amdgpu_kernel void @constant_sextload_v2i1_to_v2i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v2i1_to_v2i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -1184,6 +1198,7 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v3i1_to_v3i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v3, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1281,6 +1296,7 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v3i1_to_v3i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -1378,6 +1394,7 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v4i1_to_v4i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1480,6 +1497,7 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v4i1_to_v4i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -1621,6 +1639,7 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v8i1_to_v8i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v8, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -1767,6 +1786,7 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i32(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v8i1_to_v8i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -1989,6 +2009,7 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_zextload_v16i1_to_v16i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v16, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -2222,6 +2243,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i32(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_sextload_v16i1_to_v16i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0
@ -2629,6 +2651,7 @@ define amdgpu_kernel void @constant_zextload_v32i1_to_v32i32(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_zextload_v32i1_to_v32i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -3100,6 +3123,7 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i32(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_sextload_v32i1_to_v32i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -3870,6 +3894,7 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_zextload_v64i1_to_v64i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -4766,6 +4791,7 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_sextload_v64i1_to_v64i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -4970,6 +4996,7 @@ define amdgpu_kernel void @constant_zextload_i1_to_i64(ptr addrspace(1) %out, pt
;
; GFX1250-LABEL: constant_zextload_i1_to_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -5052,6 +5079,7 @@ define amdgpu_kernel void @constant_sextload_i1_to_i64(ptr addrspace(1) %out, pt
;
; GFX1250-LABEL: constant_sextload_i1_to_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5134,6 +5162,7 @@ define amdgpu_kernel void @constant_zextload_v1i1_to_v1i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v1i1_to_v1i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0
@ -5216,6 +5245,7 @@ define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v1i1_to_v1i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5311,6 +5341,7 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v2i1_to_v2i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5412,6 +5443,7 @@ define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v2i1_to_v2i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5530,6 +5562,7 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v3i1_to_v3i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v5, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5661,6 +5694,7 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v3i1_to_v3i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v5, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5799,6 +5833,7 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v4i1_to_v4i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -5948,6 +5983,7 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v4i1_to_v4i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v9, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -6135,6 +6171,7 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_zextload_v8i1_to_v8i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -6367,6 +6404,7 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
;
; GFX1250-LABEL: constant_sextload_v8i1_to_v8i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v16, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -6695,6 +6733,7 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_zextload_v16i1_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -7100,6 +7139,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v32, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -7698,6 +7738,7 @@ define amdgpu_kernel void @constant_zextload_v32i1_to_v32i64(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_zextload_v32i1_to_v32i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -8495,6 +8536,7 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_sextload_v32i1_to_v32i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -9657,6 +9699,7 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_zextload_v64i1_to_v64i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -11206,6 +11249,7 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
;
; GFX1250-LABEL: constant_sextload_v64i1_to_v64i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b64 s[10:11], s[2:3], 0x0

25
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
View File

@ -87,6 +87,7 @@ define amdgpu_kernel void @constant_load_i32(ptr addrspace(1) %out, ptr addrspac
;
; GFX1250-LABEL: constant_load_i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -184,6 +185,7 @@ define amdgpu_kernel void @constant_load_v2i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v2i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -293,6 +295,7 @@ define amdgpu_kernel void @constant_load_v3i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v3i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b96 s[4:6], s[2:3], 0x0
@ -400,6 +403,7 @@ define amdgpu_kernel void @constant_load_v4i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v4i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -545,6 +549,7 @@ define amdgpu_kernel void @constant_load_v8i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v8i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
@ -724,6 +729,7 @@ define amdgpu_kernel void @constant_load_v9i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: constant_load_v9i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1
@ -912,6 +918,7 @@ define amdgpu_kernel void @constant_load_v10i32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: constant_load_v10i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1
@ -1112,6 +1119,7 @@ define amdgpu_kernel void @constant_load_v11i32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: constant_load_v11i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1
@ -1310,6 +1318,7 @@ define amdgpu_kernel void @constant_load_v12i32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: constant_load_v12i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1
@ -1540,6 +1549,7 @@ define amdgpu_kernel void @constant_load_v16i32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: constant_load_v16i32:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[16:19], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b512 s[0:15], s[18:19], 0x0
@ -1648,6 +1658,7 @@ define amdgpu_kernel void @constant_zextload_i32_to_i64(ptr addrspace(1) %out, p
;
; GFX1250-LABEL: constant_zextload_i32_to_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -1752,6 +1763,7 @@ define amdgpu_kernel void @constant_sextload_i32_to_i64(ptr addrspace(1) %out, p
;
; GFX1250-LABEL: constant_sextload_i32_to_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -1851,6 +1863,7 @@ define amdgpu_kernel void @constant_zextload_v1i32_to_v1i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_zextload_v1i32_to_v1i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -1955,6 +1968,7 @@ define amdgpu_kernel void @constant_sextload_v1i32_to_v1i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_sextload_v1i32_to_v1i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0
@ -2067,6 +2081,7 @@ define amdgpu_kernel void @constant_zextload_v2i32_to_v2i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_zextload_v2i32_to_v2i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -2192,6 +2207,7 @@ define amdgpu_kernel void @constant_sextload_v2i32_to_v2i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_sextload_v2i32_to_v2i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@ -2338,6 +2354,7 @@ define amdgpu_kernel void @constant_zextload_v4i32_to_v4i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_zextload_v4i32_to_v4i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
@ -2515,6 +2532,7 @@ define amdgpu_kernel void @constant_sextload_v4i32_to_v4i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_sextload_v4i32_to_v4i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
@ -2735,6 +2753,7 @@ define amdgpu_kernel void @constant_zextload_v8i32_to_v8i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_zextload_v8i32_to_v8i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
@ -3025,6 +3044,7 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
;
; GFX1250-LABEL: constant_sextload_v8i32_to_v8i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b256 s[4:11], s[2:3], 0x0
@ -3532,6 +3552,7 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
;
; GFX1250-LABEL: constant_sextload_v16i32_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[16:19], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b512 s[0:15], s[18:19], 0x0
@ -3928,6 +3949,7 @@ define amdgpu_kernel void @constant_zextload_v16i32_to_v16i64(ptr addrspace(1) %
;
; GFX1250-LABEL: constant_zextload_v16i32_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[16:19], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b512 s[0:15], s[18:19], 0x0
@ -4870,6 +4892,7 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
;
; GFX1250-LABEL: constant_sextload_v32i32_to_v32i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[36:39], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1
@ -5617,6 +5640,7 @@ define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(ptr addrspace(1) %
;
; GFX1250-LABEL: constant_zextload_v32i32_to_v32i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[36:39], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b512 s[16:31], s[38:39], 0x40
@ -6048,6 +6072,7 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
;
; GFX1250-LABEL: constant_load_v32i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[36:39], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1

6
llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
View File

@ -66,6 +66,7 @@ define amdgpu_kernel void @copy_flat(ptr nocapture %d, ptr nocapture readonly %s
;
; GFX1250-LABEL: copy_flat:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_eq_u32 s6, 0
@ -161,6 +162,7 @@ define amdgpu_kernel void @copy_global(ptr addrspace(1) nocapture %d, ptr addrsp
;
; GFX1250-LABEL: copy_global:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_eq_u32 s6, 0
@ -258,6 +260,7 @@ define amdgpu_kernel void @copy_constant(ptr addrspace(1) nocapture %d, ptr addr
;
; GFX1250-LABEL: copy_constant:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s6, s[4:5], 0x34
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_eq_u32 s6, 0
@ -355,6 +358,7 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
;
; GFX1250-LABEL: copy_local:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_eq_u32 s2, 0
@ -481,6 +485,7 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
;
; GFX1250-LABEL: copy_flat_divergent:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x34
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_eq_u32 s2, 0
@ -614,6 +619,7 @@ define amdgpu_kernel void @copy_global_divergent(ptr addrspace(1) nocapture %d,
;
; GFX1250-LABEL: copy_global_divergent:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x34
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_eq_u32 s0, 0

14
llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
View File

@ -49,6 +49,7 @@ define amdgpu_cs void @_amdgpu_cs_main() {
;
; GFX1250-SDAG-LABEL: _amdgpu_cs_main:
; GFX1250-SDAG: ; %bb.0: ; %.entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c
; GFX1250-SDAG-NEXT: s_bfe_u32 s2, ttmp6, 0x40010
; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, 1
@ -79,6 +80,7 @@ define amdgpu_cs void @_amdgpu_cs_main() {
;
; GFX1250-GISEL-LABEL: _amdgpu_cs_main:
; GFX1250-GISEL: ; %bb.0: ; %.entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c
; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 15
; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1
@ -164,6 +166,7 @@ define amdgpu_cs void @workgroup_id_no_clusters() "amdgpu-cluster-dims"="0,0,0"
;
; GFX1250-SDAG-LABEL: workgroup_id_no_clusters:
; GFX1250-SDAG: ; %bb.0: ; %.entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff
; GFX1250-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0
@ -173,6 +176,7 @@ define amdgpu_cs void @workgroup_id_no_clusters() "amdgpu-cluster-dims"="0,0,0"
;
; GFX1250-GISEL-LABEL: workgroup_id_no_clusters:
; GFX1250-GISEL: ; %bb.0: ; %.entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_mov_b32 s0, ttmp9
; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff
; GFX1250-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16
@ -234,6 +238,7 @@ define amdgpu_cs void @workgroup_id_optimized() "amdgpu-cluster-dims"="2,3,4" {
;
; GFX1250-SDAG-LABEL: workgroup_id_optimized:
; GFX1250-SDAG: ; %bb.0: ; %.entry
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 14
; GFX1250-SDAG-NEXT: s_and_b32 s2, ttmp7, 0xffff
; GFX1250-SDAG-NEXT: s_and_b32 s0, ttmp6, 15
@ -252,6 +257,7 @@ define amdgpu_cs void @workgroup_id_optimized() "amdgpu-cluster-dims"="2,3,4" {
;
; GFX1250-GISEL-LABEL: workgroup_id_optimized:
; GFX1250-GISEL: ; %bb.0: ; %.entry
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff
; GFX1250-GISEL-NEXT: s_and_b32 s0, ttmp6, 15
; GFX1250-GISEL-NEXT: s_bfe_u32 s2, ttmp6, 0x40004
@ -333,12 +339,14 @@ define amdgpu_cs void @caller() {
;
; GFX1250-SDAG-LABEL: caller:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: s_mov_b32 s32, 0
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c
; GFX1250-SDAG-NEXT: s_and_b32 s1, ttmp6, 15
; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, 1
; GFX1250-SDAG-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-SDAG-NEXT: s_mul_i32 s0, ttmp9, s0
; GFX1250-SDAG-NEXT: s_mov_b32 s32, 0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, s0
; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s2, 0
; GFX1250-SDAG-NEXT: s_cselect_b32 s2, ttmp9, s1
@ -349,12 +357,14 @@ define amdgpu_cs void @caller() {
;
; GFX1250-GISEL-LABEL: caller:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_mov_b32 s32, 0
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c
; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 15
; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1
; GFX1250-GISEL-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-GISEL-NEXT: s_mul_i32 s0, ttmp9, s0
; GFX1250-GISEL-NEXT: s_mov_b32 s32, 0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, s0
; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0
; GFX1250-GISEL-NEXT: s_cselect_b32 s2, ttmp9, s1

1
llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
View File

@ -595,6 +595,7 @@ define float @v_mad_mix_f32_bf16lo_cast_from_half_bf16lo_bf16lo(half %src0, bflo
define amdgpu_kernel void @test_fma_mix_f32_bf16_src2_bf16lo(float %x, i32 %y, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_fma_mix_f32_bf16_src2_bf16lo:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, s0, 0, s1 op_sel_hi:[0,0,1]

2
llvm/test/CodeGen/AMDGPU/mad_64_32.ll
View File

@ -1118,6 +1118,7 @@ define amdgpu_kernel void @mad_i64_i32_uniform(ptr addrspace(1) %out, i32 %arg0,
;
; GFX1250-LABEL: mad_i64_i32_uniform:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -2226,6 +2227,7 @@ define amdgpu_ps i64 @lshr_mad_i64_sgpr(i64 inreg %arg0) #0 {
;
; GFX1250-LABEL: lshr_mad_i64_sgpr:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mov_b32 s3, 0
; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: s_mov_b64 s[4:5], 0xffffffffffff1c18

14
llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
View File

@ -26,6 +26,7 @@ define amdgpu_ps float @mad_i32_vvv(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-LABEL: mad_i32_vvv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -58,6 +59,7 @@ define amdgpu_ps float @mad_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
;
; GFX1250-LABEL: mad_i32_sss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_mul_i32 s0, s0, s1
; GFX1250-NEXT: s_add_co_i32 s0, s0, s2
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
@ -88,6 +90,7 @@ define amdgpu_ps float @mad_i32_vvc(i32 %a, i32 %b) {
;
; GFX1250-LABEL: mad_i32_vvc:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 42
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -118,6 +121,7 @@ define amdgpu_ps float @mad_i32_vvi(i32 %a, i32 %b) {
;
; GFX1250-LABEL: mad_i32_vvi:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 0x12d687
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -148,6 +152,7 @@ define amdgpu_ps float @mad_i32_vvi_neg(i32 %a, i32 %b) {
;
; GFX1250-LABEL: mad_i32_vvi_neg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 0xffed2979
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -175,6 +180,7 @@ define amdgpu_ps float @mad_i32_vcv(i32 %a, i32 %c) {
;
; GFX1250-LABEL: mad_i32_vcv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, 42, v1
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, 42
@ -202,6 +208,7 @@ define amdgpu_ps float @mad_i32_vcc(i32 %a) {
;
; GFX1250-LABEL: mad_i32_vcc:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, 42, 43
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, 42
@ -230,6 +237,7 @@ define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {
;
; GFX1250-LABEL: mad_i32_vvs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, v1, s0
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -257,6 +265,7 @@ define amdgpu_ps float @mad_i32_vsv(i32 %a, i32 inreg %b, i32 %c) {
;
; GFX1250-LABEL: mad_i32_vsv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, s0, v1
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -284,6 +293,7 @@ define amdgpu_ps float @mad_i32_svv(i32 inreg %a, i32 %b, i32 %c) {
;
; GFX1250-LABEL: mad_i32_svv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, s0, v0, v1
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -314,6 +324,7 @@ define amdgpu_ps float @mad_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c) {
;
; GFX1250-LABEL: mad_i32_vss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, v0, s0, s1
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -344,6 +355,7 @@ define amdgpu_ps float @mad_i32_svs(i32 inreg %a, i32 %b, i32 inreg %c) {
;
; GFX1250-LABEL: mad_i32_svs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, s0, v0, s1
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -372,6 +384,7 @@ define amdgpu_ps float @mad_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
;
; GFX1250-LABEL: mad_i32_ssv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mad_u32 v0, s0, s1, v0
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
@ -407,6 +420,7 @@ define amdgpu_ps float @mad_i32_vvv_multiuse(i32 %a, i32 %b, i32 %c) {
;
; GFX1250-LABEL: mad_i32_vvv_multiuse:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mul_lo_u32 v1, v0, v1
; GFX1250-NEXT: v_add_nc_u32_e32 v0, v1, v2
; GFX1250-NEXT: flat_store_b32 v[0:1], v1

23
llvm/test/CodeGen/AMDGPU/max.ll
View File

@ -27,6 +27,7 @@ define amdgpu_kernel void @v_test_imax_sge_i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: v_test_imax_sge_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
@ -100,6 +101,7 @@ define amdgpu_kernel void @v_test_imax_sge_v4i32(ptr addrspace(1) %out, ptr addr
;
; GFX1250-LABEL: v_test_imax_sge_v4i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v4, 0
@ -166,6 +168,7 @@ define amdgpu_kernel void @s_test_imax_sge_i32(ptr addrspace(1) %out, i32 %a, i3
;
; GFX1250-LABEL: s_test_imax_sge_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -206,6 +209,7 @@ define amdgpu_kernel void @s_test_imax_sge_imm_i32(ptr addrspace(1) %out, i32 %a
;
; GFX1250-LABEL: s_test_imax_sge_imm_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -256,6 +260,7 @@ define amdgpu_kernel void @v_test_imax_sge_i8(ptr addrspace(1) %out, ptr addrspa
;
; GFX1250-LABEL: v_test_imax_sge_i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -327,6 +332,7 @@ define amdgpu_kernel void @s_test_imax_sgt_imm_i32(ptr addrspace(1) %out, i32 %a
;
; GFX1250-LABEL: s_test_imax_sgt_imm_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -369,6 +375,7 @@ define amdgpu_kernel void @s_test_imax_sgt_imm_v2i32(ptr addrspace(1) %out, <2 x
;
; GFX1250-LABEL: s_test_imax_sgt_imm_v2i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -421,6 +428,7 @@ define amdgpu_kernel void @v_test_imax_sgt_i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: v_test_imax_sgt_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
@ -481,6 +489,7 @@ define amdgpu_kernel void @s_test_imax_sgt_i32(ptr addrspace(1) %out, i32 %a, i3
;
; GFX1250-LABEL: s_test_imax_sgt_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -530,6 +539,7 @@ define amdgpu_kernel void @v_test_umax_uge_i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: v_test_umax_uge_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
@ -590,6 +600,7 @@ define amdgpu_kernel void @s_test_umax_uge_i32(ptr addrspace(1) %out, i32 %a, i3
;
; GFX1250-LABEL: s_test_umax_uge_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -636,6 +647,7 @@ define amdgpu_kernel void @s_test_umax_uge_v3i32(ptr addrspace(1) %out, <3 x i32
;
; GFX1250-LABEL: s_test_umax_uge_v3i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
@ -696,6 +708,7 @@ define amdgpu_kernel void @v_test_umax_uge_i8(ptr addrspace(1) %out, ptr addrspa
;
; GFX1250-LABEL: v_test_umax_uge_i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -766,6 +779,7 @@ define amdgpu_kernel void @v_test_umax_ugt_i32(ptr addrspace(1) %out, ptr addrsp
;
; GFX1250-LABEL: v_test_umax_ugt_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
@ -824,6 +838,7 @@ define amdgpu_kernel void @s_test_umax_ugt_i32(ptr addrspace(1) %out, i32 %a, i3
;
; GFX1250-LABEL: s_test_umax_ugt_i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -866,6 +881,7 @@ define amdgpu_kernel void @s_test_umax_ugt_imm_v2i32(ptr addrspace(1) %out, <2 x
;
; GFX1250-LABEL: s_test_umax_ugt_imm_v2i32:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
@ -914,6 +930,7 @@ define amdgpu_kernel void @simplify_demanded_bits_test_umax_ugt_i16(ptr addrspac
;
; GFX1250-LABEL: simplify_demanded_bits_test_umax_ugt_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x2
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x4c
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x70
@ -977,6 +994,7 @@ define amdgpu_kernel void @simplify_demanded_bits_test_max_slt_i16(ptr addrspace
;
; GFX1250-LABEL: simplify_demanded_bits_test_max_slt_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x2
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x4c
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x70
@ -1039,6 +1057,7 @@ define amdgpu_kernel void @s_test_imax_sge_i16(ptr addrspace(1) %out, [8 x i32],
;
; GFX1250-LABEL: s_test_imax_sge_i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x2
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x70
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x4c
@ -1113,6 +1132,7 @@ define amdgpu_kernel void @test_umax_ugt_i64(ptr addrspace(1) %out, i64 %a, i64
;
; GFX1250-LABEL: test_umax_ugt_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -1166,6 +1186,7 @@ define amdgpu_kernel void @test_umax_uge_i64(ptr addrspace(1) %out, i64 %a, i64
;
; GFX1250-LABEL: test_umax_uge_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -1219,6 +1240,7 @@ define amdgpu_kernel void @test_imax_sgt_i64(ptr addrspace(1) %out, i64 %a, i64
;
; GFX1250-LABEL: test_imax_sgt_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
@ -1272,6 +1294,7 @@ define amdgpu_kernel void @test_imax_sge_i64(ptr addrspace(1) %out, i64 %a, i64
;
; GFX1250-LABEL: test_imax_sge_i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34

3
llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
View File

@ -42,6 +42,7 @@ define amdgpu_kernel void @test_s_barrier() {
;
; GFX1250-LABEL: test_s_barrier:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_barrier_signal -1
; GFX1250-NEXT: s_barrier_wait -1
; GFX1250-NEXT: s_endpgm
@ -101,6 +102,7 @@ define amdgpu_kernel void @test_s_barrier_workgroup_fence() {
;
; GFX1250-LABEL: test_s_barrier_workgroup_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_barrier_signal -1
@ -163,6 +165,7 @@ define amdgpu_kernel void @test_s_barrier_agent_fence() {
;
; GFX1250-LABEL: test_s_barrier_agent_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0

24
llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
View File

@ -82,6 +82,7 @@ define amdgpu_kernel void @workgroup_acquire_fence() {
;
; GFX1250-LABEL: workgroup_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -163,6 +164,7 @@ define amdgpu_kernel void @workgroup_release_fence() {
;
; GFX1250-LABEL: workgroup_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -249,6 +251,7 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() {
;
; GFX1250-LABEL: workgroup_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -335,6 +338,7 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() {
;
; GFX1250-LABEL: workgroup_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -411,6 +415,7 @@ define amdgpu_kernel void @workgroup_one_as_acquire_fence() {
;
; GFX1250-LABEL: workgroup_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -492,6 +497,7 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() {
;
; GFX1250-LABEL: workgroup_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -578,6 +584,7 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: workgroup_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -664,6 +671,7 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: workgroup_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -762,6 +770,7 @@ define amdgpu_kernel void @agent_acquire_fence() {
;
; GFX1250-LABEL: agent_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
@ -851,6 +860,7 @@ define amdgpu_kernel void @agent_release_fence() {
;
; GFX1250-LABEL: agent_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -956,6 +966,7 @@ define amdgpu_kernel void @agent_acq_rel_fence() {
;
; GFX1250-LABEL: agent_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1062,6 +1073,7 @@ define amdgpu_kernel void @agent_seq_cst_fence() {
;
; GFX1250-LABEL: agent_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1162,6 +1174,7 @@ define amdgpu_kernel void @agent_one_as_acquire_fence() {
;
; GFX1250-LABEL: agent_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
@ -1251,6 +1264,7 @@ define amdgpu_kernel void @agent_one_as_release_fence() {
;
; GFX1250-LABEL: agent_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1356,6 +1370,7 @@ define amdgpu_kernel void @agent_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: agent_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1462,6 +1477,7 @@ define amdgpu_kernel void @agent_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: agent_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1564,6 +1580,7 @@ define amdgpu_kernel void @system_acquire_fence() {
;
; GFX1250-LABEL: system_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
@ -1657,6 +1674,7 @@ define amdgpu_kernel void @system_release_fence() {
;
; GFX1250-LABEL: system_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1768,6 +1786,7 @@ define amdgpu_kernel void @system_acq_rel_fence() {
;
; GFX1250-LABEL: system_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1880,6 +1899,7 @@ define amdgpu_kernel void @system_seq_cst_fence() {
;
; GFX1250-LABEL: system_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -1982,6 +2002,7 @@ define amdgpu_kernel void @system_one_as_acquire_fence() {
;
; GFX1250-LABEL: system_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
@ -2075,6 +2096,7 @@ define amdgpu_kernel void @system_one_as_release_fence() {
;
; GFX1250-LABEL: system_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -2186,6 +2208,7 @@ define amdgpu_kernel void @system_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: system_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -2298,6 +2321,7 @@ define amdgpu_kernel void @system_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: system_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0

24
llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
View File

@ -80,6 +80,7 @@ define amdgpu_kernel void @workgroup_acquire_fence() {
;
; GFX1250-LABEL: workgroup_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -153,6 +154,7 @@ define amdgpu_kernel void @workgroup_release_fence() {
;
; GFX1250-LABEL: workgroup_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -226,6 +228,7 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() {
;
; GFX1250-LABEL: workgroup_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -299,6 +302,7 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() {
;
; GFX1250-LABEL: workgroup_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -361,6 +365,7 @@ define amdgpu_kernel void @workgroup_one_as_acquire_fence() {
;
; GFX1250-LABEL: workgroup_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("workgroup-one-as") acquire, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -422,6 +427,7 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() {
;
; GFX1250-LABEL: workgroup_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("workgroup-one-as") release, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -483,6 +489,7 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: workgroup_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("workgroup-one-as") acq_rel, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -544,6 +551,7 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: workgroup_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("workgroup-one-as") seq_cst, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -616,6 +624,7 @@ define amdgpu_kernel void @agent_acquire_fence() {
;
; GFX1250-LABEL: agent_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -689,6 +698,7 @@ define amdgpu_kernel void @agent_release_fence() {
;
; GFX1250-LABEL: agent_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -762,6 +772,7 @@ define amdgpu_kernel void @agent_acq_rel_fence() {
;
; GFX1250-LABEL: agent_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -835,6 +846,7 @@ define amdgpu_kernel void @agent_seq_cst_fence() {
;
; GFX1250-LABEL: agent_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -897,6 +909,7 @@ define amdgpu_kernel void @agent_one_as_acquire_fence() {
;
; GFX1250-LABEL: agent_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("agent-one-as") acquire, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -958,6 +971,7 @@ define amdgpu_kernel void @agent_one_as_release_fence() {
;
; GFX1250-LABEL: agent_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("agent-one-as") release, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -1019,6 +1033,7 @@ define amdgpu_kernel void @agent_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: agent_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("agent-one-as") acq_rel, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -1080,6 +1095,7 @@ define amdgpu_kernel void @agent_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: agent_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("agent-one-as") seq_cst, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -1152,6 +1168,7 @@ define amdgpu_kernel void @system_acquire_fence() {
;
; GFX1250-LABEL: system_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -1225,6 +1242,7 @@ define amdgpu_kernel void @system_release_fence() {
;
; GFX1250-LABEL: system_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -1298,6 +1316,7 @@ define amdgpu_kernel void @system_acq_rel_fence() {
;
; GFX1250-LABEL: system_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -1371,6 +1390,7 @@ define amdgpu_kernel void @system_seq_cst_fence() {
;
; GFX1250-LABEL: system_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_endpgm
entry:
@ -1433,6 +1453,7 @@ define amdgpu_kernel void @system_one_as_acquire_fence() {
;
; GFX1250-LABEL: system_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("one-as") acquire, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -1494,6 +1515,7 @@ define amdgpu_kernel void @system_one_as_release_fence() {
;
; GFX1250-LABEL: system_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("one-as") release, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -1555,6 +1577,7 @@ define amdgpu_kernel void @system_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: system_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("one-as") acq_rel, !mmra !{!"amdgpu-synchronize-as", !"local"}
@ -1616,6 +1639,7 @@ define amdgpu_kernel void @system_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: system_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("one-as") seq_cst, !mmra !{!"amdgpu-synchronize-as", !"local"}

48
llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
View File

@ -69,6 +69,7 @@ define amdgpu_kernel void @singlethread_acquire_fence() {
;
; GFX1250-LABEL: singlethread_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread") acquire
@ -130,6 +131,7 @@ define amdgpu_kernel void @singlethread_release_fence() {
;
; GFX1250-LABEL: singlethread_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread") release
@ -191,6 +193,7 @@ define amdgpu_kernel void @singlethread_acq_rel_fence() {
;
; GFX1250-LABEL: singlethread_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread") acq_rel
@ -252,6 +255,7 @@ define amdgpu_kernel void @singlethread_seq_cst_fence() {
;
; GFX1250-LABEL: singlethread_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread") seq_cst
@ -313,6 +317,7 @@ define amdgpu_kernel void @singlethread_one_as_acquire_fence() {
;
; GFX1250-LABEL: singlethread_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread-one-as") acquire
@ -374,6 +379,7 @@ define amdgpu_kernel void @singlethread_one_as_release_fence() {
;
; GFX1250-LABEL: singlethread_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread-one-as") release
@ -435,6 +441,7 @@ define amdgpu_kernel void @singlethread_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: singlethread_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread-one-as") acq_rel
@ -496,6 +503,7 @@ define amdgpu_kernel void @singlethread_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: singlethread_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("singlethread-one-as") seq_cst
@ -557,6 +565,7 @@ define amdgpu_kernel void @wavefront_acquire_fence() {
;
; GFX1250-LABEL: wavefront_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront") acquire
@ -618,6 +627,7 @@ define amdgpu_kernel void @wavefront_release_fence() {
;
; GFX1250-LABEL: wavefront_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront") release
@ -679,6 +689,7 @@ define amdgpu_kernel void @wavefront_acq_rel_fence() {
;
; GFX1250-LABEL: wavefront_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront") acq_rel
@ -740,6 +751,7 @@ define amdgpu_kernel void @wavefront_seq_cst_fence() {
;
; GFX1250-LABEL: wavefront_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront") seq_cst
@ -801,6 +813,7 @@ define amdgpu_kernel void @wavefront_one_as_acquire_fence() {
;
; GFX1250-LABEL: wavefront_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront-one-as") acquire
@ -862,6 +875,7 @@ define amdgpu_kernel void @wavefront_one_as_release_fence() {
;
; GFX1250-LABEL: wavefront_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront-one-as") release
@ -923,6 +937,7 @@ define amdgpu_kernel void @wavefront_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: wavefront_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront-one-as") acq_rel
@ -984,6 +999,7 @@ define amdgpu_kernel void @wavefront_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: wavefront_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_endpgm
entry:
fence syncscope("wavefront-one-as") seq_cst
@ -1066,6 +1082,7 @@ define amdgpu_kernel void @workgroup_acquire_fence() {
;
; GFX1250-LABEL: workgroup_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1152,6 +1169,7 @@ define amdgpu_kernel void @workgroup_release_fence() {
;
; GFX1250-LABEL: workgroup_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1243,6 +1261,7 @@ define amdgpu_kernel void @workgroup_acq_rel_fence() {
;
; GFX1250-LABEL: workgroup_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1334,6 +1353,7 @@ define amdgpu_kernel void @workgroup_seq_cst_fence() {
;
; GFX1250-LABEL: workgroup_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1410,6 +1430,7 @@ define amdgpu_kernel void @workgroup_one_as_acquire_fence() {
;
; GFX1250-LABEL: workgroup_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1491,6 +1512,7 @@ define amdgpu_kernel void @workgroup_one_as_release_fence() {
;
; GFX1250-LABEL: workgroup_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1577,6 +1599,7 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: workgroup_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1663,6 +1686,7 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: workgroup_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1762,6 +1786,7 @@ define amdgpu_kernel void @cluster_acquire_fence() {
;
; GFX1250-LABEL: cluster_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SE
@ -1851,6 +1876,7 @@ define amdgpu_kernel void @cluster_release_fence() {
;
; GFX1250-LABEL: cluster_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_endpgm
@ -1955,6 +1981,7 @@ define amdgpu_kernel void @cluster_acq_rel_fence() {
;
; GFX1250-LABEL: cluster_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SE
@ -2060,6 +2087,7 @@ define amdgpu_kernel void @cluster_seq_cst_fence() {
;
; GFX1250-LABEL: cluster_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SE
@ -2159,6 +2187,7 @@ define amdgpu_kernel void @cluster_one_as_acquire_fence() {
;
; GFX1250-LABEL: cluster_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SE
@ -2248,6 +2277,7 @@ define amdgpu_kernel void @cluster_one_as_release_fence() {
;
; GFX1250-LABEL: cluster_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_endpgm
@ -2352,6 +2382,7 @@ define amdgpu_kernel void @cluster_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: cluster_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SE
@ -2457,6 +2488,7 @@ define amdgpu_kernel void @cluster_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: cluster_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SE
@ -2556,6 +2588,7 @@ define amdgpu_kernel void @agent_acquire_fence() {
;
; GFX1250-LABEL: agent_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
@ -2645,6 +2678,7 @@ define amdgpu_kernel void @agent_release_fence() {
;
; GFX1250-LABEL: agent_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
@ -2750,6 +2784,7 @@ define amdgpu_kernel void @agent_acq_rel_fence() {
;
; GFX1250-LABEL: agent_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
@ -2856,6 +2891,7 @@ define amdgpu_kernel void @agent_seq_cst_fence() {
;
; GFX1250-LABEL: agent_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
@ -2956,6 +2992,7 @@ define amdgpu_kernel void @agent_one_as_acquire_fence() {
;
; GFX1250-LABEL: agent_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
@ -3045,6 +3082,7 @@ define amdgpu_kernel void @agent_one_as_release_fence() {
;
; GFX1250-LABEL: agent_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -3150,6 +3188,7 @@ define amdgpu_kernel void @agent_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: agent_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -3256,6 +3295,7 @@ define amdgpu_kernel void @agent_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: agent_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -3358,6 +3398,7 @@ define amdgpu_kernel void @system_acquire_fence() {
;
; GFX1250-LABEL: system_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
@ -3451,6 +3492,7 @@ define amdgpu_kernel void @system_release_fence() {
;
; GFX1250-LABEL: system_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
@ -3562,6 +3604,7 @@ define amdgpu_kernel void @system_acq_rel_fence() {
;
; GFX1250-LABEL: system_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
@ -3674,6 +3717,7 @@ define amdgpu_kernel void @system_seq_cst_fence() {
;
; GFX1250-LABEL: system_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
@ -3776,6 +3820,7 @@ define amdgpu_kernel void @system_one_as_acquire_fence() {
;
; GFX1250-LABEL: system_one_as_acquire_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
@ -3869,6 +3914,7 @@ define amdgpu_kernel void @system_one_as_release_fence() {
;
; GFX1250-LABEL: system_one_as_release_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -3980,6 +4026,7 @@ define amdgpu_kernel void @system_one_as_acq_rel_fence() {
;
; GFX1250-LABEL: system_one_as_acq_rel_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
@ -4092,6 +4139,7 @@ define amdgpu_kernel void @system_one_as_seq_cst_fence() {
;
; GFX1250-LABEL: system_one_as_seq_cst_fence:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: global_wb scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0

92
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
View File

@ -191,6 +191,7 @@ define amdgpu_kernel void @flat_agent_unordered_load(
;
; GFX1250-LABEL: flat_agent_unordered_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -384,6 +385,7 @@ define amdgpu_kernel void @flat_agent_monotonic_load(
;
; GFX1250-LABEL: flat_agent_monotonic_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -592,6 +594,7 @@ define amdgpu_kernel void @flat_agent_acquire_load(
;
; GFX1250-LABEL: flat_agent_acquire_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -823,6 +826,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_load(
;
; GFX1250-LABEL: flat_agent_seq_cst_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -987,6 +991,7 @@ define amdgpu_kernel void @flat_agent_unordered_store(
;
; GFX1250-LABEL: flat_agent_unordered_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1147,6 +1152,7 @@ define amdgpu_kernel void @flat_agent_monotonic_store(
;
; GFX1250-LABEL: flat_agent_monotonic_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1331,6 +1337,7 @@ define amdgpu_kernel void @flat_agent_release_store(
;
; GFX1250-LABEL: flat_agent_release_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1518,6 +1525,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_store(
;
; GFX1250-LABEL: flat_agent_seq_cst_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1681,6 +1689,7 @@ define amdgpu_kernel void @flat_agent_monotonic_atomicrmw(
;
; GFX1250-LABEL: flat_agent_monotonic_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -1872,6 +1881,7 @@ define amdgpu_kernel void @flat_agent_acquire_atomicrmw(
;
; GFX1250-LABEL: flat_agent_acquire_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2058,6 +2068,7 @@ define amdgpu_kernel void @flat_agent_release_atomicrmw(
;
; GFX1250-LABEL: flat_agent_release_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2276,6 +2287,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_atomicrmw(
;
; GFX1250-LABEL: flat_agent_acq_rel_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2496,6 +2508,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_atomicrmw(
;
; GFX1250-LABEL: flat_agent_seq_cst_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2720,6 +2733,7 @@ define amdgpu_kernel void @flat_agent_acquire_ret_atomicrmw(
;
; GFX1250-LABEL: flat_agent_acquire_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2967,6 +2981,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_ret_atomicrmw(
;
; GFX1250-LABEL: flat_agent_acq_rel_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -3217,6 +3232,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_ret_atomicrmw(
;
; GFX1250-LABEL: flat_agent_seq_cst_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -3472,6 +3488,7 @@ define amdgpu_kernel void @flat_agent_monotonic_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_monotonic_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -3756,6 +3773,7 @@ define amdgpu_kernel void @flat_agent_acquire_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acquire_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4035,6 +4053,7 @@ define amdgpu_kernel void @flat_agent_release_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_release_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4346,6 +4365,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acq_rel_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4659,6 +4679,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_seq_cst_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4948,6 +4969,7 @@ define amdgpu_kernel void @flat_agent_monotonic_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_monotonic_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -5234,6 +5256,7 @@ define amdgpu_kernel void @flat_agent_acquire_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acquire_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -5544,6 +5567,7 @@ define amdgpu_kernel void @flat_agent_release_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_release_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -5857,6 +5881,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acq_rel_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -6170,6 +6195,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_seq_cst_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -6483,6 +6509,7 @@ define amdgpu_kernel void @flat_agent_monotonic_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_monotonic_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -6796,6 +6823,7 @@ define amdgpu_kernel void @flat_agent_acquire_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acquire_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -7109,6 +7137,7 @@ define amdgpu_kernel void @flat_agent_release_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_release_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -7422,6 +7451,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acq_rel_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -7735,6 +7765,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_seq_cst_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -8037,6 +8068,7 @@ define amdgpu_kernel void @flat_agent_monotonic_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_monotonic_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -8353,6 +8385,7 @@ define amdgpu_kernel void @flat_agent_acquire_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acquire_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -8679,6 +8712,7 @@ define amdgpu_kernel void @flat_agent_release_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_release_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9022,6 +9056,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acq_rel_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9366,6 +9401,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_seq_cst_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9686,6 +9722,7 @@ define amdgpu_kernel void @flat_agent_monotonic_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_monotonic_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -10003,6 +10040,7 @@ define amdgpu_kernel void @flat_agent_acquire_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acquire_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -10344,6 +10382,7 @@ define amdgpu_kernel void @flat_agent_release_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_release_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -10688,6 +10727,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acq_rel_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -11032,6 +11072,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_seq_cst_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -11376,6 +11417,7 @@ define amdgpu_kernel void @flat_agent_monotonic_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_monotonic_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -11720,6 +11762,7 @@ define amdgpu_kernel void @flat_agent_acquire_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acquire_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12064,6 +12107,7 @@ define amdgpu_kernel void @flat_agent_release_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_release_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12408,6 +12452,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_acq_rel_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12752,6 +12797,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_seq_cst_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12957,6 +13003,7 @@ define amdgpu_kernel void @flat_agent_one_as_unordered_load(
;
; GFX1250-LABEL: flat_agent_one_as_unordered_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13150,6 +13197,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_load(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13368,6 +13416,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_load(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13610,6 +13659,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_load(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13775,6 +13825,7 @@ define amdgpu_kernel void @flat_agent_one_as_unordered_store(
;
; GFX1250-LABEL: flat_agent_one_as_unordered_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -13935,6 +13986,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_store(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -14119,6 +14171,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_store(
;
; GFX1250-LABEL: flat_agent_one_as_release_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -14306,6 +14359,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_store(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -14469,6 +14523,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -14656,6 +14711,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -14842,6 +14898,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_release_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15056,6 +15113,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15272,6 +15330,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15506,6 +15565,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_ret_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15764,6 +15824,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_ret_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -16025,6 +16086,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_ret_atomicrmw(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -16281,6 +16343,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -16561,6 +16624,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -16840,6 +16904,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_release_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17147,6 +17212,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17456,6 +17522,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17741,6 +17808,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18023,6 +18091,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18329,6 +18398,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_release_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18638,6 +18708,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18947,6 +19018,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -19256,6 +19328,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -19565,6 +19638,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -19874,6 +19948,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_release_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -20183,6 +20258,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -20492,6 +20568,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -20794,6 +20871,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -21120,6 +21198,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -21447,6 +21526,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_release_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -21800,6 +21880,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -22155,6 +22236,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -22486,6 +22568,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -22814,6 +22897,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -23166,6 +23250,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_release_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -23521,6 +23606,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -23876,6 +23962,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -24231,6 +24318,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_monotonic_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -24586,6 +24674,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acquire_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -24941,6 +25030,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_release_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -25296,6 +25386,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_acq_rel_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -25651,6 +25742,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8

92
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
View File

@ -191,6 +191,7 @@ define amdgpu_kernel void @flat_cluster_unordered_load(
;
; GFX1250-LABEL: flat_cluster_unordered_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -384,6 +385,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_load(
;
; GFX1250-LABEL: flat_cluster_monotonic_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -592,6 +594,7 @@ define amdgpu_kernel void @flat_cluster_acquire_load(
;
; GFX1250-LABEL: flat_cluster_acquire_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -823,6 +826,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_load(
;
; GFX1250-LABEL: flat_cluster_seq_cst_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -987,6 +991,7 @@ define amdgpu_kernel void @flat_cluster_unordered_store(
;
; GFX1250-LABEL: flat_cluster_unordered_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1147,6 +1152,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_store(
;
; GFX1250-LABEL: flat_cluster_monotonic_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1331,6 +1337,7 @@ define amdgpu_kernel void @flat_cluster_release_store(
;
; GFX1250-LABEL: flat_cluster_release_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1517,6 +1524,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_store(
;
; GFX1250-LABEL: flat_cluster_seq_cst_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -1679,6 +1687,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_monotonic_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -1870,6 +1879,7 @@ define amdgpu_kernel void @flat_cluster_acquire_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_acquire_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2056,6 +2066,7 @@ define amdgpu_kernel void @flat_cluster_release_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_release_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2273,6 +2284,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_acq_rel_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2492,6 +2504,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_seq_cst_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2715,6 +2728,7 @@ define amdgpu_kernel void @flat_cluster_acquire_ret_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_acquire_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -2962,6 +2976,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_ret_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_acq_rel_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -3211,6 +3226,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_ret_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_seq_cst_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -3465,6 +3481,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_monotonic_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -3749,6 +3766,7 @@ define amdgpu_kernel void @flat_cluster_acquire_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acquire_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4028,6 +4046,7 @@ define amdgpu_kernel void @flat_cluster_release_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_release_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4338,6 +4357,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acq_rel_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4650,6 +4670,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_seq_cst_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -4938,6 +4959,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_monotonic_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -5224,6 +5246,7 @@ define amdgpu_kernel void @flat_cluster_acquire_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acquire_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -5534,6 +5557,7 @@ define amdgpu_kernel void @flat_cluster_release_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_release_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -5846,6 +5870,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acq_rel_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -6158,6 +6183,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_seq_cst_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -6470,6 +6496,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_monotonic_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -6782,6 +6809,7 @@ define amdgpu_kernel void @flat_cluster_acquire_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acquire_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -7094,6 +7122,7 @@ define amdgpu_kernel void @flat_cluster_release_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_release_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -7406,6 +7435,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acq_rel_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -7718,6 +7748,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_seq_cst_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -8019,6 +8050,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_monotonic_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -8335,6 +8367,7 @@ define amdgpu_kernel void @flat_cluster_acquire_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acquire_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -8661,6 +8694,7 @@ define amdgpu_kernel void @flat_cluster_release_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_release_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9003,6 +9037,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acq_rel_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9346,6 +9381,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_seq_cst_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9665,6 +9701,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_monotonic_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -9982,6 +10019,7 @@ define amdgpu_kernel void @flat_cluster_acquire_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acquire_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -10323,6 +10361,7 @@ define amdgpu_kernel void @flat_cluster_release_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_release_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -10666,6 +10705,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acq_rel_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -11009,6 +11049,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_seq_cst_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -11352,6 +11393,7 @@ define amdgpu_kernel void @flat_cluster_monotonic_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_monotonic_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -11695,6 +11737,7 @@ define amdgpu_kernel void @flat_cluster_acquire_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acquire_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12038,6 +12081,7 @@ define amdgpu_kernel void @flat_cluster_release_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_release_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12381,6 +12425,7 @@ define amdgpu_kernel void @flat_cluster_acq_rel_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_acq_rel_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12724,6 +12769,7 @@ define amdgpu_kernel void @flat_cluster_seq_cst_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_seq_cst_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -12928,6 +12974,7 @@ define amdgpu_kernel void @flat_cluster_one_as_unordered_load(
;
; GFX1250-LABEL: flat_cluster_one_as_unordered_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13121,6 +13168,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_load(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13339,6 +13387,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_load(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13581,6 +13630,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_load(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -13746,6 +13796,7 @@ define amdgpu_kernel void @flat_cluster_one_as_unordered_store(
;
; GFX1250-LABEL: flat_cluster_one_as_unordered_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -13906,6 +13957,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_store(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -14090,6 +14142,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_store(
;
; GFX1250-LABEL: flat_cluster_one_as_release_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -14276,6 +14329,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_store(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_store:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
@ -14438,6 +14492,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -14625,6 +14680,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -14811,6 +14867,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_release_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15024,6 +15081,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15239,6 +15297,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15472,6 +15531,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_ret_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15730,6 +15790,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_ret_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -15990,6 +16051,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_ret_atomicrmw(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_ret_atomicrmw:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x8
@ -16245,6 +16307,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -16525,6 +16588,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -16804,6 +16868,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_release_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17110,6 +17175,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17418,6 +17484,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_monotonic_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_monotonic_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17702,6 +17769,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -17984,6 +18052,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18290,6 +18359,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_release_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18598,6 +18668,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -18906,6 +18977,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_acquire_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_acquire_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -19214,6 +19286,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -19522,6 +19595,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -19830,6 +19904,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_release_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -20138,6 +20213,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -20446,6 +20522,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_seq_cst_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_seq_cst_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -20747,6 +20824,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -21073,6 +21151,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -21400,6 +21479,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_release_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -21752,6 +21832,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -22106,6 +22187,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_monotonic_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_monotonic_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -22436,6 +22518,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -22764,6 +22847,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -23116,6 +23200,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_release_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -23470,6 +23555,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -23824,6 +23910,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_acquire_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_acquire_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -24178,6 +24265,7 @@ define amdgpu_kernel void @flat_cluster_one_as_monotonic_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_monotonic_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -24532,6 +24620,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acquire_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acquire_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -24886,6 +24975,7 @@ define amdgpu_kernel void @flat_cluster_one_as_release_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_release_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -25240,6 +25330,7 @@ define amdgpu_kernel void @flat_cluster_one_as_acq_rel_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_acq_rel_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8
@ -25594,6 +25685,7 @@ define amdgpu_kernel void @flat_cluster_one_as_seq_cst_seq_cst_ret_cmpxchg(
;
; GFX1250-LABEL: flat_cluster_one_as_seq_cst_seq_cst_ret_cmpxchg:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x8

4
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
View File

@ -20,6 +20,7 @@ define amdgpu_kernel void @flat_last_use_load_0(ptr %in, ptr %out) {
;
; GFX1250-LABEL: flat_last_use_load_0:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -68,6 +69,7 @@ define amdgpu_kernel void @flat_last_use_load_1(ptr %in, ptr %out) {
;
; GFX1250-LABEL: flat_last_use_load_1:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v1, v0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -108,6 +110,7 @@ define amdgpu_kernel void @flat_last_use_and_volatile_load(ptr %in, ptr %out) {
;
; GFX1250-LABEL: flat_last_use_and_volatile_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
@ -139,6 +142,7 @@ define amdgpu_kernel void @flat_last_use_and_nontemporal_load(ptr %in, ptr %out)
;
; GFX1250-LABEL: flat_last_use_and_nontemporal_load:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8

Some files were not shown because too many files have changed in this diff Show More