AMDGPU: Simplify foldImmediate with register class based checks
Generalize the code over the properties of the mov instruction, rather than maintaining parallel logic to figure out the type of mov to use. I've maintained the behavior with 16-bit physical SGPRs, though I think the behavior here is broken and corrupting any value that happens to be live in the high bits. It just happens there's no way to separately write to those with a real instruction but I don't think we should be trying to make assumptions around that property. This is NFC-ish. It now does a better job with imm pseudos which practically won't reach here. This also will make it easier to support more folds in a future patch. I added a couple of new tests with 16-bit extract of 64-bit sources. The only other test change is an immediate rendering change from zero extended to sign extended.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
d2b810e24f
commit
a32d42e594
@ -3573,54 +3573,93 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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assert(!UseMI.getOperand(0).getSubReg() && "Expected SSA form");
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Register DstReg = UseMI.getOperand(0).getReg();
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unsigned OpSize = getOpSize(UseMI, 0);
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bool Is16Bit = OpSize == 2;
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bool Is64Bit = OpSize == 8;
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bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
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unsigned NewOpc = isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO
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: AMDGPU::V_MOV_B32_e32
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: Is64Bit ? AMDGPU::S_MOV_B64_IMM_PSEUDO
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: AMDGPU::S_MOV_B32;
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Register UseSubReg = UseMI.getOperand(1).getSubReg();
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std::optional<int64_t> SubRegImm =
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extractSubregFromImm(Imm, UseMI.getOperand(1).getSubReg());
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const TargetRegisterClass *DstRC = RI.getRegClassForReg(*MRI, DstReg);
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APInt Imm(Is64Bit ? 64 : 32, *SubRegImm,
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/*isSigned=*/true, /*implicitTrunc=*/true);
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if (RI.isAGPR(*MRI, DstReg)) {
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if (Is64Bit || !isInlineConstant(Imm))
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return false;
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NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32_e64;
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}
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bool Is16Bit = UseSubReg != AMDGPU::NoSubRegister &&
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RI.getSubRegIdxSize(UseSubReg) == 16;
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if (Is16Bit) {
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if (isVGPRCopy)
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if (RI.hasVGPRs(DstRC))
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return false; // Do not clobber vgpr_hi16
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if (DstReg.isVirtual() && UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
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if (DstReg.isVirtual() && UseSubReg != AMDGPU::lo16)
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return false;
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UseMI.getOperand(0).setSubReg(0);
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if (DstReg.isPhysical()) {
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DstReg = RI.get32BitRegister(DstReg);
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UseMI.getOperand(0).setReg(DstReg);
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}
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assert(UseMI.getOperand(1).getReg().isVirtual());
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}
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MachineFunction *MF = UseMI.getMF();
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const MCInstrDesc &NewMCID = get(NewOpc);
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const TargetRegisterClass *NewDefRC = getRegClass(NewMCID, 0, &RI, *MF);
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if (DstReg.isPhysical()) {
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if (!NewDefRC->contains(DstReg))
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return false;
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} else if (!MRI->constrainRegClass(DstReg, NewDefRC))
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unsigned NewOpc = AMDGPU::INSTRUCTION_LIST_END;
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MCRegister MovDstPhysReg =
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DstReg.isPhysical() ? MCRegister(DstReg) : MCRegister();
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std::optional<int64_t> SubRegImm = extractSubregFromImm(Imm, UseSubReg);
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// TODO: Try to fold with AMDGPU::V_MOV_B16_t16_e64
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for (unsigned MovOp :
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{AMDGPU::S_MOV_B32, AMDGPU::V_MOV_B32_e32, AMDGPU::S_MOV_B64,
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AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_ACCVGPR_WRITE_B32_e64}) {
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const MCInstrDesc &MovDesc = get(MovOp);
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const TargetRegisterClass *MovDstRC = getRegClass(MovDesc, 0, &RI, *MF);
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if (Is16Bit) {
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// We just need to find a correctly sized register class, so the
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// subregister index compatibility doesn't matter since we're statically
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// extracting the immediate value.
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MovDstRC = RI.getMatchingSuperRegClass(MovDstRC, DstRC, AMDGPU::lo16);
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if (!MovDstRC)
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continue;
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if (MovDstPhysReg) {
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// FIXME: We probably should not do this. If there is a live value in
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// the high half of the register, it will be corrupted.
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MovDstPhysReg = RI.getMatchingSuperReg(MCRegister(DstReg),
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AMDGPU::lo16, MovDstRC);
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if (!MovDstPhysReg)
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continue;
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}
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}
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// Result class isn't the right size, try the next instruction.
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if (MovDstPhysReg) {
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if (!MovDstRC->contains(MovDstPhysReg))
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return false;
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} else if (!MRI->constrainRegClass(DstReg, MovDstRC)) {
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// TODO: This will be overly conservative in the case of 16-bit virtual
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// SGPRs. We could hack up the virtual register uses to use a compatible
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// 32-bit class.
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continue;
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}
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const MCOperandInfo &OpInfo = MovDesc.operands()[1];
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// Ensure the interpreted immediate value is a valid operand in the new
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// mov.
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//
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// FIXME: isImmOperandLegal should have form that doesn't require existing
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// MachineInstr or MachineOperand
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if (!RI.opCanUseLiteralConstant(OpInfo.OperandType) &&
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!isInlineConstant(*SubRegImm, OpInfo.OperandType))
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break;
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NewOpc = MovOp;
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break;
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}
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if (NewOpc == AMDGPU::INSTRUCTION_LIST_END)
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return false;
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if (Is16Bit) {
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UseMI.getOperand(0).setSubReg(AMDGPU::NoSubRegister);
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if (MovDstPhysReg)
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UseMI.getOperand(0).setReg(MovDstPhysReg);
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assert(UseMI.getOperand(1).getReg().isVirtual());
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}
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const MCInstrDesc &NewMCID = get(NewOpc);
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UseMI.setDesc(NewMCID);
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UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
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UseMI.getOperand(1).ChangeToImmediate(*SubRegImm);
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UseMI.addImplicitDefUseOperands(*MF);
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return true;
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}
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@ -188,8 +188,7 @@ body: |
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; GCN-LABEL: name: fold_sreg_64_to_sreg_64
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; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1311768467750121200
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; GCN-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
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; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_MOV_B]]
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; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_MOV_B64_]]
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%0:sreg_64 = S_MOV_B64 1311768467750121200
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%1:sreg_64 = COPY killed %0
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SI_RETURN_TO_EPILOG %1
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@ -761,8 +760,8 @@ body: |
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bb.0:
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; GCN-LABEL: name: fold_av_mov_b32_imm_pseudo_inlineimm_to_av
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; GCN: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 64, implicit $exec
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; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY killed [[AV_MOV_]]
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; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[COPY]]
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; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 64, implicit $exec
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; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[V_MOV_B32_e32_]]
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%0:av_32 = AV_MOV_B32_IMM_PSEUDO 64, implicit $exec
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%1:av_32 = COPY killed %0
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SI_RETURN_TO_EPILOG implicit %1
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@ -800,9 +799,67 @@ body: |
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bb.0:
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; GCN-LABEL: name: fold_av_mov_b64_imm_pseudo_inlineimm_to_av
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; GCN: [[AV_MOV_:%[0-9]+]]:av_64_align2 = AV_MOV_B64_IMM_PSEUDO 64, implicit $exec
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; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY killed [[AV_MOV_]]
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; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[COPY]]
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; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 64, implicit $exec
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; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[V_MOV_B]]
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%0:av_64_align2 = AV_MOV_B64_IMM_PSEUDO 64, implicit $exec
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%1:av_64_align2 = COPY killed %0
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SI_RETURN_TO_EPILOG implicit %1
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...
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---
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name: fold_simm_16_sub_to_lo_from_mov_64_virt_sgpr16
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_lo_from_mov_64_virt_sgpr16
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; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 64
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; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B64_]].lo16
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; GCN-NEXT: SI_RETURN_TO_EPILOG [[COPY]]
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%0:sreg_64 = S_MOV_B64 64
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%1:sgpr_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_virt_sgpr16
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_virt_sgpr16
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; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 64
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; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B64_]].hi16
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; GCN-NEXT: SI_RETURN_TO_EPILOG [[COPY]]
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%0:sreg_64 = S_MOV_B64 64
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%1:sgpr_lo16 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_lo_from_mov_64_phys_sgpr16_lo
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_lo_from_mov_64_phys_sgpr16_lo
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; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 64
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; GCN-NEXT: $sgpr0 = S_MOV_B32 64
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; GCN-NEXT: SI_RETURN_TO_EPILOG $sgpr0_lo16
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%0:sreg_64 = S_MOV_B64 64
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$sgpr0_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG $sgpr0_lo16
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...
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---
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name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_phys_sgpr16_lo
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_phys_sgpr16_lo
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; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 64
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; GCN-NEXT: $sgpr0 = S_MOV_B32 0
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; GCN-NEXT: SI_RETURN_TO_EPILOG $sgpr0_lo16
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%0:sreg_64 = S_MOV_B64 64
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$sgpr0_lo16 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG $sgpr0_lo16
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...
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