[AArch64] Cleanup existing values in getMemOpInfo (#98196)
This patch tries to clean up some of the existing values in getMemOpInfo. All values should now be in bytes (not bits), and the MinOffset/MaxOffset are now always represented unscaled (the immediate that will be present in the final instruction). Although I could not find a place where it altered codegen, the offset of a post-index instruction will be 0, not scale*imm. A IsPostIndexLdStOpcode method has been added to try and make sure that case is handled properly.
This commit is contained in:
David Green
GitHub
parent
5f696c1bd9
commit
a3cf8642bf
@ -1487,7 +1487,8 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
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// If the first store isn't right where we want SP then we can't fold the
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// update in so create a normal arithmetic instruction instead.
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if (MBBI->getOperand(MBBI->getNumOperands() - 1).getImm() != 0 ||
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CSStackSizeInc < MinOffset || CSStackSizeInc > MaxOffset) {
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CSStackSizeInc < MinOffset * (int64_t)Scale.getFixedValue() ||
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CSStackSizeInc > MaxOffset * (int64_t)Scale.getFixedValue()) {
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// If we are destroying the frame, make sure we add the increment after the
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// last frame operation.
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if (FrameFlag == MachineInstr::FrameDestroy)
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@ -3487,6 +3487,229 @@ MachineInstr *AArch64InstrInfo::emitLdStWithAddr(MachineInstr &MemI,
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"Function must not be called with an addressing mode it can't handle");
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}
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/// Return true if the opcode is a post-index ld/st instruction, which really
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/// loads from base+0.
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static bool isPostIndexLdStOpcode(unsigned Opcode) {
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switch (Opcode) {
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default:
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return false;
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case AArch64::LD1Fourv16b_POST:
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case AArch64::LD1Fourv1d_POST:
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case AArch64::LD1Fourv2d_POST:
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case AArch64::LD1Fourv2s_POST:
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case AArch64::LD1Fourv4h_POST:
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case AArch64::LD1Fourv4s_POST:
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case AArch64::LD1Fourv8b_POST:
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case AArch64::LD1Fourv8h_POST:
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case AArch64::LD1Onev16b_POST:
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case AArch64::LD1Onev1d_POST:
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case AArch64::LD1Onev2d_POST:
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case AArch64::LD1Onev2s_POST:
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case AArch64::LD1Onev4h_POST:
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case AArch64::LD1Onev4s_POST:
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case AArch64::LD1Onev8b_POST:
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case AArch64::LD1Onev8h_POST:
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case AArch64::LD1Rv16b_POST:
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case AArch64::LD1Rv1d_POST:
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case AArch64::LD1Rv2d_POST:
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case AArch64::LD1Rv2s_POST:
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case AArch64::LD1Rv4h_POST:
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case AArch64::LD1Rv4s_POST:
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case AArch64::LD1Rv8b_POST:
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case AArch64::LD1Rv8h_POST:
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case AArch64::LD1Threev16b_POST:
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case AArch64::LD1Threev1d_POST:
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case AArch64::LD1Threev2d_POST:
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case AArch64::LD1Threev2s_POST:
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case AArch64::LD1Threev4h_POST:
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case AArch64::LD1Threev4s_POST:
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case AArch64::LD1Threev8b_POST:
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case AArch64::LD1Threev8h_POST:
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case AArch64::LD1Twov16b_POST:
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case AArch64::LD1Twov1d_POST:
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case AArch64::LD1Twov2d_POST:
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case AArch64::LD1Twov2s_POST:
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case AArch64::LD1Twov4h_POST:
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case AArch64::LD1Twov4s_POST:
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case AArch64::LD1Twov8b_POST:
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case AArch64::LD1Twov8h_POST:
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case AArch64::LD1i16_POST:
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case AArch64::LD1i32_POST:
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case AArch64::LD1i64_POST:
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case AArch64::LD1i8_POST:
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case AArch64::LD2Rv16b_POST:
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case AArch64::LD2Rv1d_POST:
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case AArch64::LD2Rv2d_POST:
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case AArch64::LD2Rv2s_POST:
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case AArch64::LD2Rv4h_POST:
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case AArch64::LD2Rv4s_POST:
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case AArch64::LD2Rv8b_POST:
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case AArch64::LD2Rv8h_POST:
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case AArch64::LD2Twov16b_POST:
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case AArch64::LD2Twov2d_POST:
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case AArch64::LD2Twov2s_POST:
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case AArch64::LD2Twov4h_POST:
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case AArch64::LD2Twov4s_POST:
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case AArch64::LD2Twov8b_POST:
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case AArch64::LD2Twov8h_POST:
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case AArch64::LD2i16_POST:
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case AArch64::LD2i32_POST:
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case AArch64::LD2i64_POST:
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case AArch64::LD2i8_POST:
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case AArch64::LD3Rv16b_POST:
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case AArch64::LD3Rv1d_POST:
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case AArch64::LD3Rv2d_POST:
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case AArch64::LD3Rv2s_POST:
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case AArch64::LD3Rv4h_POST:
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case AArch64::LD3Rv4s_POST:
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case AArch64::LD3Rv8b_POST:
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case AArch64::LD3Rv8h_POST:
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case AArch64::LD3Threev16b_POST:
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case AArch64::LD3Threev2d_POST:
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case AArch64::LD3Threev2s_POST:
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case AArch64::LD3Threev4h_POST:
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case AArch64::LD3Threev4s_POST:
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case AArch64::LD3Threev8b_POST:
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case AArch64::LD3Threev8h_POST:
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case AArch64::LD3i16_POST:
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case AArch64::LD3i32_POST:
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case AArch64::LD3i64_POST:
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case AArch64::LD3i8_POST:
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case AArch64::LD4Fourv16b_POST:
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case AArch64::LD4Fourv2d_POST:
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case AArch64::LD4Fourv2s_POST:
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case AArch64::LD4Fourv4h_POST:
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case AArch64::LD4Fourv4s_POST:
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case AArch64::LD4Fourv8b_POST:
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case AArch64::LD4Fourv8h_POST:
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case AArch64::LD4Rv16b_POST:
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case AArch64::LD4Rv1d_POST:
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case AArch64::LD4Rv2d_POST:
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case AArch64::LD4Rv2s_POST:
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case AArch64::LD4Rv4h_POST:
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case AArch64::LD4Rv4s_POST:
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case AArch64::LD4Rv8b_POST:
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case AArch64::LD4Rv8h_POST:
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case AArch64::LD4i16_POST:
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case AArch64::LD4i32_POST:
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case AArch64::LD4i64_POST:
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case AArch64::LD4i8_POST:
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case AArch64::LDAPRWpost:
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case AArch64::LDAPRXpost:
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case AArch64::LDIAPPWpost:
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case AArch64::LDIAPPXpost:
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case AArch64::LDPDpost:
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case AArch64::LDPQpost:
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case AArch64::LDPSWpost:
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case AArch64::LDPSpost:
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case AArch64::LDPWpost:
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case AArch64::LDPXpost:
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case AArch64::LDRBBpost:
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case AArch64::LDRBpost:
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case AArch64::LDRDpost:
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case AArch64::LDRHHpost:
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case AArch64::LDRHpost:
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case AArch64::LDRQpost:
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case AArch64::LDRSBWpost:
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case AArch64::LDRSBXpost:
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case AArch64::LDRSHWpost:
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case AArch64::LDRSHXpost:
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case AArch64::LDRSWpost:
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case AArch64::LDRSpost:
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case AArch64::LDRWpost:
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case AArch64::LDRXpost:
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case AArch64::ST1Fourv16b_POST:
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case AArch64::ST1Fourv1d_POST:
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case AArch64::ST1Fourv2d_POST:
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case AArch64::ST1Fourv2s_POST:
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case AArch64::ST1Fourv4h_POST:
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case AArch64::ST1Fourv4s_POST:
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case AArch64::ST1Fourv8b_POST:
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case AArch64::ST1Fourv8h_POST:
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case AArch64::ST1Onev16b_POST:
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case AArch64::ST1Onev1d_POST:
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case AArch64::ST1Onev2d_POST:
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case AArch64::ST1Onev2s_POST:
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case AArch64::ST1Onev4h_POST:
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case AArch64::ST1Onev4s_POST:
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case AArch64::ST1Onev8b_POST:
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case AArch64::ST1Onev8h_POST:
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case AArch64::ST1Threev16b_POST:
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case AArch64::ST1Threev1d_POST:
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case AArch64::ST1Threev2d_POST:
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case AArch64::ST1Threev2s_POST:
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case AArch64::ST1Threev4h_POST:
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case AArch64::ST1Threev4s_POST:
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case AArch64::ST1Threev8b_POST:
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case AArch64::ST1Threev8h_POST:
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case AArch64::ST1Twov16b_POST:
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case AArch64::ST1Twov1d_POST:
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case AArch64::ST1Twov2d_POST:
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case AArch64::ST1Twov2s_POST:
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case AArch64::ST1Twov4h_POST:
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case AArch64::ST1Twov4s_POST:
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case AArch64::ST1Twov8b_POST:
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case AArch64::ST1Twov8h_POST:
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case AArch64::ST1i16_POST:
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case AArch64::ST1i32_POST:
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case AArch64::ST1i64_POST:
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case AArch64::ST1i8_POST:
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case AArch64::ST2GPostIndex:
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case AArch64::ST2Twov16b_POST:
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case AArch64::ST2Twov2d_POST:
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case AArch64::ST2Twov2s_POST:
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case AArch64::ST2Twov4h_POST:
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case AArch64::ST2Twov4s_POST:
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case AArch64::ST2Twov8b_POST:
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case AArch64::ST2Twov8h_POST:
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case AArch64::ST2i16_POST:
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case AArch64::ST2i32_POST:
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case AArch64::ST2i64_POST:
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case AArch64::ST2i8_POST:
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case AArch64::ST3Threev16b_POST:
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case AArch64::ST3Threev2d_POST:
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case AArch64::ST3Threev2s_POST:
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case AArch64::ST3Threev4h_POST:
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case AArch64::ST3Threev4s_POST:
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case AArch64::ST3Threev8b_POST:
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case AArch64::ST3Threev8h_POST:
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case AArch64::ST3i16_POST:
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case AArch64::ST3i32_POST:
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case AArch64::ST3i64_POST:
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case AArch64::ST3i8_POST:
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case AArch64::ST4Fourv16b_POST:
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case AArch64::ST4Fourv2d_POST:
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case AArch64::ST4Fourv2s_POST:
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case AArch64::ST4Fourv4h_POST:
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case AArch64::ST4Fourv4s_POST:
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case AArch64::ST4Fourv8b_POST:
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case AArch64::ST4Fourv8h_POST:
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case AArch64::ST4i16_POST:
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case AArch64::ST4i32_POST:
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case AArch64::ST4i64_POST:
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case AArch64::ST4i8_POST:
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case AArch64::STGPostIndex:
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case AArch64::STGPpost:
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case AArch64::STPDpost:
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case AArch64::STPQpost:
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case AArch64::STPSpost:
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case AArch64::STPWpost:
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case AArch64::STPXpost:
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case AArch64::STRBBpost:
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case AArch64::STRBpost:
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case AArch64::STRDpost:
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case AArch64::STRHHpost:
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case AArch64::STRHpost:
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case AArch64::STRQpost:
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case AArch64::STRSpost:
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case AArch64::STRWpost:
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case AArch64::STRXpost:
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case AArch64::STZ2GPostIndex:
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case AArch64::STZGPostIndex:
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return true;
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}
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}
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bool AArch64InstrInfo::getMemOperandWithOffsetWidth(
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const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
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bool &OffsetIsScalable, TypeSize &Width,
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@ -3518,8 +3741,11 @@ bool AArch64InstrInfo::getMemOperandWithOffsetWidth(
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// Compute the offset. Offset is calculated as the immediate operand
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// multiplied by the scaling factor. Unscaled instructions have scaling factor
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// set to 1.
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if (LdSt.getNumExplicitOperands() == 3) {
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// set to 1. Postindex are a special case which have an offset of 0.
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if (isPostIndexLdStOpcode(LdSt.getOpcode())) {
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BaseOp = &LdSt.getOperand(2);
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Offset = 0;
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} else if (LdSt.getNumExplicitOperands() == 3) {
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BaseOp = &LdSt.getOperand(1);
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Offset = LdSt.getOperand(2).getImm() * Scale.getKnownMinValue();
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} else {
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@ -3529,10 +3755,7 @@ bool AArch64InstrInfo::getMemOperandWithOffsetWidth(
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}
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OffsetIsScalable = Scale.isScalable();
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if (!BaseOp->isReg() && !BaseOp->isFI())
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return false;
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return true;
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return BaseOp->isReg() || BaseOp->isFI();
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}
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MachineOperand &
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@ -3622,8 +3845,8 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
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break;
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case AArch64::STRWpost:
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case AArch64::LDRWpost:
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Scale = TypeSize::getFixed(4);
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Width = TypeSize::getFixed(32);
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Scale = TypeSize::getFixed(1);
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Width = TypeSize::getFixed(4);
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MinOffset = -256;
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MaxOffset = 255;
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break;
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@ -3690,13 +3913,15 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
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MinOffset = -256;
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MaxOffset = 255;
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break;
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// LDP / STP
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// LDP / STP (including pre/post inc)
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case AArch64::LDPQi:
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case AArch64::LDNPQi:
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case AArch64::STPQi:
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case AArch64::STNPQi:
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case AArch64::STPQpre:
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case AArch64::LDPQpost:
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Scale = TypeSize::getFixed(16);
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Width = TypeSize::getFixed(32);
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Width = TypeSize::getFixed(16 * 2);
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MinOffset = -64;
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MaxOffset = 63;
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break;
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@ -3708,8 +3933,12 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
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case AArch64::STPDi:
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case AArch64::STNPXi:
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case AArch64::STNPDi:
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case AArch64::STPXpre:
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case AArch64::LDPXpost:
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case AArch64::STPDpre:
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case AArch64::LDPDpost:
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Scale = TypeSize::getFixed(8);
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Width = TypeSize::getFixed(16);
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Width = TypeSize::getFixed(8 * 2);
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MinOffset = -64;
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MaxOffset = 63;
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break;
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@ -3722,27 +3951,10 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
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case AArch64::STNPWi:
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case AArch64::STNPSi:
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Scale = TypeSize::getFixed(4);
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Width = TypeSize::getFixed(8);
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Width = TypeSize::getFixed(4 * 2);
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MinOffset = -64;
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MaxOffset = 63;
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break;
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// pre/post inc
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case AArch64::STPQpre:
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case AArch64::LDPQpost:
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Scale = TypeSize::getFixed(16);
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Width = TypeSize::getFixed(16);
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MinOffset = -1024;
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MaxOffset = 1008;
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break;
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case AArch64::STPXpre:
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case AArch64::LDPXpost:
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case AArch64::STPDpre:
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case AArch64::LDPDpost:
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Scale = TypeSize::getFixed(8);
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Width = TypeSize::getFixed(8);
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MinOffset = -512;
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MaxOffset = 504;
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break;
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case AArch64::StoreSwiftAsyncContext:
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// Store is an STRXui, but there might be an ADDXri in the expansion too.
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Scale = TypeSize::getFixed(1);
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@ -317,7 +317,10 @@ public:
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/// Returns true if opcode \p Opc is a memory operation. If it is, set
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/// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
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///
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/// For unscaled instructions, \p Scale is set to 1.
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/// For unscaled instructions, \p Scale is set to 1. All values are in bytes.
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/// MinOffset/MaxOffset are the un-scaled limits of the immediate in the
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/// instruction, the actual offset limit is [MinOffset*Scale,
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/// MaxOffset*Scale].
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static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width,
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int64_t &MinOffset, int64_t &MaxOffset);
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63
llvm/test/CodeGen/AArch64/sched-postidxalias.mir
Normal file
63
llvm/test/CodeGen/AArch64/sched-postidxalias.mir
Normal file
@ -0,0 +1,63 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Both the accesses should have an offset of 0
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# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)
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# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
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target triple = "aarch64"
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define ptr @post(ptr %p, i32 %d1, i32 %d2) {
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entry:
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%d3 = mul i32 %d1, %d2
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%q = getelementptr i64, ptr %p, i64 3
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%r = getelementptr i64, ptr %p, i64 3
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store i32 %d3, ptr %p, align 8
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%0 = load i32, ptr %r, align 8
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store i32 %d1, ptr %p, align 8
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%add.ptr = getelementptr inbounds i8, ptr %p, i64 24
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ret ptr %add.ptr
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}
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...
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---
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name: post
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gpr64common, preferred-register: '' }
|
||||
- { id: 1, class: gpr32, preferred-register: '' }
|
||||
- { id: 2, class: gpr32, preferred-register: '' }
|
||||
- { id: 3, class: gpr32, preferred-register: '' }
|
||||
- { id: 4, class: gpr64common, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$x0', virtual-reg: '%0' }
|
||||
- { reg: '$w1', virtual-reg: '%1' }
|
||||
- { reg: '$w2', virtual-reg: '%2' }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0, $w1, $w2
|
||||
|
||||
; CHECK-LABEL: name: post
|
||||
; CHECK: liveins: $x0, $w1, $w2
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w2
|
||||
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
||||
; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY]], $wzr
|
||||
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
|
||||
; CHECK-NEXT: STRWui [[MADDWrrr]], [[COPY2]], 0 :: (store (s32) into %ir.p, align 8)
|
||||
; CHECK-NEXT: early-clobber [[COPY2]]:gpr64common = STRWpost [[COPY1]], [[COPY2]], 24 :: (store (s32) into %ir.p, align 8)
|
||||
; CHECK-NEXT: $x0 = COPY [[COPY2]]
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
||||
%2:gpr32 = COPY $w2
|
||||
%1:gpr32 = COPY $w1
|
||||
%4:gpr64common = COPY $x0
|
||||
%3:gpr32 = MADDWrrr %1, %2, $wzr
|
||||
STRWui %3, %4, 0 :: (store (s32) into %ir.p, align 8)
|
||||
early-clobber %4:gpr64common = STRWpost %1, %4, 24 :: (store (s32) into %ir.p, align 8)
|
||||
$x0 = COPY %4
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user