AMDGPU: Teach lowering that sqrt never returns subnormal (#174838)
This commit is contained in:
Matt Arsenault
GitHub
parent
3665de766f
commit
a470e708be
@ -2635,6 +2635,7 @@ static bool valueIsKnownNeverF32Denorm(SDValue Src) {
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return Src.getOperand(0).getValueType() == MVT::f16;
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case ISD::FP16_TO_FP:
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case ISD::FFREXP:
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case ISD::FSQRT:
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case AMDGPUISD::LOG:
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case AMDGPUISD::EXP:
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return true;
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@ -2645,6 +2646,7 @@ static bool valueIsKnownNeverF32Denorm(SDValue Src) {
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case Intrinsic::amdgcn_log:
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case Intrinsic::amdgcn_log_clamp:
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case Intrinsic::amdgcn_exp2:
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case Intrinsic::amdgcn_sqrt:
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return true;
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default:
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return false;
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@ -3410,6 +3410,7 @@ static bool valueIsKnownNeverF32Denorm(const MachineRegisterInfo &MRI,
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case Intrinsic::amdgcn_log:
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case Intrinsic::amdgcn_log_clamp:
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case Intrinsic::amdgcn_exp2:
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case Intrinsic::amdgcn_sqrt:
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return true;
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default:
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break;
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@ -3417,6 +3418,8 @@ static bool valueIsKnownNeverF32Denorm(const MachineRegisterInfo &MRI,
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break;
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}
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case TargetOpcode::G_FSQRT:
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return true;
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case TargetOpcode::G_FFREXP: {
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if (DefMI->getOperand(0).getReg() == Src)
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return true;
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@ -4852,6 +4852,211 @@ define float @v_sqrt_f32__amdgcn_log_known_not_denorm(float %x) {
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ret float %result
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}
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define float @v_sqrt_f32__sqrt_known_not_denorm(float %x) {
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; SDAG-IEEE-LABEL: v_sqrt_f32__sqrt_known_not_denorm:
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; SDAG-IEEE: ; %bb.0:
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; SDAG-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-IEEE-NEXT: s_mov_b32 s6, 0xf800000
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; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
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; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v0
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; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
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; SDAG-IEEE-NEXT: v_sqrt_f32_e32 v1, v0
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; SDAG-IEEE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1
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; SDAG-IEEE-NEXT: v_fma_f32 v3, -v2, v1, v0
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; SDAG-IEEE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3
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; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]
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; SDAG-IEEE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1
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; SDAG-IEEE-NEXT: v_fma_f32 v1, -v3, v1, v0
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; SDAG-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1
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; SDAG-IEEE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]
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; SDAG-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
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; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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; SDAG-IEEE-NEXT: v_mov_b32_e32 v2, 0x260
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; SDAG-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
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; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
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; SDAG-IEEE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v0
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; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
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; SDAG-IEEE-NEXT: v_rsq_f32_e32 v1, v0
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; SDAG-IEEE-NEXT: v_mul_f32_e32 v3, v0, v1
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; SDAG-IEEE-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; SDAG-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 0.5
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; SDAG-IEEE-NEXT: v_fma_f32 v3, v3, v4, v3
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; SDAG-IEEE-NEXT: v_fma_f32 v5, -v3, v3, v0
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; SDAG-IEEE-NEXT: v_fma_f32 v1, v1, v4, v1
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; SDAG-IEEE-NEXT: v_fma_f32 v1, v5, v1, v3
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; SDAG-IEEE-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
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; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; SDAG-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
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; SDAG-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; SDAG-IEEE-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-IEEE-LABEL: v_sqrt_f32__sqrt_known_not_denorm:
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; GISEL-IEEE: ; %bb.0:
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; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0xf800000
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; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0
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; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
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; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-IEEE-NEXT: v_sqrt_f32_e32 v2, v0
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; GISEL-IEEE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v2
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; GISEL-IEEE-NEXT: v_fma_f32 v4, -v3, v2, v0
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; GISEL-IEEE-NEXT: v_add_i32_e64 v5, s[4:5], 1, v2
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; GISEL-IEEE-NEXT: v_fma_f32 v6, -v5, v2, v0
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; GISEL-IEEE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v4
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; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
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; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v6
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; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
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; GISEL-IEEE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2
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; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
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; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, 0x260
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; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3
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; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0
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; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
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; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-IEEE-NEXT: v_rsq_f32_e32 v1, v0
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; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, v0, v1
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; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GISEL-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 0.5
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; GISEL-IEEE-NEXT: v_fma_f32 v2, v2, v4, v2
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; GISEL-IEEE-NEXT: v_fma_f32 v1, v1, v4, v1
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; GISEL-IEEE-NEXT: v_fma_f32 v4, -v2, v2, v0
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; GISEL-IEEE-NEXT: v_fma_f32 v1, v4, v1, v2
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; GISEL-IEEE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
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; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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; GISEL-IEEE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3
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; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GISEL-IEEE-NEXT: s_setpc_b64 s[30:31]
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;
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; SDAG-DAZ-LABEL: v_sqrt_f32__sqrt_known_not_denorm:
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; SDAG-DAZ: ; %bb.0:
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; SDAG-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-DAZ-NEXT: s_mov_b32 s4, 0xf800000
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
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; SDAG-DAZ-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
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; SDAG-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
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; SDAG-DAZ-NEXT: v_rsq_f32_e32 v1, v0
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; SDAG-DAZ-NEXT: v_fma_f32 v3, -v1, v2, 0.5
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; SDAG-DAZ-NEXT: v_fma_f32 v2, v2, v3, v2
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; SDAG-DAZ-NEXT: v_fma_f32 v4, -v2, v2, v0
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; SDAG-DAZ-NEXT: v_fma_f32 v1, v1, v3, v1
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; SDAG-DAZ-NEXT: v_fma_f32 v1, v4, v1, v2
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
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; SDAG-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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; SDAG-DAZ-NEXT: v_mov_b32_e32 v2, 0x260
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; SDAG-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
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; SDAG-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
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; SDAG-DAZ-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
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; SDAG-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
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; SDAG-DAZ-NEXT: v_rsq_f32_e32 v1, v0
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v3, v0, v1
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; SDAG-DAZ-NEXT: v_fma_f32 v4, -v1, v3, 0.5
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; SDAG-DAZ-NEXT: v_fma_f32 v3, v3, v4, v3
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; SDAG-DAZ-NEXT: v_fma_f32 v5, -v3, v3, v0
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; SDAG-DAZ-NEXT: v_fma_f32 v1, v1, v4, v1
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; SDAG-DAZ-NEXT: v_fma_f32 v1, v5, v1, v3
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; SDAG-DAZ-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
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; SDAG-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; SDAG-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
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; SDAG-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; SDAG-DAZ-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-DAZ-LABEL: v_sqrt_f32__sqrt_known_not_denorm:
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; GISEL-DAZ: ; %bb.0:
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; GISEL-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-DAZ-NEXT: v_mov_b32_e32 v1, 0xf800000
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0
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; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
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; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-DAZ-NEXT: v_rsq_f32_e32 v2, v0
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, v0, v2
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0.5, v2
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; GISEL-DAZ-NEXT: v_fma_f32 v4, -v2, v3, 0.5
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; GISEL-DAZ-NEXT: v_fma_f32 v3, v3, v4, v3
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; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v4, v2
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; GISEL-DAZ-NEXT: v_fma_f32 v4, -v3, v3, v0
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; GISEL-DAZ-NEXT: v_fma_f32 v2, v4, v2, v3
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v3, 0x37800000, v2
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; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
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; GISEL-DAZ-NEXT: v_mov_b32_e32 v3, 0x260
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; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v3
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; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0
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; GISEL-DAZ-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
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; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-DAZ-NEXT: v_rsq_f32_e32 v1, v0
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, v0, v1
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GISEL-DAZ-NEXT: v_fma_f32 v4, -v1, v2, 0.5
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; GISEL-DAZ-NEXT: v_fma_f32 v2, v2, v4, v2
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; GISEL-DAZ-NEXT: v_fma_f32 v1, v1, v4, v1
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; GISEL-DAZ-NEXT: v_fma_f32 v4, -v2, v2, v0
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; GISEL-DAZ-NEXT: v_fma_f32 v1, v4, v1, v2
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; GISEL-DAZ-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
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; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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; GISEL-DAZ-NEXT: v_cmp_class_f32_e32 vcc, v0, v3
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; GISEL-DAZ-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GISEL-DAZ-NEXT: s_setpc_b64 s[30:31]
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%sqrt0 = call float @llvm.sqrt.f32(float %x)
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%result = call float @llvm.sqrt.f32(float %sqrt0)
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ret float %result
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}
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define float @v_sqrt_f32__amdgcn_sqrt_known_not_denorm(float %x) {
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; SDAG-LABEL: v_sqrt_f32__amdgcn_sqrt_known_not_denorm:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: v_sqrt_f32_e32 v0, v0
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; SDAG-NEXT: s_mov_b32 s4, 0xf800000
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; SDAG-NEXT: v_mov_b32_e32 v2, 0x260
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; SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
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; SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
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; SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
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; SDAG-NEXT: v_rsq_f32_e32 v1, v0
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; SDAG-NEXT: v_mul_f32_e32 v3, v0, v1
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; SDAG-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; SDAG-NEXT: v_fma_f32 v4, -v1, v3, 0.5
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; SDAG-NEXT: v_fma_f32 v3, v3, v4, v3
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; SDAG-NEXT: v_fma_f32 v1, v1, v4, v1
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; SDAG-NEXT: v_fma_f32 v4, -v3, v3, v0
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; SDAG-NEXT: v_fma_f32 v1, v4, v1, v3
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; SDAG-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
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; SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
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; SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: v_sqrt_f32__amdgcn_sqrt_known_not_denorm:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: v_sqrt_f32_e32 v0, v0
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; GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000
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; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0
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; GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
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; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-NEXT: v_rsq_f32_e32 v1, v0
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; GISEL-NEXT: v_mov_b32_e32 v2, 0x260
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; GISEL-NEXT: v_mul_f32_e32 v3, v0, v1
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; GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GISEL-NEXT: v_fma_f32 v4, -v1, v3, 0.5
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; GISEL-NEXT: v_fma_f32 v3, v3, v4, v3
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; GISEL-NEXT: v_fma_f32 v1, v1, v4, v1
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; GISEL-NEXT: v_fma_f32 v4, -v3, v3, v0
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; GISEL-NEXT: v_fma_f32 v1, v4, v1, v3
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; GISEL-NEXT: v_mul_f32_e32 v3, 0x37800000, v1
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; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2
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; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%sqrt0 = call float @llvm.amdgcn.sqrt.f32(float %x)
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%result = call float @llvm.sqrt.f32(float %sqrt0)
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ret float %result
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}
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declare float @llvm.fabs.f32(float) #0
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declare float @llvm.sqrt.f32(float) #0
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