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[NewPM] Adds a port for AArch64ExpandPseudo (#187332)

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Adds a port for AArch64ExpandPseudo to NewPM.

- Refactored lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp to extract
base logic as Impl
- Renamed existing pass with "Legacy" suffix and updated references
- Added NewPM pass AArch64ExpandPseudoPass
- Updated tests

Following tests mention this pass but weren't migrated because they need
a full codegen pipeline which doesn't exist yet.

```
  LLVM :: CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
  LLVM :: CodeGen/AArch64/addg_subg.mir
  LLVM :: CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
  LLVM :: CodeGen/AArch64/spillfill-sve.mir
  LLVM :: CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir
```
This commit is contained in:
Anshul Nigham 2026-03-18 15:22:10 -07:00 committed by GitHub
parent ca07ca0314
commit a67c3b7468
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
20 changed files with 95 additions and 55 deletions
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10
llvm/lib/Target/AArch64/AArch64.h
View File

@ -42,7 +42,7 @@ FunctionPass *createAArch64AdvSIMDScalar();
FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
CodeGenOptLevel OptLevel);
FunctionPass *createAArch64StorePairSuppressPass();
FunctionPass *createAArch64ExpandPseudoPass();
FunctionPass *createAArch64ExpandPseudoLegacyPass();
FunctionPass *createAArch64SLSHardeningPass();
FunctionPass *createAArch64SpeculationHardeningPass();
FunctionPass *createAArch64LoadStoreOptLegacyPass();
@ -94,7 +94,7 @@ void initializeAArch64ConditionOptimizerLegacyPass(PassRegistry &);
void initializeAArch64ConditionalComparesPass(PassRegistry &);
void initializeAArch64DAGToDAGISelLegacyPass(PassRegistry &);
void initializeAArch64DeadRegisterDefinitionsLegacyPass(PassRegistry &);
void initializeAArch64ExpandPseudoPass(PassRegistry &);
void initializeAArch64ExpandPseudoLegacyPass(PassRegistry &);
void initializeAArch64LoadStoreOptLegacyPass(PassRegistry &);
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &);
void initializeAArch64MIPeepholeOptPass(PassRegistry &);
@ -169,6 +169,12 @@ public:
MachineFunctionAnalysisManager &MFAM);
};
class AArch64ExpandPseudoPass : public PassInfoMixin<AArch64ExpandPseudoPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
class AArch64ConditionOptimizerPass
: public PassInfoMixin<AArch64ConditionOptimizerPass> {
public:

118
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View File

@ -45,17 +45,11 @@ using namespace llvm;
namespace {
class AArch64ExpandPseudo : public MachineFunctionPass {
class AArch64ExpandPseudoImpl {
public:
const AArch64InstrInfo *TII;
static char ID;
AArch64ExpandPseudo() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &Fn) override;
StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME; }
bool run(MachineFunction &MF);
private:
bool expandMBB(MachineBasicBlock &MBB);
@ -113,11 +107,22 @@ private:
MachineBasicBlock::iterator MBBI);
};
class AArch64ExpandPseudoLegacy : public MachineFunctionPass {
public:
static char ID;
AArch64ExpandPseudoLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME; }
};
} // end anonymous namespace
char AArch64ExpandPseudo::ID = 0;
char AArch64ExpandPseudoLegacy::ID = 0;
INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
INITIALIZE_PASS(AArch64ExpandPseudoLegacy, "aarch64-expand-pseudo",
AARCH64_EXPAND_PSEUDO_NAME, false, false)
/// Transfer implicit operands on the pseudo instruction to the
@ -137,9 +142,9 @@ static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
/// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
/// real move-immediate instructions to synthesize the immediate.
bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned BitSize) {
bool AArch64ExpandPseudoImpl::expandMOVImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned BitSize) {
MachineInstr &MI = *MBBI;
Register DstReg = MI.getOperand(0).getReg();
RegState RenamableState =
@ -249,7 +254,7 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
return true;
}
bool AArch64ExpandPseudo::expandCMP_SWAP(
bool AArch64ExpandPseudoImpl::expandCMP_SWAP(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp,
unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
MachineBasicBlock::iterator &NextMBBI) {
@ -329,7 +334,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
return true;
}
bool AArch64ExpandPseudo::expandCMP_SWAP_128(
bool AArch64ExpandPseudoImpl::expandCMP_SWAP_128(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
@ -503,10 +508,9 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
/// or that they are undef (don't care / not used), otherwise the
/// swapping of operands is illegal because the operation is not
/// (or cannot be emulated to be) fully commutative.
bool AArch64ExpandPseudo::expand_DestructiveOp(
MachineInstr &MI,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
bool AArch64ExpandPseudoImpl::expand_DestructiveOp(
MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
unsigned Opcode = AArch64::getSVEPseudoMap(MI.getOpcode());
uint64_t DType = TII->get(Opcode).TSFlags & AArch64::DestructiveInstTypeMask;
uint64_t FalseLanes = MI.getDesc().TSFlags & AArch64::FalseLanesMask;
@ -714,7 +718,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
return true;
}
bool AArch64ExpandPseudo::expandSVEBitwisePseudo(
bool AArch64ExpandPseudoImpl::expandSVEBitwisePseudo(
MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
MachineInstrBuilder PRFX, DOP;
@ -782,7 +786,7 @@ bool AArch64ExpandPseudo::expandSVEBitwisePseudo(
return true;
}
bool AArch64ExpandPseudo::expandSetTagLoop(
bool AArch64ExpandPseudoImpl::expandSetTagLoop(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
@ -859,9 +863,9 @@ bool AArch64ExpandPseudo::expandSetTagLoop(
return true;
}
bool AArch64ExpandPseudo::expandSVESpillFill(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned Opc, unsigned N) {
bool AArch64ExpandPseudoImpl::expandSVESpillFill(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Opc,
unsigned N) {
assert((Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI ||
Opc == AArch64::LDR_PXI || Opc == AArch64::STR_PXI) &&
"Unexpected opcode");
@ -933,7 +937,7 @@ static MachineInstr *createCall(MachineBasicBlock &MBB,
return createCallWithOps(MBB, MBBI, TII, Opc, CallTarget, RegMaskStartIdx);
}
bool AArch64ExpandPseudo::expandCALL_RVMARKER(
bool AArch64ExpandPseudoImpl::expandCALL_RVMARKER(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
// Expand CALL_RVMARKER pseudo to:
// - a branch to the call target, followed by
@ -989,8 +993,8 @@ bool AArch64ExpandPseudo::expandCALL_RVMARKER(
return true;
}
bool AArch64ExpandPseudo::expandCALL_BTI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
bool AArch64ExpandPseudoImpl::expandCALL_BTI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
// Expand CALL_BTI pseudo to:
// - a branch to the call target
// - a BTI instruction
@ -1017,7 +1021,7 @@ bool AArch64ExpandPseudo::expandCALL_BTI(MachineBasicBlock &MBB,
return true;
}
bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext(
bool AArch64ExpandPseudoImpl::expandStoreSwiftAsyncContext(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
Register CtxReg = MBBI->getOperand(0).getReg();
Register BaseReg = MBBI->getOperand(1).getReg();
@ -1074,7 +1078,7 @@ bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext(
return true;
}
bool AArch64ExpandPseudo::expandSTSHHAtomicStore(
bool AArch64ExpandPseudoImpl::expandSTSHHAtomicStore(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL(MI.getDebugLoc());
@ -1139,11 +1143,10 @@ bool AArch64ExpandPseudo::expandSTSHHAtomicStore(
return true;
}
AArch64ExpandPseudo::ConditionalBlocks
AArch64ExpandPseudo::expandConditionalPseudo(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
DebugLoc DL,
MachineInstrBuilder &Branch) {
AArch64ExpandPseudoImpl::ConditionalBlocks
AArch64ExpandPseudoImpl::expandConditionalPseudo(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
MachineInstrBuilder &Branch) {
assert((std::next(MBBI) != MBB.end() ||
MBB.successors().begin() != MBB.successors().end()) &&
"Unexpected unreachable in block");
@ -1172,8 +1175,8 @@ AArch64ExpandPseudo::expandConditionalPseudo(MachineBasicBlock &MBB,
}
MachineBasicBlock *
AArch64ExpandPseudo::expandRestoreZASave(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
AArch64ExpandPseudoImpl::expandRestoreZASave(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@ -1198,8 +1201,8 @@ AArch64ExpandPseudo::expandRestoreZASave(MachineBasicBlock &MBB,
static constexpr unsigned ZERO_ALL_ZA_MASK = 0b11111111;
MachineBasicBlock *
AArch64ExpandPseudo::expandCommitZASave(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
AArch64ExpandPseudoImpl::expandCommitZASave(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
[[maybe_unused]] auto *RI = MBB.getParent()->getSubtarget().getRegisterInfo();
@ -1238,8 +1241,8 @@ AArch64ExpandPseudo::expandCommitZASave(MachineBasicBlock &MBB,
}
MachineBasicBlock *
AArch64ExpandPseudo::expandCondSMToggle(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
AArch64ExpandPseudoImpl::expandCondSMToggle(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
// In the case of a smstart/smstop before a unreachable, just remove the pseudo.
// Exception handling code generated by Clang may introduce unreachables and it
@ -1324,7 +1327,7 @@ AArch64ExpandPseudo::expandCondSMToggle(MachineBasicBlock &MBB,
return &EndBB;
}
bool AArch64ExpandPseudo::expandMultiVecPseudo(
bool AArch64ExpandPseudoImpl::expandMultiVecPseudo(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
TargetRegisterClass ContiguousClass, TargetRegisterClass StridedClass,
unsigned ContiguousOp, unsigned StridedOpc) {
@ -1351,7 +1354,7 @@ bool AArch64ExpandPseudo::expandMultiVecPseudo(
return true;
}
bool AArch64ExpandPseudo::expandFormTuplePseudo(
bool AArch64ExpandPseudoImpl::expandFormTuplePseudo(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI, unsigned Size) {
assert((Size == 2 || Size == 4) && "Invalid Tuple Size");
@ -1379,9 +1382,9 @@ bool AArch64ExpandPseudo::expandFormTuplePseudo(
/// If MBBI references a pseudo instruction that should be expanded here,
/// do the expansion and return true. Otherwise return false.
bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
bool AArch64ExpandPseudoImpl::expandMI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
unsigned Opcode = MI.getOpcode();
@ -2007,7 +2010,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
/// Iterate over the instructions in basic block MBB and expand any
/// pseudo instructions. Return true if anything was modified.
bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
bool AArch64ExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
bool Modified = false;
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
@ -2020,7 +2023,7 @@ bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
return Modified;
}
bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
bool AArch64ExpandPseudoImpl::run(MachineFunction &MF) {
TII = MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
bool Modified = false;
@ -2029,7 +2032,22 @@ bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
/// Returns an instance of the pseudo instruction expansion pass.
FunctionPass *llvm::createAArch64ExpandPseudoPass() {
return new AArch64ExpandPseudo();
bool AArch64ExpandPseudoLegacy::runOnMachineFunction(MachineFunction &MF) {
return AArch64ExpandPseudoImpl().run(MF);
}
/// Returns an instance of the pseudo instruction expansion pass.
FunctionPass *llvm::createAArch64ExpandPseudoLegacyPass() {
return new AArch64ExpandPseudoLegacy();
}
PreservedAnalyses
AArch64ExpandPseudoPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
const bool Changed = AArch64ExpandPseudoImpl().run(MF);
if (!Changed)
return PreservedAnalyses::all();
PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
return PA;
}

1
llvm/lib/Target/AArch64/AArch64PassRegistry.def
View File

@ -30,6 +30,7 @@ MACHINE_FUNCTION_PASS("aarch64-branch-targets", AArch64BranchTargetsPass())
MACHINE_FUNCTION_PASS("aarch64-collect-loh", AArch64CollectLOHPass())
MACHINE_FUNCTION_PASS("aarch64-condopt", AArch64ConditionOptimizerPass())
MACHINE_FUNCTION_PASS("aarch64-dead-defs", AArch64DeadRegisterDefinitionsPass())
MACHINE_FUNCTION_PASS("aarch64-expand-pseudo", AArch64ExpandPseudoPass())
MACHINE_FUNCTION_PASS("aarch64-fix-cortex-a53-835769", AArch64A53Fix835769Pass())
MACHINE_FUNCTION_PASS("aarch64-jump-tables", AArch64CompressJumpTablesPass())
MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())

4
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -253,7 +253,7 @@ LLVMInitializeAArch64Target() {
initializeAArch64ConditionalComparesPass(PR);
initializeAArch64ConditionOptimizerLegacyPass(PR);
initializeAArch64DeadRegisterDefinitionsLegacyPass(PR);
initializeAArch64ExpandPseudoPass(PR);
initializeAArch64ExpandPseudoLegacyPass(PR);
initializeAArch64LoadStoreOptLegacyPass(PR);
initializeAArch64MIPeepholeOptPass(PR);
initializeAArch64SIMDInstrOptPass(PR);
@ -875,7 +875,7 @@ void AArch64PassConfig::addPreSched2() {
if (EnableHomogeneousPrologEpilog)
addPass(createAArch64LowerHomogeneousPrologEpilogPass());
// Expand some pseudo instructions to allow proper scheduling.
addPass(createAArch64ExpandPseudoPass());
addPass(createAArch64ExpandPseudoLegacyPass());
// Use load/store pair instructions when possible.
if (TM->getOptLevel() != CodeGenOptLevel::None) {
if (EnableLoadStoreOpt)

1
llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=aarch64-expand-pseudo -o - %s | FileCheck %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -passes=aarch64-expand-pseudo -o - %s | FileCheck %s
# When expanding a BLR_BTI, we should copy all the operands to the branch in the
# bundle. Otherwise we could end up using a register after the BL which was

1
llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
---

1
llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=arm64-apple-ios -o - -emit-call-site-info %s -verify-machineinstrs | FileCheck %s
# RUN: llc -passes=aarch64-expand-pseudo -mtriple=arm64-apple-ios -o - -emit-call-site-info %s | FileCheck %s
--- |
define void @test_1_callsite_info() {

1
llvm/test/CodeGen/AArch64/expand-constructive-zzi.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -mattr=+sve -run-pass=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -mattr=+sve -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
# Test the expansion of constructive binary operations into their
# destructive counterparts.

1
llvm/test/CodeGen/AArch64/expand-load-got-pseudo.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
# RUN: llc -passes=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
# This testcase was obtained by looking at FileCheck.cpp and reducing it down via llvm-reduce

1
llvm/test/CodeGen/AArch64/expand-movi-renamable.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=arm64-apple-darwin -o - %s | FileCheck %s
# RUN: llc -passes=aarch64-expand-pseudo -mtriple=arm64-apple-darwin -o - %s | FileCheck %s
# Check that we preserve renamble when expanding MOVi32imm/MOVi64imm.
#

1
llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
# RUN: llc -passes=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
---

1
llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
# RUN: llc -passes=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
---
# CHECK-LABEL: name: test

1
llvm/test/CodeGen/AArch64/movimm-expand-ldst.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64 -verify-machineinstrs -run-pass=aarch64-expand-pseudo -run-pass=aarch64-ldst-opt -debug-only=aarch64-ldst-opt %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -passes=aarch64-expand-pseudo,aarch64-ldst-opt -debug-only=aarch64-ldst-opt %s -o - | FileCheck %s
# REQUIRES: asserts
---
name: test_fold_repeating_constant_load

1
llvm/test/CodeGen/AArch64/movimm-wzr.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
# RUN: llc -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
--- |
; ModuleID = 'simple.ll'

1
llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
# Should create an additional LSL to zero the lanes as the DstReg is not unique

1
llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
# Should create an additional LSL to zero the lanes as the DstReg is not unique

1
llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
# Should create an additional LSL to zero the lanes as the DstReg is not unique

1
llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=aarch64-expand-pseudo -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -passes=aarch64-expand-pseudo -simplify-mir %s -o - | FileCheck %s
---
name: add_x
alignment: 4

1
llvm/test/CodeGen/AArch64/sve2-bitsel-pseudos-expansion.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -mattr=+sve2 -run-pass=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -mattr=+sve2 -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
---
name: eon_destructive

2
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
View File

@ -302,7 +302,7 @@ private:
void addTargetSpecificPasses(PassManagerBase &PM) const override {
// Function return is a pseudo-instruction that needs to be expanded
PM.add(createAArch64ExpandPseudoPass());
PM.add(createAArch64ExpandPseudoLegacyPass());
}
};