shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

[lldb] Support both RISCV-32 and RISCV-64 in GetRegisterInfo (#176472)

Browse Source 
`GetRegisterInfo` hardcodes to use `RegisterInfoPOSIX_riscv64` instead
of checking the triple to determine whether to use
`RegisterInfoPOSIX_riscv64` or `RegisterInfoPOSIX_riscv32`.

Someone put up a [PR](https://github.com/llvm/llvm-project/pull/175262)
for this, but seems to have removed their account and the associated PR
with it.

Fixes #175092
This commit is contained in:
Jonas Devlieghere 2026-01-16 15:24:25 -08:00 committed by GitHub
parent a3a8e82e88
commit a84d74355e
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 36 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
View File

@ -7,6 +7,8 @@
//===----------------------------------------------------------------------===//
#include "EmulateInstructionRISCV.h"
#include "Plugins/Process/Utility/RegisterInfoInterface.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
@ -1837,10 +1839,23 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
}
}
RegisterInfoPOSIX_riscv64 reg_info(m_arch,
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
const RegisterInfo *array = reg_info.GetRegisterInfo();
const uint32_t length = reg_info.GetRegisterCount();
std::unique_ptr<RegisterInfoInterface> reg_info;
switch (m_arch.GetTriple().getArch()) {
case llvm::Triple::riscv32:
reg_info = std::make_unique<RegisterInfoPOSIX_riscv32>(
m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
break;
case llvm::Triple::riscv64:
reg_info = std::make_unique<RegisterInfoPOSIX_riscv64>(
m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
break;
default:
assert(false && "unsupported triple");
return {};
}
const RegisterInfo *array = reg_info->GetRegisterInfo();
const uint32_t length = reg_info->GetRegisterCount();
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};

17
lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
View File

@ -16,6 +16,7 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) {
ASSERT_TRUE(this->Execute(*decode, false));
ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits);
}
TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) {
// Test that GetRegisterInfo returns valid register info for riscv64.
auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
ASSERT_TRUE(reg_info.has_value());
ASSERT_EQ(reg_info->byte_size, 8u);
ASSERT_STREQ(reg_info->name, "ra");
}
TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) {
// Test that GetRegisterInfo returns valid register info for riscv32.
auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv);
ASSERT_TRUE(reg_info.has_value());
ASSERT_EQ(reg_info->byte_size, 4u);
ASSERT_STREQ(reg_info->name, "ra");
}